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Claims  |
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What is claimed is:
1. A low power input buffer, comprising:
(a) an input node, an output node, a power supply node, and a ground node,
said power supply node adapted to be electrically coupled to a power
supply selected from the group consisting of a battery-powered power
supply or a signal powered power supply;
(b) a first inverter having a signal input and an output and a second
inverter having a signal input and an output, the signal input of said
first inverter electrically coupled to said input node, the output of said
first inverter electrically coupled to the signal input of said second
inverter, and the output of second inverter electrically coupled to said
output node;
(c) said first inverter with power input electrically coupled through a
first resistor to said power supply node; and
(d) said second inverter with power input electrically coupled to said
power supply node.
2. The buffer of claim 1, wherein:
(a) said first resistor comprises a p-channel field effect transistor with
a gate electrically coupled to said ground node.
3. The buffer of claim 1, wherein:
(a) said first inverter comprises a first p-channel field effect transistor
having a gate, drain, and source and a first n-channel field effect
transistor having a gate and a drain, said gate of said first p-channel
field effect transistor electrically coupled to said first inverter signal
input and said drain of said first p-channel field effect transistor
electrically coupled to the drain of said first n-channel field effect
transistor, the gate of said first n-channel field effect transistor
electrically coupled to said first inverter signal input, and said first
resistor electrically coupling the source of said first p-channel field
effect transistor to said power supply node.
4. The buffer of claim 3, further comprising:
(a) said first n-channel field effect transistor having a source; and
(b) a second resistor electrically coupling the source of said first
n-channel field effect transistor to said ground node.
5. The buffer of claim 4, wherein:
(a) said first inverter comprises (i) a second p-channel field effect
transistor having a gate, drain, and source, said gate of said second
p-channel field effect transistor electrically coupled to said first
inverter signal input, said source of said second p-channel field effect
transistor electrically coupled to said drain of said first p-channel
field effect transistor, said drain of said second p-channel field effect
transistor electrically coupled to the output of said first inverter and
to the drain of a second n-channel field effect transistor, said second
n-channel field effect transistor with gate electrically coupled to said
first inverter signal input and with source electrically coupled to said
drain of said first n-channel field effect transistor, (ii) a third
p-channel field effect transistor having a drain, source, and gate, said
gate of said third p-channel field effect transistor electrically coupled
to said first inverter output, with source of said third p-channel field
effect transistor electrically coupled to said first p-channel field
effect transistor source, and with drain of said third p-channel field
effect transistor electrically coupled to said source of said first
n-channel field effect transistor, and (iii) a third n-channel field
effect transistor having a gate, source, and drain, said gate of said
third n-channel field effect transistor electrically coupled to said first
inverter output, with source of said third n-channel field effect
transistor electrically coupled to said source of said first n-channel
field effect transistor, and said drain of said third n-channel field
effect transistor electrically coupled to said source of said first
p-channel field effect transistor, whereby said first inverter has input
hysteresis circuit electrically coupled between said signal input and said
output.
6. The buffer of claim 5, further comprising:
(a) a third inverter having a signal input and an output, said third
inverter electrically coupled between said first and second inverters with
signal input electrically coupled to said output of said first inverter
and with output electrically coupled to said signal input of said second
inverter, said third inverter with power input electrically coupled
through said first resistor to said power supply node and with ground
input electrically coupled to said second resistor.
7. The buffer of claim 6, further comprising:
(a) a fourth inverter having a signal input and an output, said fourth
inverter electrically coupled between said first and third inverters with
signal input electrically coupled to said output of said first inverter
and with output electrically coupled to said signal input of said third
inverter, said fourth inverter with power input electrically coupled to a
tap on said first resistor and with ground input electrically coupled to a
tap on said second resistor.
8. The buffer of claim 7, wherein:
(a) said first resistor comprises first and second p-channel resistive
field effect transistors, each of said first and second p-channel
resistive field effect transistors having a gate, source, and drain, said
gate of said first p-channel resistive field effect transistor
electrically coupled to said ground node, said source of said first
p-channel resistive field effect transistor electrically coupled to said
power supply node and said drain of said first p-channel resistive field
effect transistor electrically coupled to the source of said second
p-channel resistive field effect transistor, said gate of said second
p-channel resistive field effect transistor electrically coupled to said
ground node and said drain electrically coupled to said source of said
first p-channel field effect transistor, said tap on said first resistor
is said drain of said first p-channel resistive field effect transistor.
9. The buffer of claim 7, wherein:
(a) said second resistor includes first and second n-channel resistive
field effect transistors, each of which has a corresponding gate, source,
and drain, said gate of said first n-channel resistive field effect
transistor electrically coupled to said power supply node, said source of
said first n-channel resistive field effect transistor electrically
coupled to said ground node and said drain of said first n-channel
resistive field effect transistor electrically coupled to the source of
said second n-channel resistive field effect transistor, said gate of
second n-channel resistive field effect transistor electrically coupled to
said power supply node and said drain of said second n-channel resistive
field effect transistor electrically coupled to said source of said first
n-channel field effect transistor, said tap on said second resistor is
said drain of said first n-channel resistive field effect transistor.
10. The low power input buffer of claim 1, wherein a diode is electrically
coupled between said power supply and said power supply node.
11. The low power input buffer of claim 1, wherein said first inverter is a
CMOS inverter and said second inverter is a CMOS inverter.
12. An integrated circuit, comprising:
(a) a first plurality of field effect transistors (FETs) powered by a first
power supply;
(b) a second plurality of FETs powered by a second power supply;
(c) a level translator coupling signals from said first plurality to said
second plurality, said level translator including FETs from said second
plurality which form a memory cell and FETs from said first plurality
which form a one-shot which sets said memory cell.
13. The integrated circuit of claim 12, wherein:
(a) said level translator generates a high going pulse on a first line to
said memory from a rising edge input.
14. The integrated circuit of claim 13, wherein:
(a) said level translator generates a high going pulse on a second line to
said memory from a falling edge input.
15. The integrated circuit of claim 12, further comprising an alternate
power supply electrically coupled to at least one of said first and second
power supplies.
16. The integrated circuit of claim 15, further wherein said alternate
power supply is a parasitic, signal powered power supply.
17. A low power input buffer, comprising:
(a) an input node, an output node, a power supply node, and a ground node;
(b) a first inverter having a signal input and an output and a second
inverter having a signal input and an output, the signal input of said
first inverter electrically coupled to said input node, the output of said
first inverter electrically coupled to the signal input of said second
inverter, and the output of second inverter electrically coupled to said
output node;
(c) said first inverter with power input electrically coupled through a
first resistor to said power supply node, said first resistor comprising a
p-channel field effect transistor with a gate electrically coupled to said
ground node;
(d) said second inverter with power input electrically coupled to said
power supply node;
(e) said first inverter comprises a first p-channel field effect transistor
having a gate, drain, and source and a first n-channel field effect
transistor having a gate and a drain, said gate of said first p-channel
field effect transistor electrically coupled to said first inverter signal
input and said drain of said first p-channel field effect transistor
electrically coupled to the drain of said first n-channel field effect
transistor, the gate of said first n-channel field effect transistor
electrically coupled to said first inverter signal input, and said first
resistor electrically coupling the source of said first p-channel field
effect transistor to said power supply node;
(f) said first n-channel field effect transistor having a source; and
(g) a second resistor electrically coupling the source of said first
n-channel field effect transistor to said ground node.
18. The low power input buffer of claim 17, wherein:
(a) said first inverter comprises
(i) a second p-channel field effect transistor having a gate, drain, and
source, said gate of said second p-channel field effect transistor
electrically coupled to said first inverter signal input, said source of
said second p-channel field effect transistor electrically coupled to said
drain of said first p-channel field effect transistor, said drain of said
second p-channel field effect transistor electrically coupled to the
output of said first inverter and to the drain of a second n-channel field
effect transistor, said second n-channel field effect transistor with gate
electrically coupled to said first inverter signal input and with source
electrically coupled to said drain of said first n-channel field effect
transistor,
(ii) a third p-channel field effect transistor having a drain, source, and
gate, said gate of said third p-channel field effect transistor
electrically coupled to said first inverter output, with source of said
third p-channel field effect transistor electrically coupled to said first
p-channel field effect transistor source, and with drain of said third
p-channel field effect transistor electrically coupled to said source of
said first n-channel field effect transistor, and
(iii) a third n-channel field effect transistor having a gate, source, and
drain, said gate of said third n-channel field effect transistor
electrically coupled to said first inverter output, with source of said
third n-channel field effect transistor electrically coupled to said
source of said first n-channel field effect transistor, and said drain of
said third n-channel field effect transistor electrically coupled to said
source of said first p-channel field effect transistor, whereby said first
inverter has input hysteresis circuit electrically coupled between said
signal input and said output.
19. The low power input buffer of claim 12, further comprising:
(a) a third inverter having a signal input and an output, said third
inverter electrically coupled between said first and second inverters with
signal input electrically coupled to said output of said first inverter
and with output electrically coupled to said signal input of said second
inverter, said third inverter with power input electrically coupled
through said first resistor to said power supply node and with ground
input electrically coupled to said second resistor.
20. The low power input buffer of claim 19, further comprising:
(a) a fourth inverter having a signal input and an output, said fourth
inverter electrically coupled between said first and third inverters with
signal input electrically coupled to said output of said first inverter
and with output electrically coupled to said signal input of said third
inverter, said fourth inverter with power input electrically coupled to a
tap on said first resistor and with ground input electrically coupled to a
tap on said second resistor.
21. The low power input buffer of claim 20, wherein
(a) said first resistor comprises first and second p-channel resistive
field effect transistors, each of said first and second p-channel
resistive field effect transistor having a gate, source, and drain, said
gate of said first p-channel resistive field effect transistor
electrically coupled to said ground node, said source of said first
p-channel resistive field effect transistor electrically coupled to said
power supply node and said drain of said first p-channel resistive field
effect transistor electrically coupled to the source of said second
p-channel resistive field effect transistor, said gate of said second
p-channel resistive field effect transistor electrically coupled to said
ground node and said drain electrically coupled to said source of said
first p-channel field effect transistor, said tap on said first resistor
is said drain of said first p-channel resistive field effect transistor.
22. The low power input buffer of claim 20, wherein:
(a) said second resistor includes first and second n-channel resistive
field effect transistors, each of which has a corresponding gate, source,
and drain, said gate of said first n-channel resistive field effect
transistor electrically coupled to said power supply node, said source of
said first n-channel resistive field effect transistor electrically
coupled to said ground node and said drain of said first n-channel
resistive field effect transistor electrically coupled to the source of
said second n-channel resistive field effect transistor, said gate of
second n-channel resistive field effect transistor electrically coupled to
said power supply node and said drain of said second n-channel resistive
field effect transistor electrically coupled to said source of said first
n-channel field effect transistor, said tap on said second resistor is
said drain of said first n-channel resistive field effect transistor.
23. The low power input buffer of claim 17, further comprising an alternate
power supply adapted to be electrically coupled to said power supply node.
24. The low power input buffer of claim 23, wherein said alternate power
supply is a parasitic, signal powered power supply.
25. The low power input buffer of claim 24, wherein a diode is electrically
coupled between said parasitic, signal powered power supply and said power
supply node.
26. The low power input buffer of claim 17, further comprising an alternate
power supply electrically coupled to said power supply node.
27. The low power input buffer of claim 26, wherein said alternate power
supply is a parasitic, signal powered power supply.
28. The low power input buffer of claim 27, wherein a diode is electrically
coupled between said parasitic, signal powered power supply and said power
supply node.
29. The low power input buffer of claim 17, wherein said first inverter is
a CMOS inverter and said second inverter is a CMOS inverter.
30. A low power input buffer, comprising:
(a) an input node, an output node, a power supply node, and a ground node,
said power supply node adapted to be electrically coupled to a power
supply;
(b) a first inverter having a signal input and an output and a second
inverter having a signal input and an output, the signal input of said
first inverter electrically coupled to said input node, the output of said
first inverter electrically coupled to the signal input of said second
inverter, and the output of second inverter electrically coupled to said
output nodes
(c) said first inverter with power input electrically coupled through a
first resistor to said power supply node;
(d) said second inverter with power input electrically coupled to said
power supply nodes and
(e) a diode is electrically coupled between said power supply and said
power supply node.
31. The low power input buffer of claim 30, wherein:
(a) said first resistor comprises a p-channel field effect transistor with
a gate electrically coupled to said ground node.
32. The low power input buffer of claim 30, wherein:
(a) said first inverter comprises a first p-channel field effect transistor
having a gate, drain, and source and a first n-channel field effect
transistor having a gate and a drain, said gate of said first p-channel
field effect transistor electrically coupled to said first inverter signal
input and said drain of said first p-channel field effect transistor
electrically coupled to the drain of said first n-channel field effect
transistor, the gate of said first n-channel field effect transistor
electrically coupled to said first inverter signal input, and said first
resistor electrically coupling the source of said first p-channel field
effect transistor to said power supply node.
33. The low power input buffer of claim 32, further comprising:
(a) said first n-channel field effect transistor having a source; and
(b) a second resistor electrically coupling the source of said first
n-channel field effect transistor to said ground node.
34. The low power input buffer of claim 33, wherein:
(a) said first inverter comprises (i) a second p-channel field effect
transistor having a gate, drain, and source, said gate of said second
p-channel field effect transistor electrically coupled to said first
inverter signal input, said source of said second p-channel field effect
transistor electrically coupled to said drain of said first p-channel
field effect transistor, said drain of said second p-channel field effect
transistor electrically coupled to the output of said first inverter and
to the drain of a second n-channel field effect transistor, said second
n-channel field effect transistor with gate electrically coupled to said
first inverter signal input and with source electrically coupled to said
drain of said first n-channel field effect transistor, (ii) a third
p-channel field effect transistor having a drain, source, and gate, said
gate of said third p-channel field effect transistor electrically coupled
to said first inverter output, with source of said third p-channel field
effect transistor electrically coupled to said first p-channel field
effect transistor source, and with drain of said third p-channel field
effect transistor electrically coupled to said source of said first
n-channel field effect transistor, and (iii) a third n-channel field
effect transistor having a gate, source, and drain, said gate of said
third n-channel field effect transistor electrically coupled to said first
inverter output, with source of said third n-channel field effect
transistor electrically coupled to said source of said first n-channel
field effect transistor, and said drain of said third n-channel field
effect transistor electrically coupled to said source of said first
p-channel field effect transistor, whereby said first inverter has input
hysteresis circuit electrically coupled between said signal input and said
output.
35. The low power input buffer of claim 34, further comprising:
(a) a third inverter having a signal input and an output, said third
inverter electrically coupled between said first and second inverters with
signal input electrically coupled to said output of said first inverter
and with output electrically coupled to said signal input of said second
inverter, said third inverter with power input electrically coupled
through said first resistor to said power supply node and with ground
input electrically coupled to said second resistor.
36. The low power input buffer of claim 35, further comprising:
(a) a fourth inverter having a signal input and an output, said fourth
inverter electrically coupled between said first and third inverters with
signal input electrically coupled to said output of said first inverter
and with output electrically coupled to said signal input of said third
inverter, said fourth inverter with power input electrically coupled to a
tap on said first resistor and with ground input electrically coupled to a
tap on said second resistor.
37. The low power input buffer of claim 36, wherein:
(a) said first resistor comprises first and second p-channel resistive
field effect transistors, each of said first and second p-channel
resistive field effect transistors having a gate, source, and drain, said
gate of said first p-channel resistive field effect transistor
electrically coupled to said ground node, said source of said first
p-channel resistive field effect transistor electrically coupled to said
power supply node and said drain of said first p-channel resistive field
effect transistor electrically coupled to the source of said second
p-channel resistive field effect transistor, said gate of said second
p-channel resistive field effect transistor electrically coupled to said
ground node and said drain electrically coupled to said source of said
first p-channel field effect transistor, said tap on said first resistor
is said drain of said first p-channel resistive field effect transistor.
38. The low power input buffer of claim 36, wherein:
(a) said second resistor includes first and second n-channel resistive
field effect transistors, each of which has a corresponding gate, source,
and drain, said gate of said first n-channel resistive field effect
transistor electrically coupled to said power supply node, said source of
said first n-channel resistive field effect transistor electrically
coupled to said ground node and said drain of said first n-channel
resistive field effect transistor electrically coupled to the source of
said second n-channel resistive field effect transistor, said gate of
second n-channel resistive field effect transistor electrically coupled to
said power supply node and said drain of said second n-channel resistive
field effect transistor electrically coupled to said source of said first
n-channel field effect transistor, said tap on said second resistor is
said drain of said first n-channel resistive field effect transistor.
39. The low power input buffer of claim 30, further comprising an alternate
power supply adapted to be electrically coupled to said power supply node.
40. The low power input buffer of claim 39, wherein said alternate power
supply is a parasitic, signal powered power supply.
41. The low power input buffer of claim 40, wherein a diode is electrically
coupled between said parasitic, signal powered power supply and said power
supply node.
42. The low power input buffer of claim 33, further comprising an alternate
power supply electrically coupled to said power supply node.
43. The low power input buffer of claim 42, wherein said alternate power
supply is a parasitic, signal powered power supply.
44. The low power input buffer of claim 42, wherein a diode is electrically
coupled between said parasitic, signal powered power supply and said power
supply node.
45. The low power input buffer of claim 30, wherein said first inverter is
a CMOS inverter and said second inverter is a CMOS inverter.
46. The low power input buffer of claim 30, wherein said power supply node
and said input node are combined into a signal node. |
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Claims |
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Description |
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PARTIAL WAIVER OF COPYRIGHT PURSUANT TO 1077 O.G. 22 (Mar. 20, 1987)
All of the material in this patent application is subject to copyright
protection under the copyright laws of the United States and of other
countries. As of the first effective filing date of the present
application, this material is protected as unpublished material.
Portions of the material in the specification and drawings of this patent
application are also subject to protection under the maskwork registration
laws of the United States and of other countries.
However, permission to copy this material is hereby granted to the extent
that the owner of the copyright and maskwork fights has no objection to
the facsimile reproduction by anyone of the patent document or patent
disclosure, as it appears in the United States Patent and Trademark Office
patent file or records, but otherwise reserves all copyright and maskwork
rights whatsoever.
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to semiconductor integrated circuits, and,
more particularly, to low power integrated circuits.
Many applications call for low power integrated circuits, such as battery
powered or parasitically powered integrated circuits used for cordless
identification tags, medical diagnostics devices, and data and
communication modules. For example, the DS1992 Touch Memory.TM.
manufactured by Dallas Semiconductor Corporation in Dallas, Tex. includes
a read/write memory with battery in a coin-sized can with the front and
back of the can forming two electrodes for 1-wire communication with the
memory. The memory retains data for 10 years, and thus the memory must
have very low power consumption. Similarly, the DS1287 real time clock
module for AT-class personal computers includes a battery and crystal plus
an integrated circuit for timekeeping even when a personal computer is
powered down.
The preferred embodiment illustrated in FIGS. 1A-C limits power consumption
by, among other methods, subdividing the integrated circuit into different
portion which are separately powered by different power sources. In
particular, the one-wire communication portion derives its power by
parasitic tapping power from the communication bus; thus upon
disconnection, the communication portion has a power failure. Contrarily,
the memory and clock portions remains continually powered up by a battery.
The use of two power sources requires a voltage level translator between
the portions because the battery and the parasitic power sources may be at
different voltages. And such a level translator must also have low power
consumption, especially when the communication portion has its power
source removed: floating nodes could lead to significant leakage currents
and drain the battery. Also, the input buffers in the communication
portion must not permit large transition currents when the voltage slowly
rises and falls on the communication bus due to the possibly large
capacitive loading of the communication bus in certain applications.
Indeed, the preferred embodiment has level translators which provide
communication between domains of different power supplies by one-shot
pulses, and the input buffer includes CMOS inverters with resistive
current limitations to reduce power consumption during slowly varying
inputs while retaining fast switching.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be described with reference to the accompanying
drawings which are schematic for clarity,
FIGS. 1A-C show packaged, schematic and the high-level physical chip layout
of a first preferred embodiment.
FIGS. 2A and 2B are a single flow chart, on two sheets, showing the
sequence of operations used, in the preferred embodiment, to interface to
the one-wire bus, and to respond to memory read, scratchpad read,
scratchpad write, and scratchpad copy commands.
FIGS. 3A through 3F are an overlaid set of maskwork patterns, showing the
principal levels of the layout actually used, in the preferred embodiment,
for the integrated RAM-counter array.
FIG. 4 shows the high-level circuit organization of the preferred
embodiment.
FIGS. 4A-1 and 4A-2 shows the circuit organization of circuit block IO,
which was referred to in FIG. 4.
FIG. 4A1 shows the circuit organization of circuit block PWRCAP, which was
referred to in FIGS. 4A-1 and 4A-2.
FIGS. 4A2-1 through 4A2-6 shows the circuit organization of circuit
sub-block RTOS, which was referred to in FIGS. 4A2-1 through 4A2-6.
FIG. 4A2a shows the circuit organization of circuit block TPOSC, which was
referred to in FIGS. 4A2-1 through 4A2-6.
FIG. 4A3 shows the circuit organization of circuit block BATTEST, which was
referred to in FIGS. 4A-1-4A2.
FIGS. 4A4-1 and 4A4-2 shows the circuit organization of circuit block
OWPROT, which was referred to in FIGS. 4A-1 and 4A-2.
FIG. 4A5 shows the circuit organization of circuit block IOBUF, which was
referred to in FIGS. 4A-1 and 4A-2.
FIG. 4A6 shows the circuit organization of circuit block POR2, which was
referred to in FIGS. 4A-1 and 4A-2.
FIG. 4A6a shows a variation of the circuit of FIG. 4A6.
FIG. 4A7 shows the circuit organization of level-translator circuit block
LVLT.sub.-- CS, which is referred to in FIGS. 4A-1 and 4A 2 and elsewhere.
FIG. 4A8 shows the circuit organization of level-translator circuit block
LVLT.sub.-- IE, which is referred to in FIGS. 4A-1 and 4A-2 and elsewhere.
FIG. 4A9 shows the circuit organization of level-translator circuit block
LVLT.sub.-- OE, which is referred to in FIGS. 4A-1 and 4A-2 and elsewhere.
FIG. 4A10 shows the circuit organization of level-translator circuit block
LVLT.sub.-- lS, which is referred to in FIGS. 4A-1 and 4A-2 and elsewhere.
FIGS. 4A11-4A16 show the operation of the level-translator of FIG. 4A10.
FIGS. 4B-1 through 4B-6 shows the special function register block SFR,
which was referred to in FIG. 4.
FIG. 4B1 shows the circuit organization of block XFER which is referred to
in FIGS. 4B-1 through 4B 6.
FIG. 4B2 shows the circuit organization of block MATCH, which was referred
to in FIGS. 4B-1 through 4B-6. This block detects the occurrence of an
alarm condition in any of the counters.
FIGS. 4B-1 through 4B3-3 shows the circuit organization of block CONTROL,
which was referred to in FIGS. 4B-1 through 4B-6. In addition to
performing routine control functions, note that this circuitry generates a
signal LOCK when a match occurs within any of the three counters.
FIG. 4B4 shows the actual detailed implementation of one bit of these
counter chains.
FIG. 4C shows the divider block DIV, which was referred to in FIG. 4.
FIG. 4C1 shows a known input buffer.
FIGS. 4C2-4C4 illustrate the operation of the buffer of FIG. 4C1.
FIG. 4C5 shows a preferred embodiment input buffer.
FIGS. 4C6-4C7 illustrate the operation of the buffer of FIG. 4C5.
FIG. 5 shows an innovative socket which can be used in combination with the
chip of the preferred embodiment.
FIGS. 6A-6D show the timing of voltages appearing at various nodes in the
power-on-reset circuit of FIG. 4A6.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1A shows a preferred embodiment integrated circuit chip layout in
block format with FIG. 1B schematically illustrating the chip connected to
a battery and a crystal for use as a timekeeping system with read/write
memory and both 3-wire and one-wire communication ports. The one-wire
communications use the I/O pin and the three-wire communications use the
RST , DQ, and CLK pins. IRQ is an interrupt output, and 1 Hz is a 1 Hz
square wave output.
FIG. 1C shows in cross-sectional elevation view the system of FIG. 1B
packaged in a coin-sized can which only provides two terminals (the top
and the bottom-side of the can) and thus only provides one-wire
communication. Such a can may have dimensions of about 17 mm diameter and
6 mm thickness. Note that FIG. 1C shows the integrated circuit of FIG. 1A
as a die directly mounted on a printed circuit board and covered with a
sealer. Alternatively, the integrated circuit of FIG. 1A could be packaged
as an SOIC, DIP or PLCC or other standard IC package and this package
mounted on the printed circuit board.
For the FIG. 1C packaging, the Vcc input is grounded, the backup battery
terminal grounded, and a power battery connected. In this configuration
the integrated circuit has some devices powered by the power battery and
other devices powered by energy extracted from the one-wire communication
bus. Thus devices in these two power domains may have different power
levels, depending upon battery voltage (typically 3 volts) and
communication bus voltage (typically 5 volts), and require level
translators. Preferred embodiment level translators for signals passing
between these different power domains are shown in FIGS. 4A7-4A16 and
described in the following sections "Use of Separate Power-Spply Domains"
and "Input/Output: Block IO".
One application of the preferred embodiment, either in the FIG. 1B or FIG.
1C form, counts power cycles for items such as printed circuit boards
(PCBs) or electrical machinery. A power supply voltage (maybe after
rectification and division) is detected at the one-wire communication
port, and such a voltage may be very slowly varying due to capacitive
loading. In this case, the input buffers for the preferred embodiment must
have low power switching as the input voltage slowly crosses a threshold
to avoid battery drain. Thus the input buffer cannot draw much current and
the switching should be rapid to insure small energy consumption.
Preferred embodiment input buffers are shown in FIG. 4C5 and described in
following section "Divider Block: DIV".
Functional Description
Some notable features of the integrated circuit of FIG. 1A and the system
of FIG. 1B-C include the following:
one-wire interface requires only one port pin for communication
Contains real-time clock/calendar in binary format
4096 bits of SRAM organized in 16 pages, 256 bits per page
Programmable elapsed time meter
Programmable cycle counter which can sample and store the number of system
power-on/off cycles
Programmable alarms can be set to generate interrupts for elapsed time,
real-time clock alarms, and/or cycle counter
Lock-out feature provides tamper-proof data
Data integrity assured with strict read/write protocols
3-wire I/O for high speed data communications (not for FIG. 1C)
Replaces bar code labels with unique 64-bit factory lasered solid state
serial number
Space-saving 16-pin SOIC package (within package of FIG. 1C)
Operating temperature range=-40.degree. C. to +85.degree. C.
Battery operating voltage range =2.0 Volts to 5.5 Volts.
The embodiment of FIG. 1A offers a simple solution for storing and
retrieving vital information with minimal hardware. Only one port pin is
required for communication. This I/O gives the user access to a unique
lasered identification number, a real-time clock/calendar, elapsed time
clock, cycle counter, programmable interrupts and 4096 bits of SRAM. All
these features are available with or without system power applied. The
lasered identification number can replace bar codes for tracking purposes.
Using the one-wire port, this ID can be read when assembly is without
power. Utilizing backup energy sources, the data is nonvolatile and allows
for stand-alone operation. A strict protocol for accessing the preferred
embodiment insures data integrity. For high speed communication, the
traditional Dallas Semiconductor three-wire interface is provided.
Extensive additional material regarding the one-wire-bus architecture of
the preferred embodiment may be found in cross-referenced U.S. patent
application Ser. No. 07/725,793, filed Jul. 9, 1991, entitled "Memory,"
which is hereby incorporated by reference.
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Pin Description
PIN SYMBOL DESCRIPTION
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1,16 Vcc Power input pins for 3.0 to 5.5 volt operation.
Either pin can be used for Vcc. Only one is
required for normal operation.
(See VBATO & PFS definitions).
2 IRQ Interrupt output pin - Open drain
3 RST Reset input pin for 3-wire operation
4 DQ Data in/out pin for 3-wire operation
5,7 NC No connection pins
6 CLK Clock input pin for 3-wire operation
8,13 GND Ground pin - Either pin can be used
for ground.
9 VBATB Battery backup input pin -Battery voltage
should be 3.0 volts for power fail protection
mode. See VBATO & PFS pin definition.
10 VBATO Battery operate input for 2.0-5.5 volt
operation. Battery with 2.0-5.5 volts can be
used to power the chip. The Vcc & VBATB
pin must be grounded when this pin is used
to power the chip.
11 I/O One-Wire input/output - Complete
communication with the chip can be done
using this pin. See definitions of One-Wire
protocol for complete description. Open drain.
12 PFS PFS Power fan select - To activate
the power fail protection circuitry when using
Vcc and battery backup, this pin must be
* connected to the VBATO. In this mode the
power monitor circuitry is enabled and will
* write protect all inputs when Vcc <
VBATB. When operation is required from
2.0-5.5 volts, use VBATO for power.
This pin must be connected to ground.
In this mode, no input pin can be
held in an intermediate voltage level, i.e.,
0.7 < VIN < 2.3 V. All inputs must be at
VIL or VIH levels. See DC Characteristics
for VIL & VIH. Operational voltage range
is restricted in this mode to VBATB to 5.5 V.
14,15
X1,X2 Crystal input pins. Connections for a standard
32.768 KHz quartz crystal, Daiwa
part number DT-26S (be sure to request
6 pf load capacitance).
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The real-time clock, elapsed timer, real-time alarm, elapsed time alarm,
cycle counter and control/status register are all read/write registers.
Flag bits in the status register are read-only bits. Data is sent from the
host via the serial interface(s), least significant bit (LSB) first. All
data is in binary format. The following briefly describes the one-wire
protocol: The host generates a reset pulse that clears all previous
commands and begins communications. The preferred embodiment then sends a
presence pulse to acknowledge that reset has occurred and it is ready for
a new command. As an example to illustrate how the protocol works, a
typical command for one-wire communications is Read ROM Data. The host
sends a command byte 33h; after which it drives the I/O line to a low
state for less than 15 .mu.sec. It then releases the I/O line and samples
the line condition (high | | |
