 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed to a device and method for sampling an analog
input signal(s) to generate a sample, and for providing the sample to a
memory in a direct memory access (DMA) operation.
2. Description of the Related Art
DMA sampling systems generally function to sample an analog input signal
from a sensor to generate samples which are provided to a memory in a DMA
operation. Such systems periodically request bus mastership from a central
processing unit (CPU) which is coupled to a memory by a bus. Upon a grant
of bus mastership by the CPU, these DMA sampling systems sample the analog
input signal to generate a sample which is provided to the memory via the
bus under control of the DMA sampling systems. Thereafter, such DMA
sampling systems advise the CPU that the DMA operation has been completed,
and the CPU resumes bus mastership.
Because the time difference between the request for bus mastership from
such DMA sampling systems and the grant of bus mastership from the CPU may
vary, an exact sampling rate is generally not maintained by such DMA
sampling systems since sampling of the analog input signal occurs only
after the grant of bus mastership in such DMA sampling systems.
Certain applications of DMA sampling system require that an exact sampling
rate be maintained. For example, in fast-Fourier transform (FFT)
processing, maintenance of an exact sampling rate is particularly critical
to avoid the introduction of noise into the FFT processing algorithm. For
example, assuming a dynamic range (i.e., the ratio of the specified
maximum signal level capability of a system to its noise level) of 6
decibels per bit, a DMA sampler using an eight-bit sample potentially has
a dynamic range of 48 decibels (8 bits.times.6 decibels per bit).
However, an error in the sampling rate of as little as 1.5% translates
into a 9.5 decibel degradation in dynamic range for the DMA sampling
system. Such degradation is referred to as "aperture jitter".
SUMMARY OF THE INVENTION
An object of the present invention is to provide a DMA sampling system for
sampling an analog input signal(s) at a substantially exact sampling rate
to significantly reduce aperture jitter, and yet affording the advantage
of reducing CPU processing time through the use of a DMA operation.
Another object of the present invention is to provide a capability for
converting digital samples into a format corresponding to preliminary
steps of an FFT processing algorithm before performing a DMA operation.
A further object of the present invention is to provide a DMA sampling
system which is less susceptible to timing problems, for example, a clock
slip, by implementing the structure performing the DMA operation as a data
flow machine.
These objects are obtained by the DMA sampler herein disclosed. According
to the present invention, there is provided a DMA sampler in which
sampling circuitry is implemented as a finite state machine so that a
substantially exact sampling rate is maintained. Upon the generation of a
sample, the FFT sampling circuit notifies DMA circuitry of the existence
of a sample to be transferred to a CPU memory. The DMA circuitry is
implemented as a data flow machine so that DMA processing is initiated by
the DMA circuitry upon notification of the existence of a sample from the
FFT sampling circuitry. In response to such notification, the DMA
circuitry requests bus mastership from the CPU and waits until bus
mastership of the CPU bus is granted. The CPU is programmed to respond to
the request for bus mastership within a time period sufficient for the
sampling circuit to obtain the next sample. Upon receipt of bus
mastership, the DMA circuit drives a CPU address bus with an address and
drives the data bus with the-sample to provide the sample to the CPU
memory. Thereafter, the DMA circuitry returns bus mastership to the CPU
and the DMA operation is completed. Because the DMA circuitry is
implemented as a data flow machine so that the DMA circuitry requests bus
mastership upon notification of the existence of a sample to be
transferred to the CPU memory, the DMA circuitry helps to ensure that
samples are not lost and is less susceptible to timing problems.
These together with other objects and advantages, which will become
subsequently apparent, reside in the details of construction and operation
as more fully hereinafter described and claimed, reference being had to
the accompanying drawings, forming a part hereof, wherein like numerals
refer to like parts throughout.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a microprocessor-based system employing the
DMA sampler in accordance with the present invention;
FIG. 2 is a circuit diagram of part of the control register of FIG. 1;
FIG. 3 is a circuit diagram of part of the control register, part of the
decode logic circuit and part of the sampler of FIG. 1;
FIG. 4 is a circuit diagram of parts of the sampler and a part of the DMA
circuit of FIG. 1;
FIG. 5 is a circuit diagram of the A/D converter, the converter and the
latch of FIG. 1;
FIG. 6 is a circuit diagram of the A/D address generator of FIG. 1;
FIG. 7 is a block diagram of the DMA sampler clock of FIG. 1;
FIG. 8 is a subcircuit within the DMA circuitry of FIG. 1 which controls
memory writes;
FIG. 9 is a circuit diagram of part of the decode logic circuit of FIG. 1;
FIG. 10 is a circuit diagram of part of the memory address generator of
FIG. 1;
FIG. 11 is a circuit diagram of part of the memory address generator of
FIG. 1;
FIG. 12 is a circuit diagram of the DMA interrupt circuit of FIG. 1;
FIG. 13 is a circuit diagram of the interrupt status register of FIG. 1;
FIG. 14 is a flow chart representation of typical processing by the CPU of
FIG. 1;
FIG. 15 is a generalized circuit diagram of the microprocessor-based system
of FIG. 1; and
FIG. 16 is a timing diagram of the DMA sampler of the preferred embodiment
of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Before specifically describing the preferred embodiments of the present
invention, a general description of the present invention is given below.
Referring to FIG. 15, the microprocessor-based system employing the DMA
sampler in accordance with the present invention generally includes a CPU
2, a CPU memory 4, sampling circuitry 10 and DMA circuitry 12. The
sampling circuitry 14 and the DMA circuitry 12 may be referred to
collectively as a "DMA sampler." The CPU 2 initiates sampling by the
sampling circuitry 10 by generating the signal SWSTART. Upon activation of
the signal SWSTART, the sampling circuitry 10 samples at least one analog
input signal and generates the signal DMAQ24 to notify the DMA circuitry
12 that at least one sample has been obtained. In response to the signal
DMA Q24, the DMA circuitry 12 issues a signal BUSRQ to request bus
mastership from the CPU 2. In response to the signal BUSRQ, the CPU 2
generates the signal INBUSGRNT- to advise the DMA circuitry 12 of a grant
of bus mastership. The DMA circuitry 12 acknowledges the grant of bus
mastership by generating the signal BGACK which is provided to the CPU 2.
After a grant of bus mastership, the sampling circuitry 10 outputs a
sample(s) as the signal OUTMCUD in response to the signal BGACK from the
DMA circuitry 12. The DMA circuitry 12 generates and outputs an
appropriate CPU memory address OUTA and controls the timing for writing
the sample(s) to the CPU memory 4 using CPU bus 6. Thereafter, the CPU 2
resumes bus mastership in response to the deactivation of the signal
BGACK.
In the above description with reference to FIG. 15, it should be noted that
once sampling is initiated by the CPU 2 through generation of the signal
SWSTART, sampling is performed by the DMA sampler without any dependence
upon whether bus mastership has been granted to the DMA sampler.
Accordingly, the DMA sampler is able to maintain a substantially exact
sampling rate to avoid the degradation in performance caused by aperature
jitter in prior art DMA sampling systems.
Next, a more detailed description of the preferred embodiments of the
present invention, is given below.
The DMA sampler of the present invention is divided into two main elements:
the sampling circuitry 10 (i.e., means for sampling) and the DMA circuitry
12 (i.e., means for performing a DMA operation). The sampling circuitry 10
is implemented as a finite state machine which performs an
analog-to-digital (A/D) read operation to obtain digital samples from
analog input signal(s) provided to the DMA sampler. The CPU 2 associated
with the DMA sampler operates at a system clock rate having a period
termed "SYSCLK". The sampling circuitry 10 is designed to perform at least
one A/D read operation every 512 SYSCLKs.
The sampling circuitry 10 is capable of sampling as many as eight analog
input signals which are generally derived from sensors coupled to the DMA
sampler. Accordingly, the sampling circuitry 10 generates an A/D address
to select one of the analog input signals for sampling. The sampling
circuitry 10 cycles the A/D address from zero to three in order to sample
four analog input signals on four respective analog channels 0, 1, 2 and 3
as shown in FIG. 16. This cycling occurs for N-1 cycles, where N is a
number designated by the CPU 2. In the present invention, N may have
values of 32, 64, 128 or 256.
On the Nth cycle, the A/D read operation is performed every 256 SYSCLOCKS
to obtain samples from all eight channels of the sampling circuitry 10
with the address sequence of 0, 4, 1, 5, 2, 6, 3 and 7. Such address
sequence maintains an exact sampling frequency on channels 0, 1, 2 and 3
while also obtaining new data on analog channels 4, 5, 6 and 7 once per N
cycles. Hereinafter, N cycles is referred to as a "look".
Samples from the sampling circuitry 10 are stored in the CPU memory 4 at a
memory address derived from base addresses provided to the DMA circuitry
12 by the CPU 2 prior to sampling. These base addresses are referred to as
BASE0, BASE1 and ANBASE. Samples corresponding to A/D address 0 are stored
at CPU address locations BASE0 through BASE0+510, samples corresponding to
A/D address 1 map to BASE0+512 through BASE0+1022, samples corresponding
to A/D address 2 map to BASE0 +1024 through BASE0+1534, and samples
corresponding to A/D address 3 map to BASE0+1536 through BASE0+2046. The
above samples are referred to as "sample set 0" and correspond to one look
for each of the channels 0, 1, 2 and 3.
After sampling is performed for one look, the CPU 2 may direct the DMA
sampler to perform sampling for another look. In such case, the DMA
circuitry 12 changes the base address constant from BASE0 to BASE1 to
obtain another set of samples for channels 0, 1, 2 and 3, termed "sample
set 1". After completion of the second look, if the CPU 2 directs the DMA
sampler to perform another look, the DMA circuitry 12 changes the BASE
address constant from BASE1 back to BASE0. The DMA circuitry 12 performs
such toggling between BASE0 and BASE1 so that the CPU 2 has sufficient
time to handle samples corresponding to a given look before such samples
are written over in a subsequent look.
The samples corresponding to A/D address 4, 5, 6 and 7 are stored at memory
locations ANBASE, ANBASE+2, ANBASE+4 and ANBASE+6, respectively. Thus,
ANBASE is used as the base address for the last four analog channels
regardless of the current sample set being sampled.
With the above addressing scheme, it will be noted that two memory spaces
are allocated for each sample in the CPU memory 4. Accordingly, a sample
may be split into upper and lower halves and written to the CPU memory 4
in two successive memory locations. However, in the description of the
preferred embodiment, it is assumed that the CPU memory 4 has a sufficient
bit size to accommodate each sample at one memory location, although other
implementations of the CPU memory 4, the bit size of the CPU bus 6 and the
sample size generated by the sampling circuitry 10 are possible, and may
be readily implemented by those of ordinary skill in the art.
In the above sampling scheme, four analog input signals are sampled N times
per look on channels 0, 1, 2 and 3, while another four analog input
signals are sampled on analog channels 4, 5, 6 and 7 only once per look.
This feature provides flexibility in sampling analog input signals
provided to the DMA sampler since the CPU 2 may require more samples for a
given analog input signal per look than other analog input signals, to
operate effectively. For example, analog input signals from temperature
sensors are generally less time variant than vibration sensors, so that
analog input signals from temperature sensors may be sampled less
frequently than analog input signals from vibration sensors.
Also in accordance with the present invention, an optional feature is
provided to convert a sample of a given bit size, e.g., eight bits, into a
sign-extended twos-complement code so that the samples are in a correct
format for the preliminary step of some FFT algorithms. Thus, no other
data scaling need be performed prior to performing these particular FFT
algorithms. When other FFT algorithms are implemented on the DMA sampler
of the present invention, this feature may be omitted.
The DMA circuitry 12 is implemented as a data flow machine in which
processing initiates upon indication of the existence of a sample to be
transferred from the sampling circuitry 10 to the CPU memory 4. The DMA
circuitry 12 functions to request bus mastership from the CPU 2 and waits
until mastership of the CPU bus 6 is granted. Upon receipt of bus
mastership, the DMA circuitry 12 drives the CPU bus 6 with a CPU memory
address derived from the appropriate base address as described above, and
also drives the CPU bus 6 with the sample. The CPU memory 4 is then
enabled and strobed to complete data storage of the sample, and bus
mastership is returned to the CPU 2. In the present invention, the DMA
sampler only maintains bus mastership for two SYSCLOCKs in a normal DMA
operation. In the worst case, clock skew could cause three SYSCLOCKs from
grant of bus mastership to and release of bus mastership by the DMA
sampler. Therefore, processing performed by the CPU is only slowed a
maximum of three SYSCLOCKs for every 512 SYSCLOCKs, or 0.6%, while a
substantially exact sampling rate of the analog input signals is
maintained.
Referring to FIG. 1, a description of a microprocessor-based system
employing the DMA sampler of the preferred embodiment of the present
invention, is disclosed below.
A CPU 2 is coupled to a CPU memory 4 by a CPU bus 6. Also coupled to the
CPU bus 6 is control register 8 which the CPU 2 accesses with a specific
address provided on the CPU bus 6. The CPU 2 uses the control register 8
to write instructions to the DMA sampler, and also to read the status of
the DMA sampler.
The DMA sampler is divided into two parts: sampling circuitry 10 (i.e.,
means for sampling) and DMA circuitry 12 (i.e., means for performing a DMA
operation). The sampling circuitry 10 includes sampler 14, DMA sampler
clock 16, A/D converter 18, A/D address generator 20, latch 22 and
converter 24. The DMA circuitry 12 includes DMA circuit 26, memory address
generator 28 and the DMA sampler clock 16 which is common to both the
sampling circuitry 10 and the DMA circuitry 12. A DMA interrupt circuit 32
and an interrupt status register 34 are also provided in the
microprocessor-based system.
To initiate sampling, the CPU 2 addresses the control register 8 to
activate or deactivate certain bits stored therein. The output of the
control register S corresponding to these bits is provided to the decode
logic circuit 30 which issues a signal SWSTART to the sampler 14 to start
sampling by the DMA sampler. Also, the decode logic circuit 30 generates
two signals RDATOD- and DCDA2D which are provided to the sampler 14 when
the CPU 2 is instructed to read samples directly without intervention of
the DMA sampler.
In response to the signal SWSTART from the decode logic circuit 30, the
sampler 14 issues the signal ENBUSARB to the DMA sampler clock 16, the A/D
address generator 20 and the DMA circuit 26, to enable bus arbitration
between the DMA sampler and the CPU 2.
In response to either the signals RDATOD- and DCDA2D or the signal DMAQ24
in the sampler 14 based on the clock signal DLYGO- or the signal GOAN-,
the sampler 14 issues the signals RDATOD- and A2DDEN- to control A/D
converter 18 to read data on a selected channel, and to provide the sample
obtained by the A/D converter 18 at the output thereof. Also, in response
to the signal DCDA2D, the sampler 14 issues signal ATODCE to the latch 22
to enable the latch 22 to output data onto the CPU bus 6. The signal
ATODCE is also provided to the A/D converter 18 to enable the A/D
converter 18.
The sampler 14 also receives from the control register 8 the signal CONT
which is used by the CPU 2 to command the DMA sampler to execute more than
one look.
The DMA sampler clock 16 operates based on the system clock SYSCLK to
generate two-phase clock signals PH1 and PH0. In the preferred embodiment,
the two-phase clock signals PH1 and PH0 each have a frequency of 8
megahertz.
The two-phase clock signals PH1 and PH0 are used to generate signals GO,
DLYGO, and HALFGO. The signal GO indicates the beginning of a cycle while
the signal DLYGO is a signal delayed by one period of the signal PH0 from
the signal GO. The signal HALFGO is used to indicate the start of the
second half of one cycle. The DMA sampler clock 16 also generates a signal
32K which is used to provide timing for operations in the DMA sampler and
the DMA interrupt circuit 32.
The A/D converter 18 activates a signal DMAQ24 which is provided to the DMA
circuit 26 to indicate the fact that a sample has been obtained. When the
DMA circuit 26 is enabled by the signal ENBUSARB from the sampler 14, the
DMA circuit 26 issues a signal BUSRQ- to the control CPU 2. Accordingly,
the CPU 2 is advised that the DMA sampler has requested bus mastership by
the activation of the signal BUSRQ-. The CPU 2 is programmed to respond to
a bus request from the DMA sampler indicated by the signal BUSRQ- within
approximately 125 SYSCLOCKs. When the CPU 2 determines that it may
relinquish bus mastership to the DMA sampler, the CPU 2 responds to the
request for use of the bus by issuing the signal INBUSGRNT to the DMA
circuit 26. In response to the signal INBUSGRNT the DMA circuit 26 resets
the signal BUSRQ- and acknowledges the grant of bus mastership by
providing the signal BGACK to the CPU 2. Upon receiving the signal
INBUSGNT, the DMA sampler will provide a sample from the latch 22 to the
CPU memory 4 and return bus mastership to the CPU 2 within 3 SYSCLOCKs.
The A/D converter 18 is provided with various control information from the
control register 8 prior to the initiation of sampling. Such control
information includes, for example, a designation of the number of bits to
be obtained for each sample. Also, the A/D converter 18 is provided with
at least one analog input signal, but when plural analog input signals are
provided to the A/D converter 18, provision must be made to address the
channels of the respective analog input signals.
This function is provided by the A/D address generator 20 which uses the
clock signals DLYGO and GO to generate the signals ATODADR0, ATODADR1 and
ATODADR2. These signals are provided as a three-bit input signal to the
A/D converter 18 so that as many as eight channels may be addressed by the
A/D address generator 20.
The A/D address generator 20 also functions to provide the signals A2DA0
and A2DA1 to the memory address generator 28 for use in generating
appropriate CPU memory addresses during a look. Also, the A/D address
generator 20 generates a signal THREE which is provided to the DMA
interrupt circuit 32 and combined with other signals to generate an
interrupt to the CPU 2. The A/D address generator 20 is reset by a signal
SAMSTART- from the sampler 14 which operates to reset the A/D address
generator 20 at the beginning of a cycle.
Prior to instructing the DMA sampler to execute sampling, the CPU 2 loads
base addresses BASE0, BASE1 and ANBASE into the memory address generator
28. To perform this function, the CPU 2 generates an appropriate address
INA which is decoded in the decode logic circuit 30 to produce the signals
LDANBASE, LDDMABAS0 and LDDMABAS1. The CPU 2 also generates and provides
the signals INA18 and WRITE to the decode logic circuit 30 to generate one
of the signals RDDBASE0, RDBASE1 and RDABASE- when the CPU 2 reads samples
from the CPU memory 4 or when the DMA circuit 26 writes a sample to the
CPU memory 4 by generating the signal TOENTCNTL. The resulting signal is
used to output an appropriate CPU memory address to the CPU memory 4. In
the memory address generator 28, the base addresses BASE0, BASE1 and
ANBASE correspond to the most significant bits for generating CPU memory
addresses for the sample set 0, the sample set i and the samples
corresponding to channels 4, 5, 6 and 7, respectively.
As the next most significant bits, the memory address generator 28 uses the
signals A2DA0 and A2DA1 from the A/D address generator 20. These bits
merely sequence for each cycle so that sample sets for channels 0, 1, 2
and 3 and 4, 5, 6 and 7 are stored in separate memory spaces in the CPU
memory 4.
As the least significant bits which are used to address CPU memory 4, the
memory address generator 28 counts occurrences of the signal GO to
maintain a record of the number of cycles of samples which have been
completed while a look is progressing. The count value is used as the
least significant bits to address the CPU memory 4 only for sample sets 0
and 1 (i.e., the samples for channels 4, 5, 6 and 7 are only obtained once
per look so that the coupling of ANBASE with the signals A2DA0 and A2DA1
is sufficient to generate the CPU memory addresses for samples from
channels 4, 5, 6 and 7). The count value is also input to appropriate
logic gates to output a signal preLASTCNT to the sampler 14 to indicate
the occurrence of the end of a look.
The count value of the least significant bits of the memory address
generator 28 are reset by the signal SAMSTART- from the sampler 14. In
addition, the sampler 14 provides signals SAMSET0 and SAMSET1 to the
memory address generator 28 to enable the base addresses BASE0 and BASE1,
respectively, to be output from the memory address generator 28.
The DMA circuit 26 and the CPU 2 generate signals RAMCE-, HIRAMWRT- and
LORAMWRT- to enable a sample to be written into the CPU memory 4, and to
write the high and low sample words into the CPU memory 4 from the latch
22, respectively.
The DMA interrupt circuit 32 receives the signals 32K, THREE and BGACK, and
generates the signals SAMPEND and DMAINT to indicate to the sampler 14 and
the CPU 2, respectively, the occurrence of the end of a look. Upon
handling of the interrupt indicated by the signal DMAINT, the CPU 2 issues
the signal CLRINT- to deactivate the DMA interrupt circuit 32.
A specific description of the components used to implement each of the
elements of the preferred embodiment of the present invention as shown in
FIG. 1 is given below.
In the preferred embodiment, the CPU 2 is an MC68332 manufactured by
Motorola Corporation. The CPU 2 is coupled to the CPU memory 4, a
conventional 32K.times.16-bit RAM, via the CPU bus 6. The CPU bus 6
includes an address bus and a data bus.
The control register 8 is coupled to the CPU bus 6 and is addressed by the
CPU 2 with a particular address, so that the CPU 2 may write instructions
to the DMA sampler or read the control register 8 to determine the status
of the DMA sampler.
The control register 8 includes control register part 80 of FIG. 2 and
control register part 82 of FIG. 3. The control register part 80 is
provided with a signal RESET- which is used to clear TTL L273 registers 84
and 86 when system and DMA sampler resets occur, for example, upon
start-up of the microprocessor based system. The signal WECONFIG- is a
control signal generated by the CPU 2 to write instructions to the control
register 8 on lines designated IND. By writing to the control register 8
using the signals WECONFIG- and IND, the CPU 2 is able to control
operations of the DMA sampler by activating or deactivating particular
bits of the signal IND.
The signals generated by each bit stored in the LS373 registers 84 and 86
provide a variety of functions and capabilities. The signals SSCMP0,
SSCMP1, SSCMP2 and SSCMP3 provide the capability to control multiple DMA
samplers in accordance with the present invention, using a single CPU.
Signal ENMCUSS is used by the CPU 2 to enable a particular DMA sampler in
a multi-DMA sampler environment.
Signal DMAINTEN is used to enable or disable the DMA interrupt circuit 32
since there may be occasions on which the CPU 2 is engaged in processing
which should not be interrupted by the DMA sampler. The signals VGINTEN
and XINTEN are used to enable and disable two additional interrupts.
VGINTEN controls voltage glitch interrupt enable and XINTEN controls a
general purpose external interrupt enable. The control register part 80
also stores a bit for the signal CONT. The signal CONT is activated by the
CPU 2 when the CPU 2 requires the DMA sampler to provide samples for more
than one look. Accordingly, the signal CONT designates a continuous
sampling mode.
The control register part 80 further stores the signals CMP0 and CMP1 which
are provided to the decode logic circuit 30 to designate the number of
bits per sample to be obtained by the A/D converter 18. In the following
description, it is assumed that the number of bits per sample is 16 bits,
though the signals CMP0 and CMP1 provide the capability for larger sample
sizes.
In addition, the circuit contains an IEEE 1149.1 compliant boundary scan to
test the input and output pins of the DMA sampler.
Bits corresponding to the signals ACTLOVG0, ACTLOVG1 and ACTLOXINT are
stored in the control register part SO to select whether external
interrupts are active high or active low signals. The signal SWSTART- is
used to start the sampling process after the circuit has been configured
using the control register 8.
Referring to FIG. 3, the control register part 82 includes four TTL LS244
latches 81, 83, 85 and 87. The signals from the control register part 80
are provided to the control register part 82 directly, with the exception
of the signal ENBUSARB- which is generated in circuitry in the sampler 14,
as more fully described in a later section.
The LS244 latches 81, 83, 85 and 87 are provided with a control signal
RDCONFIG- which is activated by the CPU 2 when the CPU 2 reads the control
register 8 to determine the status of the DMA sampler. When the signal
RDCONFIG- is strobed low, the control register part 82 outputs a 16-bit
data word designated OUTMCUD which is provided to the CPU 2 on the data
bus of the CPU bus 6.
The sampler 14 includes sampler part 140 of FIG. 3, and sampler parts 142
and 144 of FIG. 4. As previously explained, when the CPU 2 requires the
DMA sampler to begin sampling, the CPU 2 writes to the control register 8
to activate the signal SWSTART-. The signal SWSTART- is provided to the
sampler part 140 at one input of NAND gate 143 of sampler latch 141. When
the signal SWSTART- is strobed low, the output of sampler latch 141 is
caused to enter a high-voltage state. Upon activation of the signal PH0
provided to the clock input of the D flip-flop 145, the output Q of the D
flip-flop 145 strobes low. This output is used to generate the signal
ENBUSARB- which is provided from the sampler 14 to the DMA sampler clock
16, the A/D address generator 20 and the DMA circuit 26 to enable bus
arbitration between the DMA sampler and the CPU 2. The output Q of the D
flip-flop 145 is also provided through inverter 146 to produce the signal
ENBUSARB, which is merely an inversion of the signal ENBUSARB-. The signal
ENBUSARB is latched in LS244 latch 81.
The sampler part 140 is also provided with control signals SWRESET- and
MCURESET- which are used to designate a DMA sampler reset and a system
reset, respectively. The signals SWRESET and MCURESET- are provided to AND
gate 147 to generate the signal RESET-. The signal RESET- is provided to
one input of NAND gate 148 to cause the output of sampler latch 141 to go
to a low-voltage state. Such operation causes the signal ENBUSARB- to
become deactivated so that bus arbitration between the DMA sampler and the
CPU 2 is inhibited. Also, the D flip-flip 145 is cleared by the signal
MCURESET which is merely the inversion of the signal MCURESET-. The
clearing of the flip-flop 145 by the signal MCURESET also inhibits bus
arbitration upon the occurrence of the system reset.
The sampler part 140 is further provided with the signal SAMPEND from the
DMA interrupt circuit 32. The signal SAMPEND indicates the end of a look
and is provided to the input of the D flip-flop 149. When activated, the
signal SAMPEND is clocked into the flip-flop 149 upon activation of clock
signal PH0 from the DMA sampler clock 16. The output Q of the flip-flop
149 is brought to a low-voltage state and provided as one of the inputs to
NOR gate 150. The other input of the NOR gate 150 is the signal CONT which
is provided from the CPU 2 via the control register 8 to indicate whether
the DMA sampler is to obtain samples for more than one look. When the DMA
sampler is merely to perform sampling for one look, the signal CONT is
deactivated so that the output of NOR gate 150 is brought to a
high-voltage state. This causes the sampler latch 141 to be reset and the
signals ENBUSARB- and ENBUSARB which are derived from the output of the D
flip-flop 145, are deactivated so that bus arbitration between the DMA
sampler and the CPU 2 is inhibited.
On the other hand, when the signal CONT is activated, the output of the NOR
gate 150 is brought to a low-voltage state so that the output of the
sampler latch 141 is brought to a high-voltage state. Accordingly, the D
flip-flop 145 is set upon activation of the clock signal PH0 so that the
output Q of the D flip-flop 145 is brought to a low-voltage state.
Accordingly, bus arbitration between the DMA sampler and the CPU 2 is
enabled for another look.
When the signal SAMPEND is clocked into D flip-flop 149 upon the occurrence
of clock signal PH0, the output Q the D flip-flop 149 is set to a
high-voltage state. Upon the next occurrence of the clock signals PH0, the
flip-flop 151 is set. Accordingly, the output Q of the D flip-flop 151 is
at a high-voltage state. The output Q of the flip-flop 151 is used to
derive the signal SAMSTART which is thus activated to designate the
beginning of a look. Also, an inverted version of the signal SAMSTART is
produced at the output of inverter 152. The signals SAMSTART and SAMSTART-
are provided to the A/D address generator 20 and the memory address
generator 28 to bring each to the proper state for the beginning of a
look.
The signal SAMSTART is also provided to the clock input of D flip-flop 153
to generate the signals SAMSET0 and SAMSET1. The Q output of the D
flip-flop 153 is fed back to the input of the D flip-flop 153 so that the
outputs Q and Q of the | | |
