High sensitivity camera device - Patent Review 5483279

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a camera device, and more particularly to a high sensitivity camera device which is made highly sensitive by extending the storage time of the image pickup element than in the conventional device.

2. Description of the Prior Art

FIG. 3 is an example of a prior art highly sensitivity camera device, which shows an RGB three chip type high sensitivity color camera device that uses charge coupled devices (referred to as CCDs hereinafter) as image pickup elements. In each of the RGB channels, a CCD 1 is a photoelectric conversion element which converts an optical information to an electrical signal. A picture signal processing circuit 2 is a signal processing circuit which performs a specific processing such as gamma correction in order to convert the output of the CCD 1 to a picture signal. A frame memory 12 stores the output of the picture signal processing circuit 2 by means of a control signal, sent from a control circuit 11, which is linked to a charge read timing of a read interval control circuit 8, and converts an intermittently output picture to a picture continuous over the entire field or entire frame by repeatedly outputting the same picture until the next charge read. The read interval control circuit 8 is a circuit which controls the time interval of read pulses for transferring the charge stored in a charge storage part of the CCD 1 to a transfer part.

During the normal image pickup, the signal charge stored in the charge storage part is transferred to the transfer part for every field or every frame. However, during the high sensitivity image pickup, the time interval of the read pulses is set to an integral multiple of the field or frame period using an internally or externally set control signal in order to realize high sensitivity by making an arrangement to store the signal charge for a longer time in the charge storage part. The memory control circuit 11 is a circuit for controlling the read or write of the frame memory 12 linked with the charge read timing. A synchronizing signal generating circuit 9 is a circuit which generates a synchronizing signal necessary for the picture signal processing circuit 2 and a timing signal necessary for the read interval control circuit 8 and the memory control circuit 11.

FIG. 4 is a diagram describing the operation during the high sensitivity image pickup for the constitution as shown in FIG. 3, and shows an example in which the signal charge in the CCD 1 is stored over two frame periods. In the figure, signal A stored in the charge storage part of the CCD 1 for two frame periods is output at the time t.sub.O. The signal A output from the CCD 1 is sent through the picture signal processing circuit 2 and is stored in the frame memory 12. In the frame memory 12, the same picture A is output repeatedly over the two frame periods until the time t.sub.1 at which the next signal B is read.

However, in the high sensitivity camera device according to the prior art, intermittent pictures are converted to a continuous picture in terms of a frame memory, so that the picture is changed only in every several fields or several frames, and there is a drawback in that the motion of an object in the picture is unnatural.

SUMMARY OF THE INVENTION

In the high sensitivity camera device according to this invention, in order to realize high sensitivity by storing a signal charge for a period longer than one frame or one field period as well as to convert intermittent pictures to a continuous picture, the following arrangement is provided. Namely, the pictures are changed for every field or every frame to avoid the unnatural appearance of the motion of the objects in the pictures by alternately recording the intermittent signals using two frame memories, and adding the picture signals from the two frame memories by changing the picture signals according to specified ratios in response to the charge read interval.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-mentioned and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of an embodiment of the high sensitivity camera device according to the invention;

FIG. 2 is a timing chart showing the operation of the embodiment in FIG. 1;

FIG. 3 is a block diagram of a prior art high sensitivity camera device; and

FIG. 4 is a timing chart showing the operation of the prior art in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Next, referring to the drawings, this invention will be described. An embodiment of this invention shown in FIG. 1 is an example of application of the invention to an RGB three chip type color camera device using CCDs. In the figure, the same reference numerals as in FIG. 3 indicate identical constituents.

In the figure, the difference from the prior art resides in the fact that two frame memories are prepared for the signal system of each color channel, the outputs of these frame memories are added with the ratio of K and (1-K), and the result is sent to an encoder. Explained in more detail, a frame memory (I) 3 and a frame memory (II) 4 alternately store the output of the picture signal processing circuit 2 by means of a write signal sent from a memory addition ratio control circuit 10, and repeatedly output the same pictures for the periods of several frames until the next write signal is delivered. The read interval control circuit 8 is a circuit which controls the time interval of the read pulses for transferring the charge stored in the charge storage part of the CCD 1. The memory addition ratio control circuit 10 performs the write and read control for the frame memory 3 and the frame memory 4 synchronized with the charge read timing. At the same time, the circuit 10 changes the addition ratio of picture signals from the frame memory 3 and the frame memory 4 by varying the coefficients K (K.ltoreq.1) and (1-K) of the arithmetic circuits 5 and 6. The synchronizing signal generating circuit 9 is a circuit which generates a synchronizing signal necessary for the picture signal processing circuit 2 and a timing signal necessary for the read interval control circuit 8 and the memory addition ratio control circuit 10.

FIG. 2 is a diagram for describing the operation of this invention, which shows an example of storing the signal charge in the CCD 1 over two frame periods. A signal A stored in the charge storage part of the CCD 1 over two frame periods is output at the time t.sub.0. The signal A output from the CCD 1 is sent through the picture signal processing circuit 2 and is stored in the frame memory (I) 3. At the time t.sub.1 two frame periods later, the next signal B output from the CCD1 is sent through the picture signal processing circuit 2 and is stored in the frame memory (II) 4.

During the times t.sub.1 and t.sub.2, 75% of picture signal A from the frame memory 3 and 25% of picture signal B from the frame memory 4 are added in an adder 13 by setting the coefficient K of the arithmetic circuit 5 to 3/4 (0.75), and the result is output. Next, during the times t.sub.2 and t.sub.3, picture signal A from the frame memory 3 and picture signal B from the frame memory 4 are added at 50% each by setting the coefficient K to 2/4, and the result is output. Further, during the times t.sub.3 and t.sub.4, 25% of picture signal A from the frame memory 3 and 75% of picture signal B from the frame memory 4 are added by setting the coefficient K to 1/4 (25%), and the result is output. During the times t.sub.4 and t.sub.5, 100% of picture signal B from the frame memory 4 is output by setting the coefficient K to 0. At the time t.sub.5, a signal C is newly output from the CCD 1, and the content of the frame memory 3 is rewritten to signal C from signal A. Thereafter, during the times t.sub.5 and t.sub.9, the picture signal from the frame memory 3 and the picture signal from the frame memory 4 are added at the ratios of 1:3, 1:1, 3:1 and 1:0, and the result is output, by sequentially changing the coefficient K from 1/4 (0.75), 2/4 (0.5), 3/4 (0.75) to 1 in the reversed order to that employed for the period from t.sub.1 to t.sub.5. It is possible to obtain picture signals free from unnatural appearance of motion by repeating, after the time t.sub.9, the operations the same as those for the period from t.sub.1 to t.sub.9.

Although the present embodiment illustrates the case where high sensitivity is attained by storing the signal charge over two frame periods, the case of storing the signal charge over three or more frame periods can also be handled by properly altering the rate of change of the coefficient K. Moreover, only the case of using CCDs as the image pickup elements has been described in the embodiment, but this invention is not limited to that case alone, and is also applicable to a camera device employing the general solid-state image pickup element such as a MOS device or a charge modulation device (CMD), or the general imaging tube such as a Saticon or a Harpicon.

As described in the above, according to this invention, even in the case of realizing high sensitivity by means of charge storage for a period of an integral multiple of one frame or one field, it is possible to obtain a high sensitivity camera device having an output which is free from unnatural appearance of motion of the objects, by using two frame memories and two arithmetic circuits whose addition coefficients during the period can be controlled.

Although the invention has been described with reference to a specific embodiment, this invention is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment, as well as other embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any modifications or embodiments as fall within the true scope of the invention.

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