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Description  |
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BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device
capable of erasing and writing data after changing condition from standby
to operation.
A so-called UV-EPROM is an ultraviolet-erasable and programmable read only
memory in which data are erased by an irradiation of ultraviolet rays and
electrically written again. A so-called EEPROM is an electrically erasable
and programmable read only memory in which data are electrically erased
and written. In such the UV-EPROM and EEPROM, data of "1" or "0" are read
out on the basis of a determination result of comparing a read potential
V.sub.S (called as V.sub.S1 or V.sub.S0 corresponding to the necessity)
corresponding a level of "1" or "0" of cell data with a reference
potential (called as V.sub.R) in a sense amplifier circuit when the data
are read out.
FIG. 1A is a plan view showing a pattern of a nonvolatile transistor which
is used as memory cell in the EEPROM electrically erasing data, and FIG.
1B is a sectional view showing a section cut by a line 1B--1B in FIG. 1A.
The transistor has a double poly-crystal silicon layer construction, in
which a floating gate 21 is formed by a first poly-crystal silicon layer
and a control gate 23 is constituted by a second poly-crystal silicon
layer. In FIGS. 1A and 1B, numeral 24 denotes a source, 25 denotes a
drain, 27 denotes a silicon substrate, 22 denotes a contact hole, and 28
denotes a data line which is formed by aluminum (Al) and connected through
the contact hole 22 to the drain 25. There will be briefly described below
data writing, reading and erasing operation of the memory cell having the
above construction.
Writing operation is performed by implanting a hot electron into the
floating gate under the condition that a drain potential is set to 8 V,
the control gate potential is 12 V and a source voltage is 0 V. Reading
operation is performed under the condition that the control gate potential
is set to 5 V, the drain potential is 1 V and the source potential is 0 V.
At this time, very few cell current flows between the source and drain
when storage data of the memory cell is "0" (a write mode), and a cell
current having about 100 .mu.A flows between the source and drain when the
storage data is "1" (an erasing mode).
Erasing operation is performed under the condition that the control gate
potential is 0 V, the drain potential is floating and the source potential
is high such as 12 V. At this time, an electron in the floating gate is
extracted to the source by means of a tunnel effect.
There is described a total configuration of the conventional nonvolatile
semiconductor memory device including the above-mentioned nonvolatile
memory cell and sense amplifier with reference to FIG. 2. In FIG. 2, the
memory device comprises a memory cell array 1 in which a plurality of
memory cells are arranged in a matrix shape, a dummy cell array 3
comprised of a dummy cell having the same construction as the plurality of
memory cells along a line in the column direction of the memory cell array
1, a read potential generation circuit 6 for supplying a predetermined
potential a memory cell selected at reading data and for generating a read
potential corresponding to a cell current in the memory cell selected, a
reference potential generation circuit 8 for supplying a predetermined
drain potential to a drain of the dummy cell selected at reading data and
for generating a reference potential at reading data, an equalizing
circuit 7 for equalizing corresponding nodes in the read and reference
potential generation circuits 6 and 8, and a current mirror type amplifier
circuit 10 for comparing the read potential and the reference potential
respectively supplied from the read and reference potentials generation
circuits 6 and 8 and for transmitting a potential corresponding to the
data of the selected memory cell to an output circuit (not shown in FIG.
2).
The read potential generation circuit 6, the equalizing circuit 7, the
reference potential generation circuit 8 and current mirror type amplifier
circuit 10 constitute the conventional sense amplifier which is materially
configured in FIG. 3, for example.
In FIG. 3, numerals P1-P23 denote P-channel enhancement transistors, D1-D12
denote N-channel depression transistors, N1-N24 denote N-channel
enhancement transistors, and I1-I12 denote N-channel transistors each
having a threshold value near 0 volt (V). In FIG. 3, the read potential
generation circuit 6 comprises the transistors P1, D1 and I1 which are
connected in series one another, the transistor N1, the transistors P2, D2
and I2 which are connected in series one another, the transistors N2, N3,
N4, N5, N6, N7 and N8, and the transistors P3 and P4 which are connected
in series each other. A driving voltage V.sub.CC is supplied to sources of
the transistors P1, P2 and P3, and sources of the transistors N1, N2, N4,
N6, N8, I1 and I2 are grounded to the earth. A gate of the transistor D1
is connected to a junction point between the transistors D1 and I1. A
drain of the transistor N1 is connected to a junction point between the
transistors D1 and I1. A gate of the transistor D2 is connected to a
junction point between D2 and I2. A drain of the transistor N2 is
connected to a junction point between the transistors D2 and I2. A driving
voltage V.sub.CC is supplied to a drain of the transistor N3 of which a
gate is connected to the junction point between the transistors D1 and I1
and a source is connected to a node ND.sub.1. A drain of the transistor N4
is connected to the node ND.sub.1 and issues a minute current (for
example, about 1 .mu.A) by a leak control signal S.sub.CL supplied to a
gate thereof in order to prevent a data line from an overcharge when data
"0" are read out for a long time. The transistor N5 has a drain connected
to the node ND.sub.1 and a source connected to one end of a transfer gate
provided between the read potential generation circuit 6 and the memory
cell array 1, and is turned on only when the data are read. A drain of the
transistor N6 is connected to the node ND.sub.1, and a drain of the
transistor N8 is connected to a node ND.sub.2. The node ND.sub.2 is
connected to the node ND.sub.1 through the transistor N7. A driving
voltage V.sub.CC is supplied a source of the transistor P3, and gate and
drain of the transistor P4 are connected to the node ND.sub.2. Each gate
of the transistors P1, P2, P3, N1, N2, N6 and N8 is supplied with a first
control signal S.sub.1 which becomes an "L" at reading data. Furthermore,
a third control signal *S.sub.3 is supplied to a gate of the transistor
N5.
In the read potential generation circuit 6, a series circuit of the
transistors P1, D1 and I1, a series circuit of the transistors P2, D2 and
I2, and the transistors N3 and N7 keep drain potentials of the memory
cells to a optimum value such as 1 V, and transmit a read potential
V.sub.S corresponding to the data of the selected memory cell from the
node ND.sub.2 to the current mirror amplifier circuit 10. The transistor
P4 supplies a constant current as a load transistor of the node ND.sub.2.
Here, the read potential is described. When the data of the memory cell
selected from the memory cell array 1 are "0" level, no current flows in
the memory cell, and a potential such as 3 V is charged in the node
ND.sub.2 through the transistors P3 and P4. When the data of the memory
cell selected are "1" level, since a cell current such as 100 .mu.A flows
in the memory cell, a potential V.sub.SA1 of the node ND.sub.2 becomes
about 1 V, for example, in accordance with a voltage divided ratio between
the load transistor P4 and the selected memory cell.
On the other hand, the reference potential generation circuit 8 is a copy
circuit of the read potential generation circuit 6, and comprises
transistors P11, D11 and I11 connected in series one another, transistors
P12, D12 and I12 connected in series one another, transistors N12, N13,
N14, N15, N16, N17 and N18, and transistors P13 and P14 connected in
series each other. Namely, the transistor P11 of the reference potential
generation circuit 8 corresponds to the transistor P1 of the read
potential generation circuit 6. A gate of the transistor N15 is supplied
with a fourth control signal *S.sub.4.
The reference potential generation circuit 8 is connected through the
transistor N15 and a dummy data line DL.sub.R to the dummy cell 3, and the
transistors P11, D11, I11, P12, D12, I12, N13 and N17 keep a drain
potential of the dummy cell 3 to a predetermined potential. The transistor
P14 supplies a constant current having a reference potential V.sub.R. A
node ND.sub.4 issuing the reference potential is connected to the dummy
data line DL.sub.R through the transistors N17 and N15. Since dummy cells
DC1-DCm are the cells in erasing mode, a cell current of 100 .mu.A flows
at reading the data. The reference potential V.sub.R at this time becomes
a value being a current ratio between the load transistor P14 and the
selected dummy cell. on the other hand, the reference potential V.sub.R
needs to be an intermediate potential between the read potential V.sub.S
when the data "0" are stored in the memory cell CAij and the read
potential V.sub.S when the data "1" is stored. Accordingly, the load
transistor P14 of the reference potential generation circuit 8 has a
predetermined current amount more than that of the corresponding
transistor P4 of the read potential generation circuit 6.
The current mirror type amplifier circuit 10 has a differential amplifier
pair including transistors P21, P22, P23, N22 and N23, a transistor N24,
and inverters IV1, IV2 and IV3. A gate of the transistor P23 is connected
to the node ND.sub.2 issuing the read potential V.sub.S, and a gate of the
transistor P23 is connected to the node ND.sub.4 issuing the reference
potential V.sub.R. A drain of the transistor N24 is connected to drains of
the transistors P22 and N22, and a source of the transistor N24 is
grounded to the earth. The inverters IV1, IV2 and IV3 are connected in
series one another, and inverts a potential of a junction point between
the transistors P22 and N22 to output it to an output circuit.
Accordingly, the read potential V.sub.S and the reference potential
V.sub.R are supplied to the transistors P22 and P23, respectively, and an
output D.sub.B is supplied to the output circuit 12 according to an amount
of these values. The output D.sub.B becomes "1" when the data "0" are
read, and does "0" when the data "1" are read.
The nodes ND.sub.1 and ND.sub.3 are connected by the transistor N20, the
nodes ND.sub.2 and ND.sub.4 are connected by the transfer gate comprised
of the transistors P20 and N21, and these transistors N20, P20 and N21
constitute the equalizing circuit 7. The equalizing circuit 7 comprises
the transistor N20 for equalizing the nodes ND.sub.1 and ND.sub.3, and the
transistors N21 and P20 for equalizing the nodes ND.sub.2 and ND.sub.4.
In the semiconductor memory device having the above configuration, during a
standby where the data are not read, the first control signal S.sub.1
being "H" during the standby is supplied to gates of the transistors N1.
N2, N6, and N8 of the read potential generation circuit 6 and gates of the
transistors N11, N12, N16, and N18 of the reference potential generation
circuit 8 in order to suppress a power consumption, so that all nodes
ND.sub.1, ND.sub.2, ND.sub.3 and ND.sub.4 are grounded to the earth. At
this time, an inverted signal *S.sub.2, which is generated by inversion of
the second control signal supplied to the gates of the transistors P21 and
N24 of the current mirror circuit 10 and the gates of the transistors n20
and N21, is "H" level, and the second control signal supplied to the gate
of the transistor P20 is "L" level.
In the case that there is a condition changed from a standby mode to a
reading mode, changes of several signals *CE, S.sub.1, WL,
*S.sub.2,D.sub.0, V.sub.S and V.sub.R are shown in FIG. 4. In FIG. 4, a
change of a first control signal S.sub.1 from "H" to "L" by receiving a
chip enable signal *CE causes the read potential generation circuit 6 and
reference potential generation circuit 8 to be an operation mode, thereby
outputting data D.sub.0 from the current mirror amplifier circuit 10 to a
not-shown output circuit. Since a potential WL of a word line needs an
enough time to be risen by means of a capacity of the memory cells, it is
impossible to normally read the data during a rising time interval. On the
other hand, since a current flows in a data line by charging a drain
potential of the transistor P4 despite of data the memory cell, a level of
the read potential V.sub.S is low. In the same manner, the dummy data line
DL.sub.R is initially charged. Since the current amount of the transistor
P4 is smaller than that of the transistor P14, a charge on the side of the
memory cells needs a longer time than a charge on the side of the
reference potential. In order to shorten a charge time on the memory cell
side, when a predetermined time passes after the control signal S.sub.1
changes from "H" to "L" , the signal *S.sub.2 changes from "H" to "L" and
the signal S.sub.2 changes from "L" to "H", thereby equalizing both levels
between the nodes ND.sub.2 and ND.sub.4 and between nodes ND.sub.1 and
ND.sub.3, respectively, so as to quicken the initial charge. After that,
when the signal *S.sub.2 changes from "L" to "H", the current mirror
amplifier circuit 10 is driven, thereby PG,10 achieving a high speed
reading with respect to stored data by outputting cell data.
In the conventional nonvolatile semiconductor memory device having the
above construction, in the case of reading the data "0" when the chip
enable signal *CE changes from "H" to "L", if the signals S.sub.2 and
*S.sub.2 change during a time period insufficient to initially charge a
potential to the data line, the levels of the reference potential V.sub.S
and the reference potential V.sub.R are respectively inverted (during
times t.sub.1 and t.sub.2 in FIG. 4). Therefore, operation changes from
"1" reading to "0" reading, thereby resulting a problem of the delay of
reading the data.
Furthermore, in order to quicken the initial reading, the node ND.sub.2 of
the read potential generation circuit 6 is equalized to the node ND.sub.4
of the reference potential generation circuit 8. Therefore, when there are
provided a plurality of the reference potential generation circuits 6, it
is necessary to provide a same number of the reference potential
generation circuits 8 and dummy cell arrays 3, thereby resulting a problem
of increasing an area of chips.
SUMMARY OF THE INVENTION
The present invention is conceived under the above condition, and has an
object to provide a nonvolatile semiconductor memory device capable of
performing a high-speed reading when the device changes from a standby
mode to a operation mode and capable of preventing an increase of a chip
area as small as possible.
A nonvolatile semiconductor device according to a first invention comprises
a memory cell array having an arrangement of a matrix by memory cells
comprised of nonvolatile transistors, a dummy cell having a transistor
construction, read potential generation means for supplying a
predetermined potential to a selected memory cell and for generating a
read potential corresponding to data stored in the selected memory cell on
the basis of a current flowing in the selected memory cell, reference
potential generation means for supplying a predetermined potential to the
dummy cell and for generating a reference potential on the basis of a
current flowing in the dummy cell, reference potential decrease means for
decreasing the reference potential for a constant time when a first
predetermined time passes after a change from a standby mode to an
operation mode, and amplifier means for comparing the read potential and
the reference potential after a second predetermined time passes after the
change from the standby mode to the operation mode and for issuing an
output being amplified corresponding a comparison result.
A nonvolatile semiconductor device according to a second invention
comprises a memory cell having an arrangement of a matrix by memory cells
comprised of nonvolatile transistors, a dummy cell having a transistor
construction, read potential generation means for supplying a
predetermined potential to a selected memory cell and for generating a
read potential corresponding to data stored in the selected memory cell on
the basis of a current flowing in the selected memory cell, reference
potential generation means for supplying a predetermined potential to the
dummy cell and for generating a reference potential on the basis of a
current flowing in the dummy cell, read potential initial charge means for
increasing the read potential for a constant time when a first
predetermined time passes after a change from a standby mode to an
operation mode, and amplifier means for comparing the read potential and
the reference potential after a second predetermined time passes after the
change from the standby mode to the operation mode and for issuing an
output being amplified corresponding a comparison result.
By the nonvolatile semiconductor memory device according to the first
invention having the above construction, when the first predetermined time
passes after the memory device starts operation from the standby mode, the
reference potential decrease means reduces the reference potential during
the constant time. By this, it is possible to shorten the delay of reading
operation caused by an initial charge as little as possible. Furthermore,
since there is no equalization between the read potential side and the
reference potential side in this invention different from the conventional
device, a plurality of read potential generation means can commonly use
the same reference potential generation means, thereby resulting a chip
area as small as possible.
By the nonvolatile semiconductor memory device according to the second
invention having the above construction, when the first predetermined time
passes after the memory device starts operation from the standby mode, the
read potential increase means increases the read potential (a rapid
charge) during the constant time. By this, it is possible to shorten the
delay of reading operation caused by an initial charge as little as
possible. Furthermore, since there is no equalization between the read
potential side and the reference potential side in this invention
different from the conventional device, a plurality of read potential
generation means can commonly use the same reference potential generation
means, thereby resulting a chip area as small as possible.
As described above, even though the initial charge to the data line is
insufficient, since the nonvolatile semiconductor memory device according
to the present invention sets both the potentials in the manner that the
reference potential is sufficient to be lower than the read potential
during a first predetermined time passing from the standby mode to the
operation mode, the reference potential generation circuit can be commonly
used, thereby reducing the entire chip area as small as possible and
reading the data in high-speed when the memory device changes from the
standby mode to the operation mode.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIGS. 1A and 1B are a plan view and a sectional view for schematically
explaining a construction of a nonvolatile transistor;
FIG. 2 is a block diagram showing a schematic configuration of the
conventional nonvolatile semiconductor memory device;
FIG. 3 is a circuit diagram showing a detailed configuration of the
conventional nonvolatile semiconductor memory device;
FIG. 4 is a timing chart for explaining operation of the conventional
nonvolatile semiconductor memory device;
FIG. 5 is a block diagram showing a schematic configuration of a
nonvolatile semiconductor memory device according to a first embodiment of
the present invention;
FIG. 6 is a circuit diagram showing a detailed configuration of the
nonvolatile semiconductor memory device according to the first embodiment
of the present invention;
FIG. 7 is a block diagram showing a concrete configuration of the
nonvolatile semiconductor memory device according to the first embodiment
of the present invention;
FIG. 8 is a timing chart for explaining operation of the nonvolatile
semiconductor device according to the first embodiment;
FIG. 9 is a block diagram showing a schematic configuration of a
nonvolatile semiconductor memory device according to a second embodiment
of the present invention;
FIG. 10 is a circuit diagram showing a detailed configuration of the
nonvolatile semiconductor memory device according to the second embodiment
of the present invention;
FIG. 11 is a timing chart for explaining operation of the nonvolatile
semiconductor device according to the second embodiment of the present
invention;
FIG. 12 is a block diagram showing a schematic configuration of a
nonvolatile semiconductor memory device according to a third embodiment of
the present invention;
FIG. 13 is a circuit diagram showing a detailed configuration of the
nonvolatile semiconductor memory device according to the third embodiment
of the present invention;
FIG. 14 is a timing chart for explaining operation of the nonvolatile
semiconductor device according to the third embodiment of the present
invention;
FIG. 15 is a block diagram showing a concrete configuration of a
nonvolatile semiconductor memory device according to a fourth embodiment
of the present invention;
FIG. 16 is a block diagram showing a concrete configuration of a
nonvolatile semiconductor memory device according to a fifth embodiment of
the present invention; and
FIG. 17 is a block diagram showing a concrete configuration of a
nonvolatile semiconductor memory device according to a sixth embodiment of
the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
There will now be described in detail preferred embodiments of a
nonvolatile semiconductor memory device (hereinunder also called as a
memory device) in reference with FIGS. 5-17.
First, a memory device according to a first embodiment of the present
invention is described in reference with FIGS. 5-8. The memory device
according to the first embodiment is the device in which the equalizing
circuit 7 of the conventional memory device shown in FIG. 2 is eliminated
and reference potential decrease means (circuit) 9 is added to the
conventional memory. Other components such as the memory cell array 1,
dummy cell array 3, read potential generation circuit 6, reference
potential generation circuit 8, and a current mirror type amplifier
circuit 10 are the same as those of the conventional device shown in FIG.
2.
A concrete configuration is described according to a detailed circuit
diagram shown in FIG. 6. The memory device according to the first
embodiment has a configuration in which the equalizing circuit 7 is
eliminated from the conventional memory device shown in FIG. 3 and
comprising the transistor N20 for equalizing the nodes ND.sub.1 and
ND.sub.3 and the transistors N21 and P20 for equalizing the nodes ND.sub.2
and ND.sub.4, the reference potential decrease circuit 9 comprising
N-channel enhancement type transistors N30 and N31 connected in series
each other, and a third control signal S.sub.5 is added to gates of the
transistors P21 and N24 of the current mirror type amplifier circuit 10. A
drain of the transistor N30 of the reference potential decrease circuit 9
is connected to the node ND.sub.3, and a gate of the transistor N30
receives a control signal *S.sub.2 which becomes from "H" to "L" after the
constant time passes after the memory device becomes in an operation mode.
The transistor N31 has a drain connected to a source of the transistor
N30, a source being grounded to the earth, and a gate receiving a driving
voltage V.sub.CC. Accordingly, the reference potential decrease circuit 9
decreases the reference potential V.sub.R during the first predetermined
time after changing the condition in the operation mode. The third control
signal S.sub.5, which is added to the gates of the transistors P21 and N24
of the current mirror type amplifier circuit 10, is a signal that changes
from "H" to "L" after the constant time further passes after the signal
*S.sub.2 changes to "L".
FIG. 7 shows a configuration of the nonvolatile semiconductor memory device
having as memory cells the nonvolatile transistors having the above
construction. In FIG. 7, a memory cell array 1 comprises a plurality (m.n)
of memory cells CA11, . . . , CAmn which are arranged in a matrix. Each
memory cell CAij (i=1, . . . , m, j=1, . . . , n), as shown in FIGS. 1A
and 1B, is a nonvolatile transistor comprised of a source, a drain, a
floating gate and a control gate. Control gates of memory cells CAk1, . .
. , CAkn of an n number arranged along the same row (such as k-th row) are
commonly connected to a corresponding word line WLk within an m number of
word lines WL1, . . . , WLm. Drains of mmory cells CA1j, . . . , CAmj of
an m number arranged along the same column (such as j-th column) are
commonly connected to a corresponding data line DLj within an n number of
data lines DL1, . . . , DLn. To sources of memory cells CAij, a potential
V.sub.M which is outputted from a cell source potential supply circuit and
has a high potential at erasing the data and potential V.sub.SS except an
erasing condition.
A selection of the m number of word lines WL1, . . . , WLm is performed by
a row decoder 2 which selects one word line corresponding to a row
address. On the other hand, a selection of the n number of data lines DL1,
. . . , DLn is performed by a column decoder 4. The column decoder 4
selects one data line corresponding to the column address by selecting a
transfer gate CTj connected to the data line DLj (j=1, . . . , n). Namely,
the data line is selected by turning on only a transder gate connected to
the data line corresponding to the column address. Each data line DLj
(j=1, . . . , n) is connected to the read potential generation circuit 6
through the corresponding transfer gate CTj. The read potential generation
circuit 6 supplies a predetermined potential (for example, 1 V in the
memory cell comprised of the transistor shown in FIGS. 1A and 1B) to a
drain of the selected memory cell at reading the data, and generates the
read potential V.sub.S corresponding to the cell current of the selected
memory cell. The read potential V.sub.S is transmitted to the current
mirror amplifier circuit 10 as input potential corresponding to the values
"1" and "0" of the cell data, respectively.
On the other hand, the dummy cell array 3 comprises a m number of dummy
cells DC1, . . . , DCm. The dummy cell DCi (i=1, . . . , m) is a
nonvolatile transistor having the same construction as the memory cell
CAij, and has a control gate connected to the corresponding word line WLi,
a drain connected to a dummy data line DL.sub.R, and a source receiving a
potential V.sub.D. The dummy data line DL.sub.R is connected to the
reference potential generation circuit 8. The reference potential
generation circuit 8 supplies a predetermined drain current to the drain
of the selected dummy cell at reading the data through the data line
DL.sub.R, and transmits the reference potential V.sub.R at reading the
data to the amplifier circuit 10. The amplifier circuit 10 compares the
reference potential V.sub.R and the read potential V.sub.S so as to output
a potential corresponding to the data of the selected memory cell to an
output circuit 12. The output circuit 12 outputs the data of the selected
memory cell on the basis of the potential transmitted from the amplifier
circuit 10.
Next, operation of the first embodiment is described in reference with FIG.
8. FIG. 8 is a waveform diagram showing operation at reading "0" data when
the memory device of the first embodiment becomes in the operation mode.
In FIG. 8, the signal *CE shows that the memory device becomes in the
operation mode, for example, a chip enable signal. When the memory device
receives the signal *CE, the first control signal S.sub.1 for activating
the memory device changes from "H" to "L" After that, the word line WL
rises to select the memory cell. At this time, the load transistor N3 of
the node ND.sub.1 and the load transistor N13 of the node ND.sub.3
respectively start a charge. Furthermore, the inverted signal *S.sub.2 of
the second control signal S.sub.2 at this time is "H" level, and the level
of the reference potential V.sub.R is reduced by the reference potential
decrease circuit 9.
On the other hand, on the memory cell side, the data line DL.sub.S is
charged by the load transistor P4. With the advance of the charge, a
current amount decreases and the read potential V.sub.S increases to be
higher than the level of the reference potential V.sub.R. Here, when the
signal *S.sub.2 is caused to be from "H" to "L", the transistor N30 of the
reference potential decrease circuit 9 is turned off, the reference
potential V.sub.R is determined by the cell current of the dummy cell.
After the difference between the reference potential V.sub.R and the read
potential v.sub.S is sufficient to be large, the fifth control signal
S.sub.5 changes from "H" to "L", and the current mirror type amplifier
circuit 10 is driven so as to issue an output D.sub.O at reading "0" data.
During the initial charging when the signal *S.sub.2 is "H", the level of
the reference potential V.sub.R is set to be higher than the read
potential V.sub.S level at reading "1" data. Accordingly, since the levels
of the reference potential V.sub.R and the read potential V.sub.S are not
inverted at reading "1" data, a read of "1" data does not delay. The level
of the reference potential V.sub.R at this time is determined by
transistor N30 of the reference potential decrease circuit 9.
As described above, by the first embodiment of the present invention, it is
possible to shorten the delay of data reading caused by the initial charge
as small as possible when the memory device becomes from the standby mode
to the operation mode, thereby performing a high-speed reading.
Furthermore, since it is unnecessary to perform the equalization, a
plurality of the read potential generation circuits can own the reference
potential generation circuit jointly, thereby reducing the chip area as
small as possible.
In the above first embodiment, even though an N-channel enhancement type
transistor applies to the transistor N30 of the reference potential
decrease circuit 9, a nonvolatile transistor as the same type as the
memory cell CAij can be used as the transistor N30.
Furthermore, even though the control signal *S.sub.2 is different from the
control signal S.sub.5 in the first embodiment, the signal S.sub.5 is the
same as the signal *S.sub.2.
Still furthermore, even though the plurality of the dummy cells DCi are
used corresponding to each word line WLi in the first embodiment, a
provision of one dummy cell (both of the N-channel transistor and the
nonvolatile transistor may be used) results the same effect.
Next, a memory device according to the second embodiment of the present
invention is described with reference to FIGS. 9-11.
The memory device according to the second embodiment, as shown in a block
diagram of FIG. 9, read potential initial charge means 11 is added to the
conventional memory device shown in the block diagram of FIG. 2, which is
connected in parallel between the read potential generation circuit 8 and
the current mirror type amplifier circuit 10. Other components are the
same as the conventional memory device which has such as the memory cell
array 1, dummy cell array 3, read potential generation circuit 6,
reference potential generation circuit 8 and current mirror type amplifier
circuit 10.
Next, there will be described a concrete configuration according to a
detailed circuit diagram shown in FIG. 10. The second embodiment
eliminates the transistors N.sub.20, N.sub.21 and P20 for equalizing the
nodes ND.sub.1 and ND.sub.3 and the nodes ND.sub.2 and ND.sub.4 in the
conventional memory device shown in FIG. 3, adds a read potential initial
charge circuit 11 comprised of P-channel enhancement transistors P30 and
P31 connected in series each other, and supplies the control signal
S.sub.5 to gates of the transistors P21 and P24 of the current mirror type
amplifier circuit 10. In the read potential initial charge circuit 11, a
drain and a gate of the transistor P31 are connected to the node ND.sub.2,
a drain of the transistor P30 is connected to a source of the transistor
P31, and | | |
