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Description  |
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RELATED APPLICATIONS
This application is related to the co-pending U.S. application Ser. No.
08/259,272, entitled "Hierarchical Connection Method, Apparatus and
Protocol", and U.S. application Ser. No. 08/179,900, entitled "Remotely
Controllable Addressable Shadow Port and Protocol for Serial Bus
Networks", both having the same effective filing date as the present
application.
FIELD OF THE INVENTION
This invention relates generally to the use of serial buses to communicate
between devices, circuits, systems, boards or networks, and in particular
to serial backplane buses. The invention is applicable to any environment
where a serial communication bus is or may be used, including circuit
boards, backplanes, integrated circuits, and systems.
BACKGROUND OF THE INVENTION
In producing integrated circuits or circuit boards for systems, the use of
a serial communication bus for test and debug is rapidly becoming a
standard practice. The use of the serial bus allows the system, circuit
board or integrated circuits to be tested and connections to be confirmed
without the need for intrusive hardware or test probes. This is
particularly important as packaging of the devices reaches higher
densities and for multiple integrated circuits packaged on a single
module, or for systems where the circuitry is not available for physical
access for other reasons.
Industry has developed and continues to develop standard protocols for
serial busses of this kind. The standards are necessary and desirable to
insure that parts and boards acquired from various vendors will be able to
communicate on a common bus. In general, the concepts of this invention
apply to any type of serial bus. However, to clarify the description of
the invention it will be described as being a feature added to a well
understood and documented IEEE/ANSI standard serial bus designed for
testing ICs at the board level, referred to as IEEE/ANSI standard 1149.1
or more commonly as the JTAG boundary scan standard.
The IEEE/ANSI 1149.1 standard describes a 4-wire serial bus that can be
used to transmit serial data to and receive serial data from multiple ICs
on a board. While the 1149.1 serial bus was originally developed to
serially access ICs at the board level, it can also be used at the
backplane level to serially access ICs on multiple boards.
The 1149.1 standard describes a 4-wire serial bus that can be used to
transmit serial data between a serial bus master and slave device. While
1149.1 was developed to serially access ICs on a board, it can be used at
the backplane level to serially access boards in a backplane. 1149.1 has
two serial access configurations, referred to as "ring" and "star", that
can be used at the backplane level.
In a backplane 1149.1 ring configuration, all boards in the backplane
directly receive the control outputs from a primary serial bus master
(PSBM) and are daisy chained between the PSBM's data output and data
input. During scan operation, the PSBM outputs control scan data through
all boards in the backplane, via its test data output (TDO) and test data
input (TDI) bus connections. The problem associated with the ring
configuration is that the scan operation only works if all the boards are
included in the backplane and are operable to scan data from their TDI
input to TDO output signals. If one of the boards is removed or has a
fault, the PSBM will be unable to scan data through the backplane. Since
the ring configuration does not allow access to remaining boards when one
is removed or disabled, it does not fully meet the needs of a serial bus
for backplane and large system applications.
In a backplane 1149.1 star configuration, all boards in the backplane
directly receive the test clock (TCK) and TDI signals from the PSBM and
output a TDO signal to the PSBM. Also each board receives a unique test
mode select (TMS) signal from the PSBM. In the star configuration only one
board is enabled at a time to be serially accessed by the PSBM. When a
board is enabled, the TMS signal associated with that board will be active
while all other TMS signals are inactive. The problem with the star
configuration is that each board requires its own TMS signal. In a
backplane with 100 boards, the PSBM would have to have 100 individually
controllable TMS signals, and the backplane would have to have traces for
each of the 100 TMS signals. Due to these requirements, star
configurations are typically not considered for backplane applications.
Two IEEE serial bus standards, P1149.5 and P1394, are in development for
use in system backplanes. Since these standards are being specifically
designed for backplane applications, they appear to overcome the problems
stated using the 1149.1 standard bus as a backplane bus. However, the
protocols of these anticipated standards are different from the 1149.1
protocol and therefore methods must be defined to translate between them
and 1149.1.
The IEEE P1149.5 standard working group is currently defining a module test
and maintenance bus that can be used in system backplane environments.
P1149.5 is a single master/multiple slave bus defined by a 5-wire
interface. The P1149.5 bus master initiates a data transfer operation by
transmitting a data packet to all slave devices. The data packet consists
of an address and command section. The slave device with a matching
address is enabled to respond to the command section of the data packet as
described in the P1149.5 standard proposal.
Interfacing an P1149.5 bus into an 1149.1 bus environment requires new
additional system hardware and software, and designers with a detailed
understanding of both bus types. Therefore, in using P1149.5 to interface
into an 1149.1 environment, an unnecessary complication is added to an
otherwise simple serial access approach. Another problem is that the
bandwidth of the 1149.1 serial data transfer will be adversely affected by
the 1149.5 to 1149.1 protocol conversion process and hardware.
The IEEE P1394 standard working group is currently defining a 2-wire
high-speed serial bus that can be used in either a cable or system
backplane environment. The P1394 standard, unlike P1149.5, is not a single
master/multiple slave type bus. In P1394, all devices (nodes) connected to
the bus are considered to be of equal mastership. The fact that P1394 can
operate on a 2-wire interface makes this bus attractive in newer 32-bit
backplane standards where only two wires are reserved for serial
communication. However, there are problems in using P1394 as a backplane
test bus to access 1149.1 board environments.
First, P1394 is significantly more complex in operation than P1149.1, thus
devices designed to translate between P1394 and 1149.1 may be costly.
Second, P1394 is not a full time test bus, but rather it is a general
purpose serial communication bus, and its primary purpose in a backplane
environment is to act as a backup interface in the event the parallel
interface between boards becomes disabled. While 1149.1 test access can be
achieved via P1394, it will be available only during time slices when the
bus is not handling functional operations. Thus on-line 1149.1 test bus
access will be limited and must be coordinated with other transactions
occurring on the P1394 bus. This will require additional hardware and
software complexity.
Another method of achieving a backplane to board level interface is to
extend the protocol defined in the 1149.1 standard. Such an approach has
been described in a paper presented at the 1991 International Test
Conference by D. Bhavsar, entitled "An Architecture for Extending the IEEE
Standard 1149.1 Test Access Port to System Backplanes". The Bhavsar paper
describes a method of extending the protocol of 1149.1 so it can be used
to access an interface circuit residing between the backplane and board
level 1149.1 buses. The interface circuit responds to 1149.1 protocol
transmitted over the backplane bus to load an address. If the address
matches the address of the interface circuit, the interface circuit is
connected to the backplane. After the interface circuit is connected to
the backplane, additional 1149.1 protocol is input to the interface
circuit to connect the backplane and board level 1149.1 buses. Following
this connection procedure, the board level 1149.1 bus can be controlled by
the backplane 1149.1 bus. Bhavsar's approach also has problems that limit
its effectiveness as a general purpose 1149.1 bus backplane to board
interface.
Bhavsar's approach does not allow selecting one board, then selecting
another board without first resetting the backplane and board level 1149.1
buses, by transitioning them into their test logic reset (TLRST) states.
Entering the TLRST state causes test conditions setup in the ICs of a
previously selected board to be lost due to the test reset action of the
1149.1 bus on the test access ports (TAPs) of the ICs.
Also, it is often desirable to select and initiate self-tests in a selected
group of backplane boards. However, since the Bhavsar approach requires
resetting the 1149.1 bus each time a new board is selected, it is
impossible to self-test more than one board at a time, because resetting
the bus aborts any previously initiated self-test.
Thus, a need exists for a simple, efficient and effective means to provide
support for the use of an 1149.1 standard serial bus in a multiple-board
backplane environment. The invention described herein meets this need.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, a backplane access approach
which provides a method of using the 1149.1 bus at the backplane level
without incurring the problems previously described is disclosed. Using
this approach, it is envisioned that one homogeneous serial bus may be
used throughout a system design, rather than translating between multiple
serial bus types. Employing a common serial bus in system designs can
simplify software and hardware engineering efforts, since only an
understanding of one bus type is required.
In a first embodiment of the invention a circuit, called an addressable
shadow port (ASP), and a protocol, called a shadow protocol, is described
which provides a simple and efficient method of directly connecting 1149.1
backplane and board buses together. When the 1149.1 backplane bus is in
either its run test/idle (RT/IDLE) or test logic reset (TLRST) states, the
ASP circuit can be enabled, via the shadow protocol of the invention, to
connect a target board's 1149.1 serial bus up to the backplane 1149.1
serial bus. After the shadow protocol herein described has been used to
connect the target board and backplane buses together, the protocol of the
invention becomes inactive and becomes transparent to the operation of the
1149.1 bus protocol.
The use of the invention results in several improvements over the use of
the 1149.1 standard in a system or backplane environment or the other
prior art extension approaches in terms of the efficiency of data
transfers, the ability to remove boards or support backplanes where not
all slots are populated, the ability to keep the 1149.1 bus in the idle
state when selecting and deselecting boards, and the advantageous use of
the well understood 1149.1 serial bus without the need for additional bus
design or translator circuitry to accomplish these improvements.
An additional embodiment is disclosed wherein a single board contains
multiple 1149.1 scan paths, each coupled to the backplane serial bus by
means of an individually addressable shadow port, for additional
flexibility in scan path and testability design. Other preferred
embodiments and enhancements are also disclosed.
Further embodiments extend the ASP circuit and protocol to allow the local
serial bus to be selectively controlled by a remote serial bus master
circuit or alternatively by a primary serial bus master located on the
backplane serial bus. The ASP capabilities are extended to allow input and
output of parallel data to a memory via the ASP and the primary serial bus
master. The ASP circuit and protocol are further extended to allow
interrupt, status and command information to be transferred between a
remote serial bus master and a primary serial bus master, to support
sophisticated commands and remote functions autonomously executed by the
remote serial bus master.
The invention is then applied to hierarchically organized systems, wherein
multiple backplane systems are linked together through networks coupled in
a multiple level environment. The ASP capabilities are extended to allow
the primary serial bus master to directly select and send and receive data
and commands to any board within the hierarchy.
An additional embodiment is disclosed wherein the circuitry and protocol of
the invention is adapted for use with the proposed two wire serial
backplane busses being considered by some in industry. Modifications and
enhancements to make the invention compatible with such a bus are
described.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1 depicts a typical backplane to board connection using the 1149.1 bus
standard;
FIG. 2 depicts a state diagram of the states the 1149.1 bus transitions
through in operation;
FIG. 3 depicts a typical prior art ring configuration of an 1149.1 standard
bus used in a backplane environment;
FIG. 4 depicts a typical prior art star configuration of an 1149.1 bus in a
backplane environment;
FIG. 5 depicts an embodiment of a connection between a serial bus master
and a single board in a backplane environment using the 1149.1 standard
bus and incorporating the addressable shadow port of the invention;
FIG. 6 depicts a system backplane having multiple boards connected to a
serial bus master with a 1149.1 serial bus using the protocol and hardware
of the invention;
FIG. 7 depicts a block level diagram of the circuitry required to implement
the addressable shadow port circuit of the invention;
FIG. 8 depicts the timing of a transfer of an IDLE bit-pair of the protocol
of the invention;
FIG. 9 depicts the timing of a transfer of a SELECT bit-pair of the
protocol of the invention;
FIG. 10 depicts the timing of a transfer of a logic 1 data bit-pair of the
protocol of the invention;
FIG. 11 depicts the timing of a transfer of a logic 0 data bit-pair of the
protocol of the invention;
FIG. 12 depicts the transactions which occur between the serial bus master
and the addressable shadow port of the invention during the select and
acknowledge transactions of the shadow protocol;
FIG. 13 depicts the signal transitions on the serial bus lines which occur
during the select and acknowledge transactions between the addressable
shadow port and the serial bus master using the protocol of the invention;
FIG. 14 is a state diagram depicting the states the transmitter circuitry
resident in the serial bus master and the addressable shadow port of the
invention transitions through during the transactions of the protocol;
FIG. 15 is a state diagram depicting the states the receiver circuitry
resident in the serial bus master and the addressable shadow port of the
invention transitions through during the transactions of the protocol;
FIG. 16 is a state diagram depicting the states the master control
circuitry of the serial bus master circuit transitions through during the
transactions of the protocol of the invention;
FIG. 17 is a state diagram depicting the states the slave control circuitry
of the addressable shadow port circuit transitions through during the
transactions of the protocol of the invention;
FIG. 18 depicts the subcircuits required in one preferred embodiment of the
addressable shadow port circuit of the invention;
FIG. 19 depicts an alternative embodiment wherein an integrated circuit
with multiple secondary ports contains several independently addressable
shadow port circuits each connected to a single primary port coupled to
the serial bus;
FIG. 20 depicts an integrated circuit incorporating the invention and
containing the addressable shadow port of the invention, a primary port
coupled to the serial backplane bus, and an internal serial bus coupled to
a plurality of application specific logic circuitry blocks.
FIG. 21 depicts a typical circuit board located on a system backplane,
coupled to a serial bus master by means of a system level serial bus and
incorporating the remote serial bus master and remotely controllable
addressable shadow port of the invention;
FIG. 22 depicts one preferred embodiment of the remote serial bus master
circuit of the invention;
FIG. 23 depicts an embodiment of the primary serial bus master of the
invention;
FIG. 24 depicts the select protocols of the invention, including an example
of the simple select message and an expanded select message using the
protocol of the invention;
FIG. 25 depicts the acknowledge protocols of the invention, including an
example of the simple acknowledge message and an expanded acknowledge
message using the protocol of the invention;
FIG. 26 depicts the select and acknowledge protocols of the invention for
simple command transfers between a primary serial bus master and a remote
serial bus master of the invention;
FIG. 27 depicts the write command select and acknowledge protocols of the
invention;
FIG. 28 depicts the read command select and acknowledge protocols of the
invention;
FIG. 29 depicts a block diagram of the circuitry of the remotely
controllable addressable shadow port circuit of the invention;
FIG. 30 depicts a block diagram of the circuitry required for a board
having the RCASP circuit adopted for a two wire backplane serial bus;
FIG. 31 depicts a block diagram of the RCASP circuit adopted for a two wire
backplane serial bus and having a two wire primary port;
FIG. 32 depicts a block diagram of a one-level bus connection and the HASP
protocol scheme of the invention;
FIG. 33 depicts a block diagram of a two-level bus connection and the HASP
connection protocol scheme of the invention;
FIG. 34 depicts a block diagram of a three-level bus connection and the
HASP connection protocol scheme of the invention;
FIG. 35 depicts an example of the select and acknowledge protocol message
transfers of the invention in an Mth level system;
FIG. 36 depicts an example of local and global reset messages in an Mth
level system using the HASP select protocol of the invention;
FIG. 37 depicts the synchronous timing of message transfers using the
invention in a two level system;
FIG. 38 depicts the synchronization of message transfers using D type F/Fs
with the HASP circuitry of the invention in a two level system;
FIG. 39 depicts a state diagram of the SBM Transmitter circuitry of the
HASP circuit of the invention;
FIG. 40 depicts a state diagram of the SBM Receiver circuitry of the HASP
circuit of the invention;
FIG. 41 depicts a state diagram of the SBM Master Control circuitry of the
invention;
FIG. 42 depicts a state diagram of the HASP receiver circuitry of the
invention;
FIG. 43 depicts a state diagram of the HASP transmitter circuitry of the
invention;
FIG. 44 depicts a state diagram of the HASP Slave Control Circuit of the
invention;
FIG. 45 depicts a block diagram of the HASP Circuit implementation;
FIG. 46 depicts a two wire connection between a primary serial bus master
and an RCASP circuit via N-level HASP circuits of the invention;
FIG. 47 depicts a HASP circuit adapted for two wire communication between
the HASP's primary and secondary ports.
FIG. 48 depicts a block diagram of a typical multiple cable environment
coupling application circuitry;
FIG. 49 depicts a block diagram of a single cable configuration coupling
the same application circuitry of FIG. 46 and incorporating the HASP
circuitry of the invention;
Corresponding numerals and symbols in the different figures refer to
corresponding parts unless otherwise indicated.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Within this specification, the following abbreviations are used hereafter:
SBM indicates the serial bus master of the invention, a circuit capable of
addressing and accessing other boards coupled to the serial bus;
PSBM indicates the primary serial bus master;
ASP indicates the addressable shadow port hardware of the invention;
TAP indicates a test access port, the standard hardware interface of
devices coupled to the 1149.1 bus;
TMS indicates the Test Mode Select line, the control line of the 1149.1
bus;
TDO indicates the Test Data Output line, one of the lines the 1149.1 bus
transfers serial data on;
TDI indicates the Test Data Input line, one of the lines the 1149.1 bus
transfers data on;
TCK indicates the Test Clock line, the common clock line used by aH of the
devices coupled to the 1149.1 serial bus to synchronize transfers between
devices.
A serial bus slave is a circuit or device that can be enabled and
communicated to by a serial bus master via the serial bus network. A
serial bus slave as used in this application refers to any well defined
logic block or circuitry having input and output circuitry operable to
allow it to be interfaced onto a serial bus. For simplicity, this
application treats serial bus slaves as being printed circuit boards,
comprised of multiple ICs that are plugged into a system backplane.
However, it should be understood that the invention could be used in
applications which define serial bus slaves as being: (1) subcircuits in
an IC, (2) ICs on a common substrate (i.e. multi-chip modules), (3) ICs on
a printed circuit board, (3) boards plugged into a system backplane, (4)
backplanes in a subsystem (5) subsystems in a system, or (6) systems
connected to other systems.
A serial bus master is a circuit or device that can output the necessary
control signals to enable communications with a serial bus slave via the
serial bus network. Throughout the remainder of this application, the
serial bus master will be referred to as an SBM.
In FIG. 1, an SBM 1 is depicted as connected to an example board 3 via a
connector 2 coupled to the standard 4-wire 1149.1 serial bus as
contemplated by the existing art. Inside board 3, the 4-wire serial bus is
connected to various integrated circuits (ICs) IC1, IC2, ICN via a
standard IC level serial interface circuit referred to as a test access
port (TAP). The TAP consists of a control circuit that responds to the
4-wire serial bus to enable and disable serial access to the IC. The TAP
pins used to connect up to the serial bus consist of a serial test data
input (TDI) pin, a serial test data output (TDO) pin, a test clock (TCK)
pin, and a test mode select (TMS) pin. The TAP's TDI pin is a
unidirectional data input signal used for shifting serial data bit streams
into the IC. The TAP's TDO pin is a unidirectional data output signal used
for shifting serial data bit streams out of the IC. The TAP's TCK pin is a
unidirectional clock input signal used for clocking the serial data bit
streams into and out of the IC, via the TDI and TDO pins. The TAP's TMS
pin is a unidirectional control input signal used for enabling the
shifting of the serial data bit streams into and out of the IC.
In operation, board 3 is plugged into a backplane, and the TAP of each IC
IC1, I2, etc. is connected in parallel to the TMS and TCK backplane serial
bus signals from the SBM. Also each IC's TAP is serially linked or
daisychained, via their TDI and TDO pin connections, to form a single
serial data path between the backplane's TDI input and TDO output signals.
From the backplane, the SBM can drive TMS and TCK signals into the board
to cause the TAPs of the ICs to serially shift data from the SBM's TDO
output signal, into the board, through each IC on the board, from the
board, and back into the SBM's TDI input signal.
To understand the relationship between the invention and the standard
1149.1 serial bus, an overview of the 1149.1 serial bus operation is
required. In FIG. 2 a simplified diagram of the operation of the 1149.1
serial bus is shown. Referring to FIG. 1, in operation the SBM outputs TMS
and TCK control signals to the controllers of the TAPs of each IC on the
board to cause the ICs to operate in step with the serial bus states of
FIG. 2. The TAP of each IC operates synchronous to the TCK clock output
from the SBM and responds to the TMS control output from the SBM, to
transition into and out of the serial bus states of FIG. 2. The serial bus
states include: RESET, IDLE, Select Data Scan (SELDS), Data Scan Sequence
(DSS), Select Command Scan (SELCS), and Command Scan Sequence (CSS).
Referring to the board example depicted in FIG. 1, a description of each of
the 1149.1 bus states is given in the following paragraphs. The board of
FIG. 1 is comprised of ICs 5, with each IC having a TAP interface 7 and
connection to the 1149.1 bus via the backplane connector 2. The TAP
interfaces of each IC on board 3 are designed to receive and respond to
the serial bus states of FIG. 2 to control serial access of the ICs. The
SBM 1 connected to the backplane is designed to generate and transmit the
serial bus states of FIG. 2 to serially access the ICs on the board.
RESET state--In response to a TMS input, the TAP of each IC on the board
can be made to transition from any state into the RESET state as shown in
FIG. 2. While in the RESET state, the TAP forces test logic in the IC into
a disabled condition so that the test logic cannot interfere with the
normal operation of the IC. The serial bus forces the TAP of each IC to
remain in the RESET state while the TMS signal is high.
IDLE state--In response to a TMS input, the TAP of each IC can be
transitioned from any state into the IDLE state. While in the IDLE state,
the TAP responds to TMS control input to: (1) remain in the idle state,
(2) enter into the data scan sequence, (3) enter into the command scan
sequence, or (4) enter the reset state.
Data Scan Sequence--In response to TMS input, the TAP of each IC can be
transitioned from the IDLE state into a data scan sequence (DSS), via the
select data scan (SELDS) state. While the TAP is in the DSS state,
additional TMS control is input to cause data to be shifted through the
ICs test data register from TDI to TDO. After the shift operation is
completed, additional TMS control is input to cause the TAP to exit the
DSS and enter the IDLE state.
Command Scan Sequence--In response to a TMS signal input, the TAP of each
IC be transitioned from the IDLE state into a command scan sequence (CSS),
via the SELDS and Select Command Scan (SELCS) states. While the TAP is in
the CSS, additional TMS control is input to cause data to be shifted
through the ICs test command register from TDI to TDO. After the shift
operation is completed, additional TMS control is input to cause the TAP
to exit the CSS and enter the IDLE state.
In summary, the ICs on the board, when connected to the backplane 1149.1
serial bus signals, operate in step with the serial bus as it transitions
through or operates in any of its defined states. The TMS signal, output
from the SBM, is used to control the operation of the TAP of each IC on
the board.
FIG. 3 depicts a backplane with boards BOARD1, BOARD2 to BOARDN coupled to
the 1149.1 standard or JTAG bus in the prior art "ring" configuration,
which is further coupled to serial bus master SBM. | | |
