A synchronous counter performing a count operation in response to an input of a clock having a fixed frequency. The synchronous counter including a first transmission gate receiving a counter initialization signal and transferring the counter output signal to a carry output node when the counter initialization signal is received during a time period in which the external address signal is not received, and a second transmission gate receiving the counter initialization signal and transferring an address signal to the carry output node when said counter initialization signal is received during a time period in which the external address signal is received.

The method and apparatus described are distinguished in that the data read out and the modified data are compared with one another before the data read out are overwritten with the modified data. Only those components of the data read out which differ from the modified data are overwritten. This is an extremely simple way of preventing changes to the stored data that were made between the time of reading out the data and overwriting the data from being unintentionally reversed.

A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.

A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.

A high modulus counter is provided for receiving a counter enable (CE) signal which switches between digital states. The counter is a single load conditional look ahead counter having a carry chain isolated from a timing critical path. The counter includes one toggle flip-flop for receiving the CE signal. The flip-flop has a first output and a second output. The first output and the second output are connected to an even counter and an odd counter, respectively. Both the output of the first counter and the output of the second counter are received by each of a plurality of multiplexers which are controlled by the first output of the toggle flip-flop. In this way, the high modulus counter outputs and increments the pointer signals of the odd counter and the even counter, alternatively. The even and odd internal counters are initially set at zero and one, respectively, and each increments by two. A second flip-flop may additionally receive the external CE signal for synchronization. The outputs of the flip-flop may also be received by a pair of AND gates, the outputs of which are received by a pair of PLS generators. The two PLS generator outputs then serve as the respective CE signals for the odd and even counters.