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CROSS REFERENCE TO RELATED APPLICATION
This application is related to a commonly assigned patent application filed on Mar. 26, 1992, and entitled: "A METHOD AND APPARATUS FOR SCAN TESTING AN ARRAY IN A DATA PROCESSING SYSTEM" by Michael E. Gladden et al., Ser. No. 07/857,878.
FIELD OF THE INVENTION
This invention relates generally to a data processing system, and more particularly to performing dual scan path testing of an array in the data processing system.
BACKGROUND OF THE INVENTION
Structured arrays in data processing systems are generally tested using a scan path test methodology to provide a high level of controllability and observability during the testing operation. The scan path test methodology uses a serial shifting
path to communicate test data between the array or logic circuit being tested and a test circuit.
In structured arrays, such as programmable logic arrays, random access memory, read only memory, and other array type structures, a sense amplifier is normally used to perform a bit line sensing function for each output of the array. In a data
processing system which uses the scan path test methodology, each of the sense amplifiers provided for an array is followed by a master/slave test latch which is used to support scan path testing. Each of the master/slave test latches are coupled
together to form a shift register structure which is used only during testing operations. The shift register structure is not used during normal operation of the data processing system.
The scan path testing methodology uses a following set of steps to verify the functionality of an associated array. In a first step, an input stimulus is provided to the array and the array is enabled. In a second step, each sense amplifier is
enabled to sense the state of its corresponding output from the array. The state is subsequently stored in the associated master/slave test latch. In a third step, the master test latch shifts the output data into *the corresponding slave test latch.
The slave test latch then shifts the output data into an adjacent master test latch in the same direction in a fourth step. The last slave test latch does not shift to a master test latch, but shifts the data onto a serial data path which leads to the
test circuitry. The test circuitry may be located on or off of the integrated circuit. The third and fourth steps are repeated until all of the output data has been shifted to the test circuitry via the serial data path. The procedure is then repeated
using a different input stimulus.
The example described above is one implementation of the scan path testing methodology. Other implementations do exist in which the function of the master test latch is performed by a sense amplifier such that circuitry required to test the
integrated circuit is minimized. Such implementations of the scan path testing methodology are well known in the data processing art. Furthermore, in each implementation, test circuitry requires the use of slave test latches. Such slave test latches
still require circuit area which is used only for testing purposes.
A dual scan path testing methodology has been developed which provides a more silicon efficient approach to the scan path testing methodology. In the dual scan path testing methodology, alternate latches are allowed to overwrite the data stored
in the next adjacent latch. Thus, during a first scan test of the array outputs, the original data from the even latches is overwritten and the original data from the odd latches is scanned out via the serial data path. During a second scan test of the
array outputs, the original data from the Odd latches is overwritten and the original data from the even latches is scanned out.
The dual scan path testing methodology described herein uses a sense amplifier to perform the single required latching function. The sense amplifier serves as a master or slave latch depending on which scan pass is performed. During the first
pass, the odd outputs are scanned out with the corresponding odd sense amplifiers serving as the master portion of the shifter and the even sense amplifiers serving as the slave portion of the shifter. Conversely, during the second pass, the even
outputs are scanned out with the corresponding even sense amplifiers serving as the master portion of the shifter and the odd sense amplifiers serving as the slave portion of the shifter. By using the sense amplifiers in addition to the dual scan path
testing methodology, testing of an array in an integrated circuit may be performed using a minimal amount of both circuitry and power consumption.
The dual scan path testing methodology is typically implemented in an integrated circuit through a software program which is written and controlled externally. The software is repeated for each vector which is to be tested. While the dual scan
path testing methodology reduces the amount of circuitry required to test an array in the integrated circuit, the software overhead required to implement the dual scan path testing methodology requires a significant number of clock cycles to process the
appropriate software program.
SUMMARY OF THE INVENTION
The previously mentioned needs are fulfilled with the present invention. Accordingly, there is provided, in a first form, a data processing system. The data processing system includes a data array for providing a plurality of data outputs in
response to an input stimulus and a scan data value. A scan test circuit is connected to the data array for receiving the plurality of data outputs and for providing serial test data in response to the plurality of data outputs. The data processing
system also includes a test module for providing both the input stimulus and the scan data input to the data array. A stimulus output of the test module is connected to a stimulus input of the data array. The test module includes a first shift register
for storing the scan data value. The first shift register provides the scan data value in response to a first enable signal. The test module also includes a repetition register for storing the scan data value during a first mode of operation of the
data processing system and for storing a vector count value during a second mode of operation. The repetition register stores one of the scan data value and the vector count value in response to a second enable signal. The repetition register is
connected to the first shift register for receiving the scan data value and is connected to an external interface for receiving the vector count value. The test module also includes a control register for storing a plurality of control values. The
plurality of control values is used to determine when the data processing system is operating in one of the first and second modes of operation. The test module also includes a state machine for providing the first and second enable signals in response
to at least one of the plurality of control values. The state machine enables the test module to provide the scan data input to the data array during both a first period of time and a second period of time when the data processing system is operating in
the first mode of operation.
Similarly, there is provided, in a second form, a method of serially scanning data from an array in a data processing system. The method includes the steps of storing a shift count value in a shift count register, storing a wait value in a
distributed register, and storing a first data value in a master shift register. A first mode value is stored in a first control register. The first mode value initializes a state machine to automatically control performance of the method of serially
scanning data from the array. The first data value is stored in a repetition register in response to a first control signal provided by the state machine. The first data value is shifted from the master shift register to the array. The array in the
data processing system is enabled to execute a first scan path test operation using the first data value. A toggle value is tested to determine if the toggle value is equal to a first predetermined value. The first data value stored in the repetition
counter is transferred to the master shift register when the toggle value is equal to the first predetermined value. The array in the data processing system is enabled to execute a second scan path test operation using the first data value.
These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to note the drawings are not intended to represent the only
form of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates, in block diagram form, a data processing system in accordance with one embodiment of the present invention;
FIG. 2 illustrates, in block diagram form, array and scanning logic of FIG. 1;
FIG. 3 illustrates, in schematic diagram form, a scanning sense amplifier of FIG. 2;
FIG. 4 illustrates, in block diagram form, a test module of FIG. 1 in accordance with one embodiment of the present invention;
FIG. 5 illustrates, in partial block diagram form, a register logic circuit of FIG. 4 in accordance with one embodiment of the present invention;
FIG. 6 illustrates, in timing diagram form, time periods and waveforms used in one embodiment of the present invention;
FIG. 7 illustrates, in tabular form, the contents of scanning sense amplifiers of FIG. 2 at different time periods in accordance with one embodiment of the present invention;
FIG. 8 illustrates, in timing diagram form, time periods and waveforms used in one embodiment of the present invention;
FIG. 9 illustrates, in tabular form, the contents of scanning sense amplifiers of FIG. 2 at different time periods in accordance with one embodiment of the present invention;
FIG. 10 illustrates, in flow chart form, a flow chart of an automatic dual scan path test operation in the data processing system of FIG. 1 in accordance with one embodiment of the present invention; and
FIG. 11 illustrates, in state diagram form, a state diagram of a function executed by a state diagram of the test module of FIG. 4 during execution of the automatic dual scan path test operation in accordance with one embodiment of the present
invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
During a following description of the implementation of the invention, the terms "assert" and "negate," and various grammatical forms thereof, are used to avoid confusion when dealing with a mixture of "active high" and "active low" logic
signals. "Assert" is used to refer to the rendering of a logic signal or register bit into its active, or logically true, state. "Negate" is used to refer to the rendering of a logic signal or register bit into its inactive, or logically false state.
In order to reduce test circuitry, the present invention uses a dual scan path test scheme for scan testing an array-type structure. The dual scan path test scheme uses a shifting scheme that only requires a minimum of one latching function per
output signal.
In the new shifting scheme, alternate latches are allowed to overwrite the data stored in the next adjacent latch. Thus, during a first scan test of the array outputs, the original data from the even latches is overwritten and the original data
from the odd latches in scanned out. And during a second scan test of the array outputs, the original data from the odd latches is overwritten and the original data from the even latches in scanned out. In alternate embodiments of the present
invention, the original data from the even latches could be scanned out first. The latches are connected in a series-connected chain with the last latch providing an output signal that can be used to determine if the array has malfunctioned. By "even"
latches is meant the second, fourth, sixth, and other even numbered latches. And by "odd" latches is meant the first, third, fifth, and other odd numbered latches.
The present invention provides a data processing system which performs an automatic dual scan path test operation which does not require an external software program after initialization by a user of the data processing system. A combination of
added states in a state machine and a small amount of additional circuitry enable the data processing system to automatically perform the dual scan path test operation without requiring the user to interface with the data processing system after an
initialization process. Operation of the data processing system as well as an explanation of the initialization process will be described in more detail herein.
DESCRIPTION OF CONNECTIVITY
FIG. 1 illustrates a data processing system 10 having array and scanning logic 12, a pre-charge logic circuit 14, a scan clock generator 16, a system controller 18, a test module 20, and a JTAG circuit 22. A plurality of Test Information
integrated circuit pins 24 are connected to JTAG circuit 22. JTAG circuit 22 is bidirectionally coupled to test module 20 via a JTAG Information bus 26. Test module 20 is coupled to array and scanning logic 12 and scan clock generator 16 via a Scan
Interface bus 34. Test module 20 is coupled to system controller 18 via a System Data bus 38 and a System Control bus 40. System controller 18 receives data via a plurality of External Data integrated circuit pins 28. Similarly, system controller 18
receives address and control information via a plurality of External Address integrated circuit pins 30 and a plurality of External Control integrated circuit pins 32, respectively. System controller 18 is coupled to array and scanning logic 12 via an
Internal Data bus 36. Additionally, system controller 18 is coupled to pre-charge logic circuit 14 via a Pre-Charge Enable signal. An output of pre-charge logic circuit 14 is coupled to array and scanning logic 12 to provide a Pre-charge signal
thereto. Scan clock generator 16 receives a Master Clock signal from an external source. The Master Clock signal is typically provided via a dedicated integrated circuit pin, but may also be provided by an chip integrated within the data processing
system. Scan clock generator 16 provides a Scan Clock 1 signal and a Scan Clock 2 signal to array and scanning logic 12.
FIG. 2 illustrates array and scanning logic 12 in more detail. Array and scanning logic 12 generally includes an array 50 and a plurality of scanning sense amplifiers, 52a through 52h. Array 50 receives Scan Enable and Scan Data Input as input
signals. Array 50 generates one Sense Amplifier Input signal for each scanning sense amplifier (52a-52h). Each scanning sense amplifier (52a-52h) also receives the Pre-charge signal as an input. Scanning sense amplifiers 52b, 52d, 52f, and 52h each
receives Scan Clock 1 as a Scan Clock input signal. Scanning sense amplifiers 52a, 52c, 52e, and 52g each receive Scan Clock 2 as a Scan Clock input signal. Each scanning sense amplifier (52a-52h) generates a signal which is output from the array and
scanning logic 12 as Normal Data Output.
Scanning sense amplifier 52a can receive an input signal labeled In from another scanning sense amplifier (not shown) or from another circuit (not shown). In the illustrated embodiment, the In input to scanning sense amplifier 52a is simply
connected to ground. Scanning sense amplifier 52a generates an output signal Out, which is received by scanning sense amplifier 52b as an input signal labeled In. Scanning sense amplifier 52b generates an output signal Out, which is received by scanning
sense amplifier 52c as an input signal labeled In. Scanning sense amplifier 52c generates an output signal Out, which is received by scanning sense amplifier 52d as an input signal labeled In.
Likewise, scanning sense amplifier 52d generates an output signal Out, which is received by scanning sense amplifier 52e as an input signal labeled In. Scanning sense amplifier 52e generates an output signal Out, which is received by scanning
sense amplifier 52f as an input signal labeled In. Scanning sense amplifier 52f generates an output signal Out, which is received by scanning sense amplifier 52g as an input signal labeled In. Scanning sense amplifier 52g generates an output signal Out,
which is received by scanning sense amplifier 52h as an input signal labeled In. Finally, scanning sense amplifier 52h generates an output signal Out, which is transferred outside of the array and scanning logic 12 as Scan Data Output.
FIG. 3 illustrates a circuit implementation of one scanning sense amplifier 52x, which could be used as any of the scanning sense amplifiers (52a-52h) of FIG. 2. In is an input signal to a CMOS transmission gate 60. Scan Clock is a control
input to the n-channel portion of CMOS transmission gate 60. Scan Clock is an input to inverter 58. The output of inverter 58, Scan Clock, is a control input to the p-channel portion of CMOS transmission gate 60. The output of CMOS transmission gate
60 is coupled to node 54. A p-channel MOS transistor 56 has a first current electrode connected to a positive power supply voltage, a second current electrode connected to node 54, and a control electrode connected to the Pre-charge signal. Node 54 is
connected to the Sense Amplifier Input signal and to an input of an inverter 62.
Still referring to FIG. 3, a p-channel MOS transistor 70 has a first current electrode connected to a positive power supply voltage, a second current electrode connected to node 54, and a control electrode connected to a node 64. An output of
inverter 62 is also coupled to node 64. An n-channel MOS transistor 68 has a first current electrode connected to ground, a second current electrode connected to node 54, and a control electrode connected to node 64. An input of an inverter 66 is
connected to node 64, and an output of inverter 66 is connected to output signal Out. The output signal Normal Data Output is connected to node 64. Transistors 70 and 68 form an inverter which has an input connected to node 64 and an output connected
to the input of inverter 62. Inverter 66 is used to invert and buffer the output signal from inverter 62.
Scanning sense amplifier 52x can perform three functions, namely, the function of a sense amplifier, a master test latch for scan testing, and a slave test latch for scan testing. Scanning sense amplifier 52x can only perform one of these
functions at a time. Node 54 is the input node to the scanning sense amplifier 52x. Node 54 can do only one of the following at a time: (1) be precharged using transistor 56; (2) receive an input value from array 50 across the Sense Amplifier Input
signal; or (3) receive an input value across the In input signal.
Node 54 is precharged high to the voltage of the positive power supply prior to the assertion of the Scan Enable signal. When Scan Enable is asserted, Sense Amplifier Input either leaves node 54 high, or pulls node 54 low to ground. The In
input signal is only used during scan testing. When the In input signal is being used, the precharging of node 54 is disabled and the Sense Amplifier Input signal is disabled. When Scan Clock is a binary zero value, the output of transmission gate 60
is tri-stated (i.e. the output of transmission gate 60 is not being driven, but is high impedance).
The feedback path connecting the output of inverter 62 to the inputs of transistors 70 and 68 allows scanning sense amplifier 52x to operate down to a minimum operating frequency of zero Hertz. Alternate embodiments of the present invention
could use a dynamic design instead of a static design. A dynamic design of scanning sense amplifier 52x would rely on charge stored on nodes and would require that the operating frequency not drop below a minimum frequency.
FIG. 4 illustrates one embodiment of test module 20. Test module 20 generally comprises a register logic circuit 80, a state machine 82, a scan bus interface 84, a JTAG interface 86, and a system interface 88. JTAG Information bus 26 is coupled
to JTAG interface 86 to provide a JTAG Data Input signal, a JTAG Reset signal, and a JTAG Clock signal. JTAG Information bus 26 is also coupled to JTAG interface 86 to receive a JTAG Data Output signal. JTAG interface 86 is coupled to register logic
circuit 80 to provide a JTAG Write signal, a JTAG Read signal, and a JTAG Data bus for transferring data. JTAG interface 86 is coupled to each of register logic 80 and state machine 82 to provide a plurality of JTAG Register Select signals.
System Control bus 40 is coupled to system interface 88 to provide a plurality of control signals. System Control bus 40 is also coupled to state machine 82 to provide an Idle Ready signal. System interface 88 is coupled to register logic
circuit 80 to provide a plurality of Register Select signals 78, a Write signal, a Read signal, and a plurality of Byte Enable signals.
Register logic circuit 80 is coupled to System Control bus 40 to provide an Idle Request signal. Additionally, register logic circuit 80 bidirectionally communicates the plurality of System Data signals 38. Register logic circuit 80 is coupled
to state machine 82 to provide a plurality of state data values via a State Data bus 74. As well, state machine 82 provides a plurality of State Control signals to register logic circuit 80. Register logic circuit 80 provides a plurality of register
control signals to scan bus interface 84 via a Register Control bus 76. Additionally, register logic circuit 80 provides a Scanned Data signal to scan bus interface 84 and receives a Generate Scan Data signal from scan bus interface 84.
Scan bus interface 84 is coupled to state machine 82 to receive a plurality of Scan Control signals. Scan bus interface 84 is also coupled to Scan Interface bus 34 to provide an Enable Test Mode signal, a Hold signal, a Scan Enable signal, an
Activate Circuit signal, a Test Register signal, and a Scan Data Output signal. Scan Interface bus 34 also transfers a Scan Data Input signal to scan bus interface 84.
FIG. 5 illustrates register logic circuit 80 of the data processing system. Register logic circuit 80 generally includes a reps counter 90, a master shift register A 92, a master shift register B 94, a shift counter A 96, a shift counter B 98, a
control register 1 100, a control register 2 102, and a distributed register 104. Register Select bus 78 provides a RSEL [2] signal to reps counter 90, shift counter A 96, and shift counter B 98. Register Select bus 78 provides a RSEL[1] signal to
master shift register A 92 and Master shift register B 94. Additionally, Register Select bus 78 provides a RSEL[3] signal to control register 1 100 and control register 2 102. As well, Register Select bus 78 provides a RSEL[4] signal to distributed
register 104. System Data bus 38 provides data to each of reps counter 90, master shift register A 92, master shift register B 94, shift counter A 96, shift counter B 98, control register 1 100, control register 2 102, and distributed register 104.
Reps counter 90 provides a TMREGOUT (test mode register output) signal to Register Control bus 76. Register Control bus 76 provides a TMBUSY (test mode busy) signal to control register 1 100 and a TREPS (test mode repetitions) signal to control
register 2 102. Register Control bus 76 also provides a TWAIT (test mode wait) signal, TMHOLD (test mode hold) signal, and a TMHOLD Enable (test mode hold enable) signal to control register 2 102.
Master shift register A 92 provides the Scanned Data signal to scan bus interface 84 (of FIG. 4). The plurality of State Control signals provide a Scan Enable A signal to master shift register A 92 and a Scan Enable B signal to master shift
register B 94. Control register 1 100 provides the Idle Request signal to System Control bus 40 (of FIG. 4). The Generate Scan Data is provided to distributed register 104. The Read signal provided by system interface 88 is provided to each of reps
counter 90, master shift register A 92, master shift register B 94, shift counter A 96, shift counter B 98, control register 1 100, control register 2 102, and distributed register 104. Similarly, the Write signal provided by system interface 88 is
provided to each of reps counter 90, master shift register A 92, master shift register B 94, shift counter A 96, shift counter B 98, control register 1 100, control register 2 102, and distributed register 104. The plurality of Byte Enable signals
provide a BE[0,1] signal to distributed register 104 and a BE[2,3] signal to control register 2 102. The BE[0,1] signal is also provided to control register 1 100 and master shift register A 92. The BE[2,3] signal is also provided to reps counter 90
and master shift register B 94. The plurality of Byte Enables signals also provides a BE[1] signal to shift counter B 98 and a BE[0] signal to shift counter A 96.
The plurality of JTAG Register Select signals provides a JSEL[3] signal to reps counter 90 and a JSEL [0] signal to master shift register A 92. The plurality of JTAG Register Select signals provides a JSEL[1] signal to master shift register B
94. A JSEL[2] signal is provided to both shift counter A 96 and shift counter B 98. The plurality of JTAG Register Select signals provides a JSEL[4] signal and a JSEL[5] signal to control register 1 100 and control register 2 102, respectively. A
JSEL[6] signal is provided to distributed register 104 via the plurality of JTAG Register Select signals.
The JTAG Write signal is provided to each of reps counter 90, master shift register A 92, master shift register B 94, shift counter A 96, shift counter B 98, control register 1 100, control register 2 102, and distributed register 104. The JTAG
Read signal is also provided to each of reps counter 90, master shift register A 92, master shift register B 94, shift counter A 96, shift counter B 98, control register 1 100, control register 2 102, and distributed register 104. The JTAG Data bus
provides data to each of reps counter 90, master shift register A 92, master shift register B 94, shift counter A 96, shift counter B 98, control register 1 100, control register 2 102, and distributed register 104.
State Data bus 74 is coupled to both shift counter A 96 to receive a Zero A signal and shift counter B 98 to receive a Zero B signal. Control register 1 100 is coupled to State Data bus 74 to provide a plurality of Control 1 signals. Similarly,
control register 2 102 is coupled to State Data bus 74 to provide a plurality of Control 2 signals. Master shift register B is also coupled to distributed register 104 to provide a MSRB.sub.-- FB signal and to receive a DREGBIN signal. Similarly,
master shifter register A is coupled to distributed register 104 to provide a MSRA.sub.-- FB signal and to receive a DREGAIN signal.
GENERAL DESCRIPTION OF OPERATION
The present invention implements state machine 82 and register logic 80 such that no external control or data is required during execution of the dual scan path test operation. Prior to execution of the dual scan path test operation, a user of
data processing system 10 initializes a system with a plurality of values which will be used during execution of the dual scan path test operation. Each of the plurality of values will subsequently be discussed in more detail. After initialization,
data processing system 10 executes the dual scan path test operation automatically and requires no additional information from the user of data processing system.
As part of the present implementation of the dual scan path test operation, the present invention requires that the same Scan Data Input signals be used during each iteration of the dual scan path test methodology. The Scan Data Input signals
are stored in master shift register A 92 during a first iteration of the dual scan path test. A copy of the Scan Data Input signals is stored in reps counter 90. During a second iteration of the dual scan path test, the contents of reps counter 90 are
automatically transferred to master shift register A 92. The same Scan Data Input signals are, therefore, used during both the first and second iterations of the dual scan path test. Control of data processing system 10 during the dual scan path
testing operation is provided by state machine 82 of test module 20 such that the same Scan Data Input signals are used during the first and second iterations of the dual scan path test methodology without requiring user intervention.
Before a more detailed explanation of the operation of data processing system 10, execution of the dual scan path testing operation will be briefly explained. During execution of the dual scan path testing operation, the first application of the
Scan Data Input signals results in the events that occur during time periods 1 through 10 as illustrated in FIG. 6 and FIG. 7. The second application of the same Scan Data Input signals results in the events that occur during time periods 11 through 20
as illustrated in FIG. 8 and FIG. 9.
FIG. 6 illustrates a timing diagram of several time periods and waveforms used in one embodiment of the present invention. The time periods are labeled 1 through 10. The Master Clock and Scan Enable signals are the signals used to generate Scan
Clock 1 and Scan Clock 2. In the present embodiment, the Scan Enable signal is used to indicate that the data processing system 10 is in a test mode and that the scan testing of array 50 is currently being performed.
The letters contained within each of the Scan Data Output bits represent the location of the scanning sense amplifier 52x which was the origin of that particular Scan Data Output bit. The original content of each scanning sense amplifier 52x is
the Sense Amplifier Input value received from the array 50. The original content of each scanning sense amplifier 52x is represented by the letter "x". For example, the original content of scanning sense amplifier 52a is represented by the letter "a".
And the original content of scanning sense amplifier 52h is represented by the letter "h". In the present embodiment, the contents "x" of each scanning sense amplifier 52x is a single binary bit of information, either a binary zero or a binary one.
FIG. 7 is a table illustrating the value of both the Scan Data Output signal and the contents of the eight scanning sense amplifiers (52a-52h) of FIG. 2 at the time periods 1 through 10 shown in FIG. 6. The first column, labeled "Time Period",
corresponds to the time periods I through 10 illustrated in FIG. 6. The second column, labeled "Contents of the Scanning Sense Amps (SSA)", illustrates how the contents of the eight scanning sense amplifiers (52a-52h) change during the different time
periods. And the third column, labeled "Scan Data Output", corresponds to the value of the Scan Data Output signal that is shifted out of scanning sense amplifier 52h during the different time periods.
FIG. 8 illustrates a timing diagram of several time periods and waveforms used in one embodiment of the present invention. The time periods are labeled 11 through 20. The Master Clock and Scan Enable signals are used to generate Scan Clock 1
and Scan Clock 2. In the present embodiment, the Scan Enable signal is used to indicate that the data processing system 10 is in a test mode and that the scan testing of array 50 is currently being performed.
FIG. 9 is a table illustrating the value of both the Scan Data Output signal and the contents of the eight scanning sense amplifiers (52a-52h) of FIG. 2 at the time periods 11 through 20 shown in FIG. 6. The first column, labeled "Time Period",
corresponds to the time periods 11 through 20 illustrated in FIG. 6. The second column, labeled "Contents of the Scanning Sense Amps (SSA)", illustrates how the contents of the eight scanning sense amplifiers (52a-52h) change during the different time
periods. And the third column, labeled "Scan Data Output", corresponds to the value of the Scan Data Output signal that is shifted out of scanning sense amplifier 52h during the different time periods.
The dual scan path testing operation of the present invention will now be briefly described. The purpose of testing an array is to ensure that the array produces the correct outputs for a given set of inputs. Array 50 is tested by applying
various stimuli to the array 50 by way of the Scan Data Input signals, and by enabling the array using the Scan Enable signal. The array 50 then produces output signals that are received by the scanning sense amplifiers (52a-52h) across the Sense
Amplifier Input signals. The information stored in the scanning sense amplifiers (52a-52h) is serially transmitted across the Scan Data Output signal during testing, while requiring a minimum of circuitry.
In order for the array 50 to be properly tested, the original contents of each of the scanning sense amplifiers (52a-52h) must be scanned out using the Scan Data Output signal. In order to scan out the original contents of each of the scanning
sense amplifiers (52a-52h), the present invention requires that the same Scan Data Input signals be applied to array 50 twice. The first application of the stimulus results in the events that occur during time periods I through 10 as illustrated in FIG.
6 and FIG. 7. During time periods 1 through 10, the Scan Data Output signal scans out the original contents of scanning sense amplifiers 52h, 52g, 52e, 52c, and 52a.
The second application of the same stimulus results in the events that occur during time periods 11 through 20 as illustrated in FIG. 8 and FIG. 9. During time periods 11 through 20 | | |
