Method and circuitry for clock synchronization

What is claimed is:

1. A method of performing phase adjustment in a phase locked loop to generate a first output phase signal from a multiplicity of input phase signals, comprising the steps of:

a) selecting a first phase signal and a second phase signal from the multiplicity of input phase signals in response to a select signal;

b) generating a weighting signal in response to a control signal, wherein the control signal causes the weighting signal to control interpolation between the first and second phase signals when the select signal is changing states, wherein the select signal is generated in response to the control signal; and

c) interpolating between the first phase signal and the second phase signal to generate the first output phase signal in response to the weighting signal.

2. The method of claim 1, further comprising the step of:

a) generating the multiplicity of input phase signals from a clock signal having a frequency F, each of the multiplicity of input phase signals having the frequency F.

3. The method of claim 2 further comprising the step of:

a) generating the select signal from the control signal.

4. The method of claim 1 further comprising the steps of:

a) selecting a third phase signal and a fourth phase signal from the multiplicity of input phase signals in response to the select signal; and

b) interpolating between the third phase signal and the fourth phase signal to generate a second output phase signal in response to the weighting signal, the second output phase signal leading the first output phase signal by substantially 90.degree..

5. A method of performing phase adjustment in a phase locked loop to generate a first output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, comprising the steps of:

a) selecting a first even phase signal from the multiplicity of even phase signals in response to an even select signal;

b) selecting a first odd phase signal from the multiplicity of odd phase signals in response to an odd select signal, wherein each of the even and odd select signals is generated in response to a control signal;

c) generating an even weighting signal and an odd weighting signal in response to the control signal, wherein the control signal causes the even and odd weighting signals to control interpolation between the first even and first odd phase signals when one of the first even and odd select signals is changing states; and

d) interpolating between the first even phase signal and the first odd phase signal to generate the first output phase signal in response to the even weighting signal and the odd weighting signal, the even weighting signal preventing the first even phase signal from contributing to the first output phase signal when the even select signal is changing states, and the odd weighting signal preventing the first odd phase signal from contributing to the first output phase signal when the odd select signal is changing states.

6. The method of claim 5 further comprising the steps of:

a) selecting a second even phase signal from the multiplicity of even phase signals in response to the even select signal;

b) selecting a second odd phase signal from the multiplicity of odd phase signals in response to the odd select signal; and

c) interpolating between the second even phase signal and the second odd phase signal to generate a second output phase signal in response to the even weighting signal and the odd weighting signal, the second output phase signal leading the first output phase signal by substantially 90.degree., the even weighting signal preventing the second even phase signal from contributing to the second output phase signal when the even select signal is changing states, and the odd weighting signal preventing the second odd phase signal from contributing to the second output phase signal when the odd select signal is changing states.

7. The method of claim 5 further comprising the step of:

a) generating the multiplicity of even phase signals and the multiplicity of odd phase signals in response to an input signal having a frequency F, the multiplicity of even phase signals and multiplicity of the odd phase signals having the frequency F.

8. The method of claim 5 further comprising the steps of:

a) generating a shift left signal and a shift right signal in response to the control signal;

b) generating the even select signal in response to the shift left signal and the shift right signal; and

c) generating the odd select signal in response to the shift left signal and the shift right signal.

9. Phase tuning circuitry for generating an output phase signal from a multiplicity of input phase signals, comprising:

a) a select circuit for generating a select signal in response to a control signal;

b) a weighting circuit for generating a weighting signal in response to the control signal;

c) a phase selector for selecting a first phase signal and a second phase signal from the multiplicity of input phase signals in response to the select signal; and

d) a phase interpolator for interpolating between the first phase signal and the second phase signal to generate the output phase signal in response to the weighting signal, wherein the weighting signal is used to control interpolation between the first and second phase signals when the select signal is changing states, wherein the select signal and the weighting signal are generated in response to the control signal.

10. The phase tuning circuitry of claim 9 wherein the phase selector further comprises:

a) a barrel shifter generating the select signal in response to the control signal.

11. The phase tuning circuitry of claim 10 wherein the phase selector further comprises:

a) a first multiplexing circuit for selecting the first phase signal from the multiplicity of input phase signals in response to the select signal; and

b) a second multiplexing circuit for selecting the second phase signal from the multiplicity of input phase signals in response to the select signal.

12. The phase tuning circuitry of claim 9 wherein the phase interpolator comprises:

a) a first differential amplifier coupled to the first phase signal and the weighting signal, the first differential amplifier having a first output coupled to the output phase signal; and

b) a second differential amplifier coupled to the second phase signal and the weighting signal, the second differential amplifier having a second output coupled to the first output.

13. Phase tuning circuitry for generating an output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, the phase tuning circuitry comprising:

a) a select signal generator for generating an even select signal and an odd select signal in response to a control signal;

b) a weighting signal generator for generating an even weighting signal and an odd weighting signal in response to the control signal;

c) a phase selector for selecting an even phase signal from the multiplicity of even phase signals in response to an even select signal and for selecting an odd phase signal from the multiplicity of odd phase signals in response to an odd select signal; and

d) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal in response to the even weighting signal and the odd weighting signal, wherein the control signal causes the even and odd weighting signals to control interpolation between the even and odd phase signals when one of the even and odd select signals is changing states, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, and the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states.

14. The phase tuning circuitry of claim 13 further comprising:

a) control circuitry responsive to the control signal for generating the even select signal, the odd select signal, the even weighting signal and the odd weighting signal.

15. The phase tuning circuitry of claim 14 wherein the phase selector comprises:

a) a first barrel shifter generating the even select signal in response to the control signal; and

b) a second barrel shifter generating the odd select signal in response to the control signal.

16. The phase tuning circuitry of claim 15 wherein the phase selector further comprises:

a) a first multiplexing means for selecting the even phase signal from the multiplicity of even phase signals in response to the even select signal; and

b) a second multiplexing means for selecting the odd phase signal from the multiplicity of odd phase signals in response to the odd select signal.

17. The phase tuning circuitry of claim 16 wherein the phase interpolator comprises:

a) a first differential amplifier coupled to the even phase signal and the even weighting signal, the first differential amplifier having a first output; and

b) a second differential amplifier coupled to the odd phase signal and the odd weighting signal, the second differential amplifier having a second output coupled to the first output.

18. The phase tuning circuitry of claim 13 further comprising:

a) a phase locked loop for generating the multiplicity of even phase signals and the multiplicity of odd phase signals.

19. The phase tuning circuitry of claim 13, wherein the phase tuning circuitry is coupled to a data input circuit, the data input circuit receiving a data input signal from which the data input circuit generates the multiplicity of even phase signals and the multiplicity of odd phase signals, the data input signal having a delay, wherein the phase tuning circuitry further comprises:

a) circuitry for compensating for the delay associated with the data input circuit.

20. The phase tuning circuitry of claim 13, wherein the output phase signal is coupled to an output buffer having a delay, and wherein the phase tuning circuitry further comprises:

a) circuitry for compensating for the delay associated with the output buffer.

21. Phase tuning circuitry for generating an output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, the phase tuning circuitry having fast power up and power down response characteristics, the phase tuning circuitry comprising:

a) a select signal generator for generating an even select signal and an odd select signal in response to a control signal;

b) a weighting signal generator for generating an even weighting signal and an odd weighting signal in response to the control signal;

c) a phase selector for selecting an even phase signal from the multiplicity of even phase signals in response to the even select signal and for selecting an odd phase signal from the multiplicity of odd phase signals in response to the odd select signal; and

d) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal in response to the even weighting signal and the odd weighting signal wherein the control signal causes the even and odd weighting signals to control interpolation between the even and odd phase signals when one of the even and odd select signals is changing states, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, and the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states.

22. Phase tuning circuitry for generating an output phase signal, comprising:

a) an accumulator for generating an underflow/overflow signal and a count signal in response to a control signal;

b) a digital to analog converter for generating an even weighting signal and an odd weighting signal in response to the count signal;

c) control circuitry for generating a barrel shift control signal in response to the underflow/overflow signal;

d) a first barrel shifter generating a multiplicity of even select signals in response to the barrel shift control signal; and

e) a second barrel shifter generating a multiplicity of odd select signals in response to the barrel shift control signal;

f) a phase selector comprising:

i) a first multiplexing means for selecting an even phase signal from a multiplicity of even phase signals in response to the multiplicity of even select signals;

ii) a second multiplexing means for selecting an odd phase signal from a multiplicity of odd phase signals in response to the multiplicity of odd select signals; and

g) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal, the phase interpolator comprising:

i) a first differential amplifier coupled to the even phase signal and the even weighting signal, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, the first differential amplifier having a first output; and

ii) a second differential amplifier coupled to the odd phase signal and the odd weighting signal, the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states, the second differential amplifier having a second output coupled to the first output.

23. The circuitry of claim 22 further comprising:

a) a voltage controlled oscillator receiving an input signal and generating the multiplicity of even phase signals and the multiplicity of odd phase signals.

24. The circuitry of claim 22 further comprising:

a) a phase locked loop for receiving the input signal and generating the multiplicity of even phase signals and the multiplicity of odd phase signals.

Description Submit all comments and votes

FIELD OF INVENTION

The present invention relates to clock synchronization circuitry including a cascaded phase locked loop. In particular the present invention relates to a delay stage for a ring oscillator and a fine phase tuning circuitry, both used in the cascaded phase locked loop.

BACKGROUND OF THE INVENTION

Clock synchronization in integrated circuits is typically performed by a phase locked loop (PLL).

Some prior PLLs use a ring oscillator as a voltage controlled oscillator. A ring oscillator is a chain of inversion elements coupled together in a negative feedback fashion, with each element contributing a delay amount which adds up to half an oscillation period. Some prior phase locked loop implementations using ring oscillators suffer phase offset and deadband problems, which are difficult to minimize without compromising one or the other.

One disadvantage of prior ring oscillators is that the number of phase signals that can be generated are limited by the number of inversion elements contained in the ring oscillator. The number of inversion elements is, in turn, limited by the length of time delay contributed by each inversion element. The greater the time delay of the inversion element, the fewer the number of inversion elements that can be included in the ring oscillator.

Another disadvantage of some prior oscillators is that they must include an odd number of inversion elements to develop a phase shift of greater than 180.degree..

Other prior PLLs use voltage controlled delay line to generate the phase shift necessary for oscillation. Such prior PLLs have a limited delay range, typically a clock period or less. Hence, the frequency of operation of such prior PLLs is very limited. Prior PLLs including delay lines also tend to be susceptible to supply noise because of their use of CMOS inverters, which couple supply noise directly into output signals.

SUMMARY AND OBJECTS OF THE INVENTION

One object of the present invention is to provide a method and circuitry for synchronizing internal device functions to an external clock.

Another object of the present invention is to provide a method and circuitry for clock synchronization that allows phase deadband characteristics to be easily optimized.

Another object of the present invention is to provide a method and circuitry for clock synchronization that allows easy optimization of stability characteristics.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes the affect of the delay of clock buffers.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes the affect of a clock distribution network on loop stability.

A still further object of the present invention is to provide a method and circuitry for clock synchronization that allows easy optimization of loop bandwidth.

A further object of the present invention is to provide a method and circuitry for clock synchronization that provides high rejection of power supply noise.

Another object of the present invention is to provide a method and circuitry for fine phase adjustment with small static phase error and high loop stability.

Another object of the present invention is to provide a method and circuitry for phase adjustment in which there are no boundary conditions or start up conditions to be concerned with.

Another object of the present invention is to provide a method and circuitry for clock synchronization that provides smooth phase adjustment.

Another object of the present invention is to provide a method and circuitry for clock synchronization that is suitable for a wide range of frequencies.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes restart response time after power down.

Another object of the present invention is to provide a method and circuitry for clock synchronization that compensates for the delays associated with data input circuitry and data output circuitry.

A still further object of the present invention is to provide a method and circuitry for clock synchronization that generates an output signal with an controlled phase offset with respect to the input reference signal.

A method of performing phase adjustment in a phase locked loop is described. First, two phase signals are selected from a multiplicity of phase signals. The two selected phase signals are selected by a select signal. Next, an output signal is generated by interpolating between the two selected phase signals. The contribution of each of the two selected phase signals to the output signal is determined by a weighting signal.

Also described is phase tuning circuitry, which includes a phase selector and a phase interpolator. The phase selector selects two phase signals from a multiplicity of phase signals in response to a select signal. The two selected phase signals are coupled to the phase interpolator. The phase interpolator generates an output signal by interpolating between the two selected phase signals. The relative contribution of each of the two selected phase signals to the output signal is determined by a weighting signal.

Also described is a delay stage for a ring oscillator. The ring oscillator includes an even number of cascaded delay stages. Each delay stage includes a differential amplifier, which generates two complementary output signals. Coupled between the complementary output signals, two voltage clamping means limit the peak-to-peak voltage swing of the output signal. Limiting the peak-to-peak voltage swing of the output signal speeds-up the delay stage and allows the ring oscillator to include a greater number of delay stages.

Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which:

FIG. 1 is a block diagram of a high speed computer bus.

FIG. 2 is a block diagram of a phase locked loop.

FIG. 3 is a block diagram of the VCO.

FIG. 4 is a diagram of the relationship between the external reference signal and the phase signals output by the VCO.

FIG. 5 is a schematic diagram of a delay stage of the VCO.

FIG. 6 is an illustration of the phase adjustment levels of the phase selection circuitry and the phase interpolator.

FIG. 7 is a detailed block diagram of the receive subloop within the phase locked loop.

FIG. 8 is a schematic diagram of the coarse select control circuit.

FIG. 9 is a block diagram of the even multiplexer and the odd multiplexer.

FIG. 10 is a schematic diagram of a multiplexer select stage.

FIG. 11 is a schematic diagram of the phase interpolator.

FIG. 12 is a timing diagram for a subloop of the phase locked loop.

FIG. 13 is a detailed block diagram of the transmit subloop within the phase locked loop.

FIG. 14 is a block diagram of the out-of-phase even multiplexer and the out-of-phase odd multiplexer.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a high speed digital computer bus system 20. Devices 30 and 32 use clock synchronization circuitry 36 to synchronize the transfer of data between data bus 38. Clock synchronization circuitry 36 is a cascaded phase locked loop (PLL) 36. The main loop of PLL 36 utilizes a ring voltage controlled oscillator (VCO), which includes an even number of cascaded delay stages of the present invention. Two subloops coupled to the main loop perform fine phase tuning according to the method and circuitry of the present invention to generate two internal clock signals.

As will be described in more detail below, each delay stage of the present invention generates two complementary output signals using a differential amplifier. Coupled between the two complementary output signals, two clamping devices limit the peak-to-peak voltage swing of the complementary output signals. When the delay stages are cascaded together, they provide twelve different phase signals that are used by the subloops.

The method and circuitry for fine phase adjustment used in the subloops also will be described in detail below. Briefly described, the phase tuning circuitry of the present invention includes a phase selector and a phase interpolator. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO of the main loop. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The effect of the even phase signal and the odd phase signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. The weighting signals allow even phase signals and odd phase signals to switch without introducing jitter onto the output signal.

The high speed digital computer bus system 20 of FIG. 1 includes master device 30, slave devices 32, only one of which is shown, and data bus 38. Data bus 38 transfers data between devices 30 and 32 at data rates up to 500 MBytes per second, in the preferred embodiment.

Master device 30 is an intelligent device, such as a microprocessor, an application specific integrated circuit (ASIC), a memory controller, or a graphics engine. Master 30 differs from slave device 32 in that master device 30 initiates data requests, such as requests to read or write slave devices 32.

Slave devices 32 do not include as much intelligence as master device 30 and can only respond to data requests. Slave devices 32 may be dynamic random access memories (DRAMs), static random access memories (SRAMs), read only memories (ROMs), electrically programmable read only memories (EPROMs), or flash memories.

Master device 30 and slave devices 32 transfer data synchronously. That is, data transfers are referenced to the clock edges of clock signals CLOCKFROMMASTER 42 and CLOCKTOMASTER 44. Both clock signals 42 and 44 are generated by clock source 46. Both clock signals 42 and 44 are carded by a single clockline, which turns around near master device 30. From there, the clockline extends back toward clock source 46, where it is terminated. As a result, both CLOCKFROMMASTER 42 and CLOCKTOMASTER 44 run at the same frequency. The phase shift between clock signals 42 and 44 varies depending upon the location of devices 30 and 32 relative to the turnaround in the clockline. The phase difference between clock signals 42 and 44 is approximately 0.degree. near the turnaround and increases as distance from the turnaround increases.

Slave devices 32 transmit data with the edges of CLOCKTOMASTER 44 and receive data with CLOCKFROMMASTER 42. Analogously, master device 30 transmits data with the edges of CLOCKFROMMASTER 42 and receives data with CLOCKTOMASTER 44. Clock and data signals remain synchronized as they propagate toward their destination because clock lines 42 and 44 and data bus 38 are matched for delay.

Devices 30 and 32 interface with data bus 38 and clock signals 42 and 44 using interface 34. Interface 34 performs a number of tasks. Among those tasks, interface 34 converts the low voltage levels of data bus 38 to ordinary CMOS levels. Interface 34 also generates internal clocks for receiving and transmitting data. Interface 34 uses clock synchronization circuitry 36 to perform voltage level conversion and clock synchronization.

FIG. 2 illustrates in block diagram form clock synchronization circuitry 36 that is the heart of interface 34. Phase locked loop 36 synchronizes the reception of data to the device's external receive clock, CLOCKTOMASTER 44 or CLOCKFROMMASTER 42, as the case may be. Similarly, phase locked loop 36 synchronizes the transmission of data with the device's external transmit clock, CLOCKTOMASTER 44 or CLOCKFROMMASTER 42, as the case may be.

Phase locked loop 36 performs both synchronization tasks using a cascaded design, which includes main loop 52 and two subloops, a receive subloop 54 and a transmit subloop 56. Main loop 52 acquires and tracks frequency, outputting 12 phase signals, PH(11:0) 58, all with the same frequency, to subloops 54 and 56. Subloops 54 and 56 perform fine phase tracking of clock signals 42 and 44 by selecting two phase signals from PH(11:0) 58. The two selected phase signals are interpolated to generate internal receive and transmit clock signals, INTRCLK 60, INTTCLK 62, and LEADING INTTCLK 63. INTRCLK 60 is in-phase with external receive clock 42. INTTCLK 62 is also in phase with its external reference clock signal, TCLK.sub.S 44. In contrast, LEADING INTTCLK 63 leads TCLK.sub.S 44 by 90.degree. in a preferred embodiment.

Main loop 52 uses a conventional second order architecture to track and acquire signal frequencies ranging from 50 MHz to 250 MHz. Main loop 52 has a short pull in time of less than 10 usec. The amount of static phase error generated by main loop 52 has no affect upon the phase tracking accuracy of PLL 36 because subloops 54 and 56 perform phase acquisition. Thus, static phase error in main loop 52 may be, and is, traded for reduced deadband and improved stability characteristics. In contrast, the jitter of phase signals PH(11:0) 58 is minimized because it directly affects the jitter within subloops 54 and 56.

Optimization of the stability of phase signals PH(11:0) 58 is further aided by the cascaded design of PLL 36. Clock distribution and buffering is performed by subloops 54 and 56, rather than main loop 52. Thus, main loop stability is unaffected by buffer and clock distribution delay. Consequently, main loop bandwidth may be easily optimized and the size of filter 82 reduced. This is particularly important in embodiments in which filter 84 and all of PLL 36 is fabricated on a single die.

Main loop 52 includes amplifiers 74 and 76, counters 78, frequency-phase detector (FPD) 80, charge pump 82, filter 84, and voltage controlled oscillator (VCO) 86.

Amplifier 74 amplifies RCLK.sub.S to a voltage swing of 0 volts to 5 volts, as required by FPD 80. Amplifier 76 similarly amplifies PH0 90 to a voltage swing of 0 volts to 5 volts. The gain of amplifiers 74 and 76 necessarily differ because the voltage swings of RCLK.sub.S and PH0 90 differ. This difference in amplification prior to frequency and phase detection by FPD 80 introduces static phase error into main loop 52. The static phase error so introduced is tolerable because it does not affect the phase tuning of subloops 54 and 56.

Prefered implementations of phase locked loop 36 include counters 78 to increase the frequency range of PLL 36. Counters 78 divide the frequency of their inputs by two, prior to coupling their outputs to FPD 80. Counters 78 thus enhance the frequency response of FPD 80 by expanding the range of frequencies that FPD 80 can accommodate.

FPD 80 is a sequential frequency detector, selected for its large tracking range and short pull-in time.

Charge pump 82 converts the output of FPD 80 into current pulses. Charge pump 82 eliminates deadband with its high input sensitivity. Charge pump 82 introduces static phase error because its mechanisms for switching from a high-to-low output and from a low-to-high output are not symmetrical. This static phase error is tolerable because main loop 52 does not perform phase tuning. Thus, charge pump 82 may, and does, differ from prior charge pumps because within main loop 52 dead band characteristics may be reduced without concern for static phase error.

Filter 84 converts the current pulses into the analog control voltage 85 coupled to VCO 86 using a standard one-pole, one zero, passive filter.

VCO 86 is a six delay stage ring oscillator. Each delay stage generates two of the twelve phase signals, PH(11:0) 58. The differential design of the VCO stage provides high power-supply rejection (PSR), as well as complementary outputs.

FIG. 3 illustrates in block diagram form ring voltage controlled oscillator 86. VCO 86 varies from previous ring oscillators in two respects. First, VCO 86 includes an even number of delay stages 140. VCO 86 is able to generate 180.degree. phase shift with an even number of delay stages 140 because each delay stage 140 generates two complementary outputs that are appropriately coupled to the next delay stage. Second, VCO 86 includes a greater number of delay stages than normal. VCO 86 is able to include more delay stages because each delay stage 140 contributes less delay then prior delay stages.

Each delay stage 140a-140f of VCO 86 generates two pairs of complementary output signals, OUT and OUTB, and CK and CKB. CK and CKB are buffered, level shifted versions of OUT and OUTB. Thus, CK and CKB have the same voltage swings and frequencies as OUT and OUTB. The buffering of CK and CKB prevents their loading from affecting the stability of VCO 86.

Delay stages 140a-140f are coupled together via OUT and OUTB so that the entire phase shift from the input of delay stage 140a to the output of delay stage 140f is greater than or equal to 180.degree. at the oscillation frequency. Outputs OUT of delay stages 140a-140e are coupled together to the INB inputs of the next delay stage 140b-140f. Outputs OUTB of delay stages 140a-140e are coupled to inputs IN of delay stages 140b-140f. Only the coupling between delay stages 140f and 140a varies from this pattern.

Outputs CK and CKB of each stage stage 140a-140f are coupled to subloops 54 and 56 as two of the twelve phases 58 output by VCO 86.

Control voltage, V.sub.c 85, controls the frequency at which each delay stage 140a-140f switches via bias voltage, V.sub.BN 160. V.sub.c 85 can vary between 3.5 volts to 0 volts, giving VCO 86 a wide locking range. V.sub.c 85 also ensures that phase signals PH(11:0) 58 have a symmetrical voltage swing via bias voltage, V.sub.BP 162.

FIG. 4 illustrates the relationship between the twelve phase signals 58 generated by VCO 86. When PLL 36 is in lock PH0 90 should be in-phase with reference signal, RCLK.sub.S, except for the static phase error contributed by amplifiers 74 and 76, and charge pump 82. The remaining phases, PH(11:1) 58, are evenly spaced across the clock period of RCLK.sub.S.

The first stage of VCO 86, delay stage 140a, outputs PH0 90 and PH6 102. These signals may be referred to as PH0 and its complement or PH6 and its complement.

The second delay stage 140b generates PH1 92 and PH7 104. These signals are also referred to as PH1 and it complement or PH7 and its complement.

PH2 94 and PH8 106 are the outputs of the delay stage 140c. These signals are also referred to as PH2 and its complement or PH8 and its complement.

Complementary phase signals PH3 96 and PH9 108 are generated by delay stage 140d.

The fifth delay stage 140e generates the complementary phase signals PH4 98 and PH10 110.

Delay stage 140f generates PH5 100 and PH11 112. These signals are also referred to as PH5 and its complement or PH11 and its complement.

FIG. 5 is a schematic diagram of a delay stage 140 within VCO 86. Delay stage 140 includes differential amplifier 164, current source 166, and source follower buffer 168.

The delay time of delay stage 140 is controlled by bias current I.sub.B 181. Varying I.sub.B 181 varies the delay time of delay stage 140. Bias current I.sub.B 181 is, in turn, controlled by bias voltage, V.sub.BN 160. The delay time of delay stage 140 is smallest when V.sub.BN is at its maximum level of 3.5 volts.

Another factor contributes to the relatively small delay time of delay stage 140. Unlike prior delay stages, the voltage swing of OUT and OUTB and CK and CKB is limited. This increases the frequency range of delay stage 140, allowing it to operate at higher frequencies.

Limiting the voltage swing of OUT and OUTB and CK and CKB also increases power supply rejection (PSR) by preventing transistors 186, 188 and 167 from entering deeply into their linear region of operation and keeping their output resistance relatively high.

The biasing of transistors 186 and 188 is controlled by V.sub.BP 162. The bias generator for V.sub.BP 162 (not shown) uses a simple current mirror design. More complex bias generators, which include common-mode feedback, could be used to set V.sub.BP 162 such that the desired voltage level is maintained at OUT and OUTB.

The voltage swing between OUT and OUTB is limited to approximately 1.5 volts peak-to-peak by transistors 190 and 192. Transistors 190 and 192 are coupled in diode fashion between OUT and OUTB, thus clamping the peak-to-peak voltage swing.

The range of possible voltage levels for OUT and OUTB is 4.5 volts to 3.0 volts. This is illustrated by the two waveforms in the upper right corner of FIG. 5. The range of voltage levels for CK and CKB is 3.3 volts to 1.8 volts. This is illustrated by the two waveforms in the lower right corner of FIG. 5.

The symmetrical shape of CK, CKB, OUT and OUTB results because I.sub.C 180 is approximately equal to 2.times.I.sub.B 181. Setting the common mode voltage level of OUT and OU