|
|
|
| United States Patent | 5489804 |
| Link to this page | http://www.wikipatents.com/5489804.html |
| Inventor(s) | Pasch; Nicholas F. (Pacifica, CA) |
| Abstract | A ring-shaped, substantially planar structure is described for interposing
between a chip and a substrate. The ring-shaped structure, being more
flexible than a similar solid structure, conforms more readily to any
irregularities in the surface of the substrate. Through holes in the
planar structure facilitate controlled formation of reflow solder
connections between the chip and the substrate. In one embodiment, the
ring shape of the planar structure has a gap to facilitate better
conformance to irregularities in the surface of the substrate and to
minimize "levering" of the chip. Other embodiments provide for "kerfing"
of the ring-shaped planar structure to permit even greater flexibility of
the structure and less levering of the chip. Angled through holes permit
adaptation of mismatched solder bump patterns on the chip and substrate.
Other embodiments are directed to conductive elements embedded within the
planar structure for making electrical contact with selected solder joints
and/or to prevent electrogalvanic corrosion of solder bumps with different
compositions. |
|
|
|
Title Information  |
|
|
|
|
|
Drawing from US Patent 5489804 |
|
|
Flexible preformed planar structures for interposing between a chip and
a substrate |
|
|
|
|
|
| Publication Date |
*
February 6, 1996 |
|
|
|
|
|
| Filing Date |
August 12, 1993 |
|
|
|
|
|
|
|
|
|
|
|
| Parent Case |
CROSS-REFERENCE TO RELATED CASES
This is a continuation-in-part of commonly-owned, U.S. patent application
Ser. No. 07/981,096, filed Nov. 24, 1992 (now U.S. Pat. No. 5,299,730,
issued Apr. 5, 1994), which is a continuation of U.S. patent application
Ser. No. 07/775,009, filed Oct. 11, 1991 (now U.S. Pat. No. 5,168,346,
issued Dec. 1, 1992), which is a continuation of U.S. patent application
Ser. No. 07/576,182, filed Aug. 30, 1990 (now U.S. Pat. No. 5,111,279,
issued May 5, 1992), which is a continuation of U.S. patent application
Ser. No. 07/400,572, filed Aug. 28, 1989 (now abandoned). |
|
|
|
|
|
|
|
|
|
|
|
|
|
Title Information  |
|
|
References  |
|
|
| *references marked with an asterisk below are user-added references |
|
U.S. References |
|
|
| Add a new US reference: |
| | Reference | Relevancy | Comments | Reference | Relevancy | Comments | 3388301
|      Your vote accepted [0 after 0 votes] | | 3429040
|      Your vote accepted [0 after 0 votes] | | 3624462
|      Your vote accepted [0 after 0 votes] | | 3811186
|      Your vote accepted [0 after 0 votes] | | 3835531
|      Your vote accepted [0 after 0 votes] | | 3871014
|      Your vote accepted [0 after 0 votes] | | 5347162 Pasch 257/773 Sep,1994 |      Your vote accepted [0 after 0 votes] | | 5258648 Lin 257/778 Nov,1993 |      Your vote accepted [0 after 0 votes] | | 5168346 Pasch 257/738 Dec,1992 |      Your vote accepted [0 after 0 votes] | | 5149958 Hallenbeck 250/216 Sep,1992 |      Your vote accepted [0 after 0 votes] | | 5111279 Pasch 257/778 May,1992 |      Your vote accepted [0 after 0 votes] | | 5077633 Freyman
Dec,1991 |      Your vote accepted [0 after 0 votes] | | 5059553 Berndlmaier 438/614 Oct,1991 |      Your vote accepted [0 after 0 votes] | | 5039628 Carey 228/180.21 Aug,1991 |      Your vote accepted [0 after 0 votes] | | 5006673 Freyman 174/255 Apr,1991 |      Your vote accepted [0 after 0 votes] | | 4970577 Ogihara 257/698 Nov,1990 |      Your vote accepted [0 after 0 votes] | | 4970575 Soga 257/786 Nov,1990 |      Your vote accepted [0 after 0 votes] | | 4926241 Carey 257/698 May,1990 |      Your vote accepted [0 after 0 votes] | | 4830264 Bitaillou 228/180.21 May,1989 |      Your vote accepted [0 after 0 votes] | | 4827118 Shibata 257/432 May,1989 |      Your vote accepted [0 after 0 votes] | | 4825284 Soga 257/717 Apr,1989 |      Your vote accepted [0 after 0 votes] | | 4811082 Jacobs 257/700 Mar,1989 |      Your vote accepted [0 after 0 votes] | | 4783722 Osaki 361/779 Nov,1988 |      Your vote accepted [0 after 0 votes] | | 4733096 Horiguchi 358/482 Mar,1988 |      Your vote accepted [0 after 0 votes] | | 4700473 Freyman 29/846 Oct,1987 |      Your vote accepted [0 after 0 votes] | | 4700276 Freyman 361/771 Oct,1987 |      Your vote accepted [0 after 0 votes] | | 4664309 Allen 228/180.22 May,1987 |      Your vote accepted [0 after 0 votes] | | 4636631 Carpentier 250/216 Jan,1987 |      Your vote accepted [0 after 0 votes] | | 4553036 Kawamura 250/208.1 Nov,1985 |      Your vote accepted [0 after 0 votes] | | 4545610 Lakritz 438/125 Oct,1985 |      Your vote accepted [0 after 0 votes] | | 4478915 Poss 428/607 Oct,1984 |      Your vote accepted [0 after 0 votes] | | 4425501 Stauffer 250/216 Jan,1984 |      Your vote accepted [0 after 0 votes] | | 4355463 Burns 29/827 Oct,1982 |      Your vote accepted [0 after 0 votes] | | 4190855 Inoue 257/668 Feb,1980 |      Your vote accepted [0 after 0 votes] | | |
|
|
|
|
U.S. References |
|
|
Foreign References |
|
|
|
|
|
|
Foreign References |
|
|
Other References |
|
|
|
|
|
|
Other References |
|
|
|
|
|
References  |
|
|
|
|
|
| Market Size |
|
Estimate the gross annual revenues of the relevant market
sector:
|
| | |
| |
|
|
| Market Share |
|
Estimate the percentage of the relevant market sector this invention will capture:
|
| | |
| |
|
|
| Reasonable Royalty |
|
What percentage of gross sales should the inventor or assignee be paid?
|
| | |
| |
|
|
|
Public's "Guesstimation" of Royalty Value
|
| Market Size | N/A | [No votes] | | x | Market Share | N/A | [No votes] | | x | Reasonable Royalty | N/A | [No votes] |
| | N/A | |
| |
|
|
|
|
|
|
|
|
|
|
|
|
Market Review  |
|
|
Technical Review  |
|
|
Claims  |
|
|
What is claimed is:
1. A semiconductor assembly, comprising:
a chip having first solder balls disposed in a ring shaped pattern on a
face thereof;
a substrate having corresponding second solder balls disposed in a
ring-shaped pattern on a face thereof;
a separate and distinct preformed planar structure disposed between the
chip and the substrate, the preformed planar structure formed in a
ring-shape closely matching the ring-shaped patterns of solder balls on
the chip and the substrate and having two opposite faces, one face in
contact with the chip and the opposite face in contact with the substrate;
through holes extending through the preformed planar substrate from the one
face to the opposite face;
conductive elements made of noble metal foil embedded within the preformed
planar structure and extending into said through holes, wherein said
conductive elements delineates each of the through holes into a first
portion and a second portion; and
solder joints formed by the first solder balls and the second solder balls
within said through holes to said conductive elements, wherein each of the
first solder balls fuse to one side of the noble metal foil in the first
portion and each of the second solder balls fuse to another side of the
noble metal foil in the second portion.
2. A semiconductor assembly according to claim 1, wherein:
at least some of the through holes are angled such that openings of said
angled through holes on the one side of the preformed planar structure
occur at points not directly opposite corresponding openings on the
opposite side of the preformed planar structure.
3. A semiconductor assembly according to claim 1, further comprising:
at least one external connection point on the preformed planar structure
connected to at least one of said conductive elements.
4. A semiconductor assembly according to claim 1, further comprising:
a plurality of spaced-apart grooves ("kerfs") formed in at least one of the
faces of the preformed planar structure.
5. A semiconductor assembly according to claim 1, further comprising:
a gap in the ring shape of the preformed planar structure, extending
completely therethrough from one face thereof to the opposite face
thereof.
6. A semiconductor assembly according to claim 5, wherein:
at least some of the through holes are angled through holes formed at a
non-perpendicular angle relative to the faces of the preformed planar
structure such that openings of said angled through holes on the one side
of the preformed planar structure occur at points not directly opposite
corresponding openings on the opposite side of the preformed planar
structure.
7. A structure for interposing between a semiconductor die having a
ring-shaped pattern of solder balls on a surface thereof and a substrate
having a ring-shaped pattern of solder balls on a surface thereof,
comprising:
a preformed planar structure disposed between a chip and a substrate,
formed in a ring-shape closely matching the ring-shaped patterns of solder
balls on the chip and the substrate, and having two opposite faces, one
face in contact with the chip and the opposite face in contact with the
substrate; and
through holes extending through the preformed planar substrate from the one
face to the opposite face for forming solder joints to conductive elements
made of noble metal foil embedded within the preformed planar structure
and extending into said through holes, wherein said conductive elements
delineates each of the through holes into a first portion and a second
portion, said solder joints formed by the first solder balls and the
second solder balls within said through holes to said conductive elements,
wherein each of the first solder balls fuse to one side of the noble metal
foil in the first portion and each of the second solder balls fuse to
another side of the noble metal foil in the second portion.
8. A structure according to claim 7, wherein:
at least some of the through holes are angled through holes formed at a
non-perpendicular angle relative to the faces of the preformed planar
structure such that openings of said angled through holes on the one side
of the preformed planar structure occur at points not directly opposite
corresponding openings on the opposite side of the preformed planar
structure.
9. A structure according to claim 7, further comprising:
at least one external connection point on the preformed planar structure
connected to at least one of said conductive elements.
10. A structure according to claim 7, further comprising:
a plurality of spaced-apart grooves ("kerfs") formed in at least one of the
faces of the preformed planar structure.
11. A structure according to claim 7, further comprising:
a gap in the ring shape of the preformed planar structure, extending
completely therethrough from one face thereof to the opposite face
thereof.
12. A structure according to claim 11, wherein:
at least some of the through holes are angled through holes formed at a
non-perpendicular angle relative to the faces of the preformed planar
structure such that openings of said angled through holes on the one side
of the preformed planar structure occur at points not directly opposite
corresponding openings on the opposite side of the preformed planar
structure.
13. A structure according to claim 11, further comprising:
a plurality of spaced-apart grooves ("kerfs") formed in at least one of the
faces of the preformed planar structure. |
|
|
|
|
Claims  |
|
|
Description  |
|
|
TECHNICAL FIELD OF THE INVENTION
The invention relates to semiconductor "flip-chip" manfacturing techniques
and, more particularly, to the fluxing and soldering steps employed in
flip-chip manufacture.
BACKGOUND OF THE INVENTION
"Flip-chip" manufacturing techniques involve soldering one or more
semiconductor (silicon) chips (one is discussed), in face-to-face
relationship, to another semiconductor chip termed a "substrate".
Typically, solder balls (otherwise known as pads or bumps) are formed
(raised above the planar surface of the chip and substrate) on facing
surfaces of both the chip and the substrate at intended points of contact
between the two, liquid flux (rosin) is often applied to the face of the
chip and/or substrate, the chip is mechanically held in register with the
substrate, and the chip and the substrate are subjected to elevated
temperature to effect soldering, or fusion of the solder balls on the chip
and the corresponding solder balls on the substrate.
The "solder balls" on either the chip or substrate, typically those on the
substrate, may be solderable metallized surfaces. The soldering process
may be carried out in a reducing atmosphere. A typical flip-chip structure
is shown in FIG. 1, and is discussed in greater detail hereinafter.
Previous systems of rigid attachment of chips to chucks have been used for
chip alignment, but they must allow some degree of compliance because the
chips tend to change relative alignment during soldering by surface
tension between the solder balls. The addition of liquid flux to the
chip/substrate (flip-chip) assembly creates capillary attraction between
the chip and the substrate, which serves to mis-align the chip with
respect to the substrate. This is illustrated in FIG. 2, and is discussed
in greater detail hereinafter. Further, much of the flux that is applied
to the flip-chip assembly is wasted. Still further, the dimension of the
remaining gap between the chip and the substrate and the mechanical
properties of the solder joints formed by the solder balls and
corresponding solder balls tends to be indeterminate.
The present invention is more broadly (i.e., than chip-to-chip) directed to
connecting one or more semiconductor "chips" (dies) to one or more
"substrates" such as other semiconductor dies, printed circuit (or wiring)
boards, and the like. The resulting assembly is termed a "flip-chip
structure".
DISCLOSURE OF THE INVENTION
It is therefore an object of the invention to provide a flip-chip
manufacturing technique which reduces capillary action, and hence
misalignment, between a chip and a substrate.
It is a further object of the invention to provide a flip-chip
manufacturing technique which requires the use of less flux, and which
controls the position of the flux between the chip and the substrate.
It is a further object of the invention to provide a flip-chip
manufacturing technique which provides a controlled spacing between chips
and the substrate.
It is a further object of the invention to provide a flip-chip
manufacturing technique which provides solder joints having predictable
and tailorable mechanical characteristics.
It is a further object of the invention to provide a flip-chip
manufacturing technique that simplifies the face-to-face joining of the
chip and substrate.
According to the invention, a preformed planar structure is interposed
between the chip(s) and the substrate in a flip-chip structure. The
preformed planar structure establishes a minimum gap between the chip(s)
and the substrate.
According to a feature of the invention, liquid flux is applied to the
preformed planar structure in order that flux is selectively applied to
the solder balls (pads) on the chip and the substrate.
In an embodiment of the invention, the preformed planar structure is
provided with through holes in registration with the solder balls (pads)
on the chip(s) and the substrate. In this embodiment, liquid flux
selectively fills the through holes for delivery to the solder balls
during soldering. The through holes also aid in maintaining registration
of the chip(s) and the substrate.
According to an aspect of the invention, the through holes are sized to
establish a predetermined mechanical structure of solder joints formed by
the solder balls when fused together.
According to an aspect of the invention, the preformed planar structure has
a planar core and opposing planar faces. The core is formed of
thermosetting organic resin, such as polyimide, or non-organic material
such as alumina, polished sapphire, beryllium oxide, aluminum or aluminum
nitride. The planar faces of the preformed planar structure are formed of
thermoplastic resin or thermosetting material, such as polyacetal, epoxy
(epoxy resins) or polystyrene. The preformed planar structure tends to
draw the chip(s) together to the substrate, establishing a flip-chip
structure or mechanical integrity.
According to an aspect of the invention, the preformed planar structure has
a thickness of 5-50 microns, preferably on the order of 20-30 microns.
Additional and further embodiments and variations of a preformed planar
structure are set forth below, with respect to the descriptions of FIGS.
6-15.
Other objects, features and advantages of the invention will become
apparent in light of the following description thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of a typical, prior art flip-chip
structure.
FIG. 2 is a cross-sectional view of a prior art flip-chip assembly
illustrating capillary action caused by liquid flux, resulting in the
misalignment of a chip with respect to a substrate.
FIG. 3 is an exploded cross-sectional view of a flip-chip assembly, prior
to soldering, according to a technique of the invention.
FIG. 4 is a perspective view of a plastic standoff element (preformed
planar structure) employed in the technique of FIG. 3.
FIG. 5 is a perspective view of an alternate embodiment of a standoff
element suitable to be employed in the technique of FIG. 3.
In the description of further embodiments of a preformed planar structure
that follows, the preformed planar structure may alternately be referred
to as an "interposer".
FIG. 6 is an exploded cross-sectional view of a flip-chip assembly
incorporating a preformed planar structure (interposer), according to the
invention.
FIG. 6a is a cross-sectional view of another embodiment of a preformed
planar structure, similar to that shown in FIG. 6, according to the
invention.
FIG. 6b is a cross-sectional view of another embodiment of a preformed
planar structure, similar to that shown in FIG. 6a, according to the
invention.
FIG. 6c is a cross-sectional view of an encapsulated semiconductor die
assembled to a preformed planar structure, according to the invention.
FIG. 7 is a cutaway view of a preformed planar structure including a
ring-shaped array of angled through holes, according to the invention.
FIG. 7a is a top view of the preformed planar structure of FIG. 7.
FIG. 7b is a top view of a preformed planar structure with a rectangular
array of angled through holes, according to the invention.
FIG. 8 is a cross-sectional view of a semiconductor device assembly
employing a preformed planar structure as a connection "pitch adapter",
according to the invention.
FIG. 8a is a cross-sectional view of a semiconductor device assembly
employing a multi-layer preformed planar structure as a connection pitch
adapter, according to the invention.
FIG. 9a is a view of a semiconductor device assembly employing dissolvable
preformed planar structures, according to the invention.
FIG. 9b is a view of a the semiconductor device assembly of FIG. 9a, after
dissolving the preformed planar structures.
FIG. 10a is a view of a ring-shaped preformed planar structure, according
to the invention.
FIG. 10b is a view of a gapped ring-shaped preformed planar structure,
according to the invention.
FIG. 10c is a close-up top view of a portion of a leg of a kerfed
ring-shaped preformed planar structure (interposer), according to the
invention.
FIG. 10d is a side view of the kerfed interposer of FIG. 10c.
| | |