Output driver with slew and skew rate control

Claims

What is claimed is:

1. An output buffer circuit having skew and slew control, comprising:

an output driver transistor coupling an output terminal to a ground terminal responsive to a voltage in excess of a threshold at a base input of said output driver transistor;

first feedback circuitry coupled to said output terminal and said base input for supplying a first current into said base input, said first feedback circuitry supplying said first current in response to a first voltage at an input signal;

second feedback circuitry coupled to said output terminal and said base input, said second feedback circuitry supplying a second current into said base input in response to said first voltage at said input signal;

output voltage compensation circuitry coupled to said circuit output and said base input for supplying a third current into said base input while said output driver transistor is enabled, said third current being supplied when the voltage at said circuit output terminal exceeds a predetermined threshold; and

current discharge circuitry which couples said base input of said output driver transistor to a ground voltage for discharging the potential at the base of said output driver transistor in response to a second voltage at said input signal.

2. The output buffer circuit of claim 1, wherein said output voltage compensation circuitry comprises:

a current source being controlled by a bias current to output a predetermined current to said base input of said output driver transistor;

current sensing circuitry coupled to the output terminal, and outputting a voltage proportional to the voltage at the output terminal;

a pull down transistor coupled to said current sensing circuitry, operable to pull down a circuit node in response to the voltage output by said current sensing circuitry; and

a current sinking transistor coupled to said current source and having a gate terminal coupled to said circuit node, operable to sink current and thereby limit the current flowing into the base of said output driving transistor in response to the voltage at said circuit node.

3. The output buffer circuit of claim 1, wherein said current discharge circuitry comprises:

a current sinking transistor between said base input of said output driving transistor and ground, and having a gate terminal controlled by a predetermined bias current;

an enable transistor counted between said base input of said output driving transistor and said current sinking transistor, said enable transistor acting in response to a high voltage at said input; and

first and second diodes coupled in series between said base input terminal of said output driving transistor and said enable transistor;

said current discharge circuitry operable to sink current from said base input terminal of said output driving transistor at a predetermined rate as determined by said bias current input to said current sinking transistor, said base input terminal being discharged until the voltage at said base input terminal reaches a predetermined voltage above ground, the predetermined voltage being set by the voltage drop across said first and second diodes.

4. The output buffer circuit of claim 1, wherein said first feedback circuitry comprises:

a MOS transistor coupling said circuit output terminal to said base input terminal, and having its gate coupled to said circuit input terminal; and

a current limiting resistor coupled between said MOS transistor and said base input terminal;

wherein the value of said current limiting resistor and the size of said MOS transistor cause a predetermined current to flow into the base input terminal of said output driving transistor.

5. The output buffer circuit of claim 1, wherein said second feedback circuitry comprises:

a delay element coupled to said circuit input terminal;

a MOS transistor coupling said circuit output terminal to said base input terminal, and having its gate coupled to said delay element; and

a current limiting resistor coupled between said MOS transistor and said base input terminal;

wherein the delay element, the value of said current limiting resistor and the size of said MOS transistor cause a predetermined current to flow into the base input terminal of said output driving transistor after a predetermined time delay following a transition from a high voltage to a low voltage at said circuit input terminal.

6. The output buffer circuit of claim 1, wherein said output driving transistor comprises a NPN bipolar transistor having a collector coupled to said output terminal, an emitter coupled to a ground voltage, and a base coupled to said base input.

7. The output buffer circuit of claim 1, wherein said output driving transistor comprises a PNP bipolar transistor having an emitter coupled to said output terminal, a collector coupled to a ground voltage, and a base coupled to said base input.

8. An output buffer circuit having skew and slew control, comprising:

an output driver transistor coupling a circuit output terminal to a ground terminal in response to a voltage which exceeds a threshold at a base input of said output driver transistor;

a plurality of serially coupled feedback circuitry elements, each coupled to said circuit output terminal and said base input, each for supplying a current into said base input in response to a first voltage at an input, said plurality of serially coupled feedback circuitry elements providing a plurality of predetermined currents into said base input following a low to high transition in the voltage at said input;

output voltage compensation circuitry coupled to said circuit output and said base input for controlling a third current into said base input while said output driver transistor is enabled, said third current being reduced when the voltage at said circuit output terminal is beneath a predetermined threshold; and

current discharge circuitry coupled to said base input of said output driver transistor and to a ground voltage for discharging the potential at the base of said output driver transistor in response to a high to low transition in the voltage at said input.

9. The output buffer circuit of claim 8, wherein said output voltage compensation circuitry comprises:

a current source coupled to a supply voltage and being controlled by a current control node to output a current to the base input of said output driver transistor, the amount of current output by said current source being within a predetermined range and being proportional to the voltage level at said current control node;

current sensing circuitry coupled to the circuit output terminal, and outputting a voltage proportional to the voltage at the circuit output terminal; and

a pull down transistor coupled to said current sensing circuitry, operable to pull down said current control node in response to the voltage output by said current sensing circuitry;

said pull down transistor varying the voltage at said current control node so that when the voltage at said circuit output terminal exceeds a certain threshold, the current source provides a predetermined current to the base input of said output driving transistor.

10. The output buffer circuit of claim 8, wherein said current discharge circuitry comprises:

a current sinking transistor coupled between said base input of said output driving transistor and a ground voltage, and having a gate terminal controlled by a predetermined bias current;

an enable transistor coupled between said base input of said output driving transistor and said said current sinking transistor and enabled by a high voltage at said input; and

first and second diodes coupled in series between said base input terminal of said output driving transistor and said enable transistor;

said current discharge circuitry operable to sink current from said base input terminal of said output driving transistor at a predetermined rate as determined by said bias current input to said current sinking transistor, said base input terminal being discharged until the voltage at said base input terminal reaches a predetermined voltage above ground, the predetermined voltage being set by the voltage drop across said first and second diodes.

11. The output buffer circuit of claim 8, wherein each of said plurality of feedback circuits comprises:

a delay element coupled to said input;

a MOS transistor coupled between said circuit output terminal and said base input terminal, and having a gate terminal coupled to said delay element; and

a resistor coupled between said MOS transistor and said base input terminal;

the value of said delay element, said resistor, and said MOS transistor providing a predetermined current into said base input terminal after a predetermined delay following a transition at said input.

12. A method of providing an output buffer with skew and slew rate control, comprising the steps of:

providing an output driver transistor coupling an output terminal to a ground terminal in response to the voltage at a base input;

providing first feedback circuitry coupled between said circuit output terminal and said base input, said first feedback circuitry supplying a first current into said base input responsive to a first voltage level at an input;

providing second feedback circuitry coupled between said circuit output terminal and said base input, said second feedback circuitry supplying a second current into said base input responsive to said first voltage level at said input;

providing output voltage compensation circuitry coupled to said circuit output and said base input for supplying a third current into said base input while said output driver transistor is enabled, said third current being supplied when the voltage at said circuit output terminal exceeds a predetermined threshold; and

providing current discharge circuitry coupled between said base input of said output driver transistor and a ground voltage, said current discharge circuitry discharging the potential at the base of said output driver transistor responsive to a second voltage level at said circuit input terminal.

13. The method of claim 12, wherein said step of providing output voltage compensation circuitry comprises the steps of:

providing a current source controlled by a bias current, said current source outputting a predetermined current to the base input of said output driver transistor;

providing current sensing circuitry coupled to the output terminal, for outputting a voltage proportional to the voltage at the output;

providing a pull down transistor coupled to said current sensing circuitry, operable to pull down a circuit node in response to the voltage output by the current sensing circuitry;

providing a current sinking transistor coupled to said current source and having a gate terminal coupled to said circuit node; and

operating said current source, current sensing circuitry, said pull down transistor and said current sinking transistor so that when the voltage at said circuit output terminal exceeds a predetermined threshold the current sensing circuitry will cause said pull down transistor to pull down said circuit node and cause said current sinking transistor to sink current, thereby limiting the current flowing into the base of said output driving transistor.

14. The method of claim 12, wherein said step of providing current discharge circuitry comprises the steps of:

providing a current sinking transistor coupled between said base input of said output driving transistor and a ground voltage, and having a gate terminal controlled by a predetermined bias current;

providing an enable transistor coupled between said base input of said output driving transistor and said current sinking transistor and enabled by a high voltage at said input;

providing first and second diodes coupled in series between said base input terminal of said output driving transistor and said enable transistor; and

operating said current discharge circuitry to sink current from said base input terminal of said output driving transistor at a predetermined rate as determined by said bias current input to said current sinking transistor, said base input terminal being discharged until the voltage at said base input terminal reaches a predetermined voltage above ground, the predetermined voltage being set by the voltage drop across said first and second diodes.

15. The method of claim 12, wherein said step of providing first feedback circuitry comprises the steps of:

providing a MOS transistor coupled between said circuit output terminal to said base input terminal, and having its gate coupled to said input;

providing a current limiting resistor coupled between said MOS transistor and said base input terminal; and

said current limiting resistor and the size of said MOS transistor causing a predetermined current to flow into the base input terminal of said output driving transistor in response to the voltage level at said input.

16. The method of claim 12, wherein said step of providing said second feedback circuitry comprises the steps of:

providing a delay element coupled to said input;

providing a MOS transistor coupled between said circuit output terminal to said base input terminal, and having its gate coupled to said delay element;

providing a current limiting resistor coupled between said MOS transistor and said base input terminal; and

delay element, the value of said current limiting resistor and the size of said MOS transistor causing a predetermined current to flow into the base input terminal of said output driving transistor after a predetermined time delay following a transition at said input from a high voltage to a low voltage.

17. The method of claim 12, wherein said step of providing an output driving transistor comprises providing an NPN bipolar transistor having a collector coupled to said circuit output terminal, an emitter coupled to a ground voltage, and a base coupled to said base input.

18. The method of claim 12, wherein said step of providing an output driving transistor comprises providing a PNP bipolar transistor having an emitter coupled to said circuit output terminal, a collector coupled to a ground voltage, and a base coupled to said base input.

19. A method for providing an output buffer circuit having skew and slew control, comprising the steps of:

providing an output driver transistor coupling a circuit output terminal to a ground terminal in response to a voltage exceeding a threshold at a base input;

providing a plurality of serially coupled feedback circuitry elements, each of said plurality of serially coupled feedback circuitry elements further coupled between said circuit output terminal and said base input, and each of said feedback circuitry elements for supplying a current into said base input responsive to a first voltage at an input, said plurality of serially coupled feedback circuitry elements providing a plurality of predetermined currents into said base input following a low to high transition in the voltage at said input;

providing output voltage compensation circuitry coupled between said circuit output terminal and to said base input, said output voltage compensation circuitry controlling a third current into said base input while said output driver transistor is enabled, said third current being reduced when the voltage at said circuit output terminal is beneath a predetermined threshold; and

providing current discharge circuitry coupled between said base input of said output driver transistor and a ground voltage, said current discharging circuitry discharging the base of said output driver transistor when a high to low transition occurs in the voltage at said input.

20. The method of claim 19, wherein said step of providing output voltage compensation circuitry comprises the steps of:

providing a current source controlled by a current control node to output a current to the base input of said output driver transistor, the amount of current output by said current source being within a predetermined range and being proportional to the voltage at said current control node;

providing current sensing circuitry coupled to the output terminal, and outputting a voltage proportional to the voltage at the output terminal;

providing a pull down transistor coupled to said current sensing circuitry, operable to pull down the voltage at said current control node in response to the voltage output by the current sensing circuitry; and

operating said pull down transistor to vary the voltage at said current control node so that when the voltage at said circuit output terminal exceeds a predetermined threshold, the current source provides a predetermined current to the base of said output driving transistor.

21. The method of claim 9, wherein said step of providing current discharge circuitry comprises the steps of:

providing a current sinking transistor coupled between said base input of said output driving transistor and a ground voltage, and having a gate terminal controlled by a predetermined bias current;

providing an enable transistor coupling said base input of said output driving transistor to said current sinking transistor, said enable transistor having a gate input coupled to said input and being enabled when the voltage at said input exceeds a threshold voltage;

providing first and second diodes coupled in series between said base input terminal of said output driving transistor and said enable transistor; and

operating said current discharge circuitry to sink current from said base input terminal of said output driving transistor at a predetermined rate as determined by said bias current input to said current sinking transistor, said base input terminal being discharged until the voltage at said base input terminal reaches a predetermined voltage above ground, the predetermined voltage being set by the voltage drop across said first and second diodes.

22. The method of claim 19, wherein said step of providing each one of said plurality of feedback circuits comprises the steps of:

providing a delay element coupled to said input;

providing a MOS transistor coupled between said circuit output terminal and said base input terminal, and having a gate terminal coupled to said delay element;

providing a resistor coupled between said MOS transistor and said base input terminal; and

said delay element, said resistor, and said MOS transistor providing a predetermined current into said base input terminal after a predetermined delay following a transition in the voltage at said input.

FIELD OF THE INVENTION

This invention relates generally to integrated circuits for circuits and systems which use high speed, low voltage level busses for data communications, and specifically to the design of output drivers and transceiver devices compatible with low voltage level, high speed data transmission busses.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the co-pending U.S. patent application entitled "Output Driver with Slew Rate Control", filed Oct. 13, 1994, U.S. patent application Ser. No. 08/323,330, TI Docket No. TI-19325, and assigned to Texas Instruments Incorporated, herein incorporated by reference.

BACKGROUND OF THE INVENTION

In increasing the data throughput rate for bussed systems, such as processors, memories, personal computers and computer systems, the use of low signal level data transmission busses has been proposed. By reducing the high output voltage level standard for a particular bus, the switching time is improved because the voltage swing from a high output level to a low output level is limited to a few hundred millivolts, as opposed to the older bus standards which required as much as 5 volts of swing to transition from a high voltage state to a low voltage state. The Futurebus standard, for example, has a reduced high level output voltage, a tight specification requirement on the slew rate of the output devices, and a tight specification requirement of the skew, that is the difference between the low-to-high delay. Also, the output drivers are required not to pull the bus below a certain defined low output level voltage, so that the voltage swing is required to be between two tightly defined high and low voltage levels. The bus specification also requires that the output devices be open-collector or open-drain types, that is the bus is pulled up to the high output state by an external R-C network. The output drivers must then overcome these pullup circuits to assert a low voltage level on the bus.

The problem in implementing low voltage level signal busses like the Futurebus using the circuits of the prior art is that switching noise produced by the output driving devices can cause erroneous results in the signal receiving devices. The noise problem is worse for these busses than for older bus standards because the available noise margins have been greatly reduced. If the device driving the bus switches quickly from a high state, that is letting the bus rise to a defined high output level, to a low state, that is outputting a signal of approximately zero volts, ringing may occur on the bus. This ringing can cause the receiving devices to erroneously input a transient as true data, that is the ring can look like a zero state on the bus followed by a high state, then a second zero state. The ringing is caused because the transition from the high state to the low state by the output driver is happening too sharply. This problem is often stated as a slew rate of the output driver device which is too fast.

Further, prior art circuits which address the slew rate problem often only affect it in one direction, that is the slew rate is lowered for the falling edge, for example, but the rising edge is unaffected. This has the effect of increasing the skew rate, the difference between rising and falling transition times, and thus takes the device further away from the bus requirements.

FIG. 1 depicts an exemplary prior art circuit for driving a Futurebus interface. Output buffer 1 is a BiCMOS output driver which includes an input IN for receiving the data to be transmitted on the bus, an inverter 3 for driving the output driving transistor 9, typically an open collector bipolar transistor, as shown here, a base resistor 5 coupled between the inverter 3 and the output driving transistor, and an N channel transistor 7 for feeding the current at the output node into the base of the bipolar transistor 9.

In operation, the circuit of FIG. 1 drives the bus represented by resistor 11 and impedance 13 as follows. Assume initially that the bus is at the high output voltage defined for the Futurebus, e.g. 2.1 Volts, which translates to a high input voltage at the IN terminal. Now assume the IN terminal sees a transition to a low logic level. The inverter 3 responds by outputting a logic one to the base of output transistor 9 and to the gate of N channel transistor 7. As current flows into the base resistor 5, the bipolar transistor 9 moves out of cutoff to a conductive state, so that the collector coupled to the output terminal begins conducting current into the collector, out through the emitter and to ground. Since the output terminal is at a high voltage of 2.1 Volts, the N channel transistor 7 begins taking additional current through its conductive path into the base of bipolar transistor 9, helping to rapidly discharge the output terminal and to provide additional base current to bipolar transistor 9.

When the input terminal IN transitions back to a high logic level, the inverter 3 will output a low logic level voltage and the N channel transistor 7 will cut off. Also the base of bipolar transistor 9 will now be at a low voltage and bipolar transistor 9 will cutoff. The output terminal OUT will then rise to the voltage provided by external pullup resistor 11.

The prior art circuit of FIG. 1 has several problems. There is minimal control of the slew rate of the output terminal. The slew rate of the circuit of FIG. 1 will primarily be determined by the bipolar output driving transistor 9, which will probably be too fast and create transients at the output terminal. Also, the low output voltage will fall to a level of a voltage which is a Vbe drop above ground plus a minimal voltage across the N channel device, which will be lower than is specified for Futurebus applications. Because the rise time of the signal at the OUT terminal is controlled only by the external resistor and load, there is also no skew control, that is there is no relationship between the fall time for the output voltage at the OUT terminal from a high to low output voltage and the rise time from a low to high output voltage.

The proposed high speed bus standards like the Futurebus require output driving circuitry that has a fast transition time and a tightly controlled slew rate and skew, so that switching noise does not exceed the reduced noise margins. In addition, the Futurebus standard requires control of the low output voltage level. The prior art circuitry cannot provide a solution that meets the requirements of these proposed busses. A need for a circuit having fast switching speed and improved slew rate, skew and low output voltage control with low noise characteristics thus exists.

SUMMARY OF THE INVENTION

Generally, and in one form of the invention, a circuit and method for an output driver with controlled slew rate for both the high to low and low to high output transitions and an overall fast output transition time is provided. This circuit provides skew control so that the rise time and fall time are within a certain minimum range. The circuit also provides continuous feedback compensation of the low output voltage to keep the low output voltage level within a desired range. The circuit of the invention includes a current source coupled to the base of an output driving transistor, the current source being biased by a stable bias reference circuit which will provide a controlled current and voltage to the current source across temperature, supply and process variations. The current source provides a predetermined amount of driving current to the output transistor. The base of the output transistor is further coupled to a slew rate control circuit that provides a controlled current supply to the driving transistor when the output is to transition from a high to a low state. The slew rate control circuit has a separate discharge circuit so that the low to high transition time of the output transistor is also controlled, providing skew control. The circuit also includes a feedback compensation circuit that senses the low output voltage and adds or subtracts driving current to the output driving transistor to keep the low output voltage level within a specified range. The slew rate control circuitry allows the output driving transistor to begin the high to low transition quickly, and then controls the slew, so that the overall propagation delay through the circuit remains faster than prior art slew rate controlled output circuits. A second embodiment of the circuit is provided which further refines the feedback circuitry and provides an alternative compensation circuit for the low output voltage level.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 depicts a prior art BiCMOS output circuit;

FIG. 2 depicts a first preferred embodiment of an output driver circuit which incorporates the current source, feedback compensation, and slew rate control circuitry of the invention;

FIG. 3 depicts the circuit detail of a first portion of the bias generator circuit of the first preferred embodiment invention;

FIG. 4 depicts the circuit detail of a second portion of the bias generator circuit of the first preferred embodiment of the invention;

FIG. 5 depicts the circuit detail of a second preferred embodiment of the output circuit of the invention;

FIG. 6 depicts the circuit detail of the bias generator of the second preferred embodiment of the invention; and

FIG. 7 depicts a transceiver device produced as an integrated circuit which incorporates several of the circuits of FIGS. 5 and 6 as output drivers for the integrated circuit.

Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 2 depicts a first preferred embodiment of an output driving circuit incorporating the circuitry of the invention. Output transistor 19 is a large driving transistor, typically an NPN bipolar transistor. The output terminal labeled OUT is coupled to a high speed, low voltage level bus having external pull up termination circuitry, which is not shown. The conductive path of the output transistor 19 couples the output terminal to ground. The base of output transistor 19 is coupled to the output of a current source structure comprised of transistors 41 and 45. The base of the output transistor 19 is further coupled to two speed up circuits: a first speed up circuit comprised of transistor 51, which is controlled by the output of inverter 41, and resistor 53; and a second speed up circuit comprised of transistor 17, delay element 15, and resistor 49. Both of the speed up circuits couple the output terminal back to the base of the output transistor to provide additional drive current during a high to low output transition. The base of output transistor 19 is also coupled to base discharge circuitry made up of Schottky diodes 39 and 37, and a current sink circuit including transistor 35 and transistor 33. The collector of output transistor 19 is coupled to the output terminal labeled OUT and to the low voltage level compensation circuitry made up of transistor 21, resistors 23 and 25, bipolar transistor 27, resistor 29, and transistor 31, which is coupled to the current source circuitry of transistors 45 and 41. Resistor 47 acts as a current limiter for the current source circuit of transistors 45 and 41.

In operation, the bus coupled at the OUT terminal will rise to a high voltage level when there is no active driving output driver on the bus. When a driving transistor asserts a low voltage on the bus, the driving transistor pulls down the bus by coupling the bus to ground. Assume initially that the bus begins in a high voltage level, that is the signal at the data input IN is a high voltage, and output transistor 19 is cutoff, the discharge circuitry of transistors 35 and 33 and diodes 39 and 37 bringing the base of transistor 19 to a predetermined low voltage level, but a predetermined voltage above ground so that the rise time of the base at the next transition is reduced. Now assume a transition occurs at the IN input to a low voltage level. Inverter 43 now puts out a high voltage. Transistor 41 is enabled, which allows the conductive path through the current source of resistor 47 and transistors 45 and 41 to begin pulling up the base of transistor 19. The rate at which the base of transistor 19 will rise is determined by the amount of drive available, which is controlled by the level from the I.sub.-- BIAS.sub.-- 1 input coupled to the gate of transistor 45 and the value of resistor 47. Controlling the bias level at the input I.sub.-- BIAS.sub.-- 1 will therefore allow control of the base voltage rise time for the output transistor 19.

Once the base of transistor 19 starts to rise, the transistor will remain in cutoff until the base-emitter threshold voltage of transistor 19 is exceeded. In order to speed up the turn on of the driving transistor 19, speed up circuits are used. Transistor 51 will turn on in response to the high voltage output by inverter 43. This will feed current from the high potential at the OUT terminal into the base of transistor 19. The amount of current fed into the base will determine the rise time of the base voltage of transistor 19, which in turn will control the slew rate for the falling output transition at the OUT terminal. Transistor 51 is used to control the slew rate. While this feedback path will speed up the initial transition at the OUT terminal, as the OUT terminal falls in response to the turn on of transistor 19, the amount of current available at the base of transistor 19 will also fall, thus reducing the available drive from transistor 19. Under certain load and temperature conditions, the output voltage at the OUT terminal will remain too high if no further drive is provided. The second speed up circuit of transistor 17, resistor 49, and delay element 15 is used to compensate for this reduced drive. A predetermined time after the inverter 43 outputs a high logic level, the delay element 15 puts a high logic level at the gate of transistor 17, and additional current is now fed into the base of output driving transistor 19. Transistor 17 controls the amount of current fed into the base by this second speedup circuit. By carefully designing these two speed up circuits, control of the fall time at the output terminal OUT will be achieved.

After the desired output level at the OUT terminal is reached, the output driver circuit of FIG. 2 must keep the bus low output voltage from falling too low. The bus specification calls for a low output voltage above ground, nominally 1 V, so that when the bus is switched back to a high output level the transition time will be reduced. If the bus falls too low, the pull up circuit must overcome this lower voltage on the next transition to a high state. Output level compensation is provided by transistor 21, resistors 23 and 25, bipolar transistor 27, pullup resistor 29, and current sinking transistor 31.

Normally, the current flowing through the current source of transistors 45, 41 and resistor 47 flows into the base of transistor 19, which is now holding the bus in a low output state by coupling the output OUT to ground. However, some of the current is also taken through current IA in the figure to current sinking transistor 31. The balance between the current IA and the current through transistor 41 into the base of transistor 19 will control the output voltage at the output terminal OUT. Resistor 29 provides a nominal high voltage at the gate of transistor 31. When the output voltage at terminal OUT falls below a predetermined threshold level, the voltage divider made up of resistors 23 and 25 will provide a voltage at the base of bipolar transistor 27 that is too low to achieve turn on, that is transistor 27 will cut off. In this case, the gate of current sink transistor 31 will be fully on, and IA will be at its maximum. This results in a reduction of current into the base of transistor 19, which will reduce its drive and thus the voltage at the OUT terminal will rise.

When the OUT terminal reaches a voltage that is higher than a desired predetermined threshold, the resistor voltage divider consisting of resistors 23 and 25 will provide a voltage at the base of transistor 27 that exceeds its turn on voltage and the gate of current sinking transistor 31 will be coupled to ground, that is pulled low. Transistor 31 will then cut off, and the current IA will be zero. Now the entire current supplied to transistor 45 will be gated into the base of transistor 19, the drive will increase, and the voltage at the OUT terminal will fall as a result. Thus the balance of the current flowing into the IA path with the current supplied by the current source circuitry into the base of transistor 19 keeps the output voltage in a defined range when the input IN is at a low level. Transistor 21 is used to enable and disable this compensation circuitry, so that the compensatio