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Claims  |
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What is claimed is:
1. A structure comprising:
a input port for receiving input data;
a splitter having an input coupled to said input port, and serving to split
said input data into baseband signal streams; and
a baseband signal processing network for receiving said baseband signal
streams and providing cross-correlated processed in phase and quadrature
phase baseband signals.
2. A structure as in claim 1 which further comprises a quadrature modulator
for receiving said processed in phase and quadrature phase baseband
signals and providing a quadrature modulated output signal.
3. A structure as in claim 1 wherein said baseband processing network
comprises for each of an I and Q channel:
an input port for receiving one of said baseband signal streams from said
splitter;
a delay element coupled to said input port for delaying said one of said
baseband signal streams a predefined period of time greater than or equal
to zero and producing a delayed baseband signal;
an amplifier coupled to receive said delayed baseband signal and adjust its
gain to provide a gain adjusted baseband data signal; and
a filter coupled to receive said gain adjusted baseband data signal and
provide a filtered baseband data signal for output to a quadrature
modulator.
4. The structure as in claim 3 wherein said baseband processing network
further comprises a cross-coupler for receiving said filtered baseband
data signal and providing in response thereto a cross-correlated data
output signal for each of said I and Q channels.
5. The structure as in claim 1 wherein said input data comprises an input
signal selected from the group consisting of binary, multilevel filtered,
multilevel unfiltered and analog signals.
6. The structure as in claim 3 wherein said delay provided in said one of
said I and Q channels is greater than the delay provided in the other of
said I and Q channels.
7. The structure as in claim 3 wherein said delay provided in said one of
said I and Q channels is half a bit period greater than the delay provided
in the other of said I and Q channels.
8. The structure as in claim 1 wherein said processed in phase and
quadrature phase baseband signals have amplitudes such that their vector
sum is substantially constant and has reduced resultant quadrature
modulated envelope fluctuations.
9. The structure as in claim 1 which further comprises means for
selectively reducing the cross-correlating factor down to zero.
10. The structure as in claim 2 which further comprises an amplifier
operated in linear mode for amplifying said quadrature modulated signal
and providing a linearly amplified output signal that is band limited.
11. A cross correlated quadrature architecture signal processor for
producing cross correlated in phase and quadrature phase signal streams
for modulation by a Quadrature Modulator comprising:
a filter for receiving an input signal selected from the group of binary,
multi-level, and analog signals and combinations thereof and producing a
filtered input signal;
signal shaping means for integrating said filtered input signal; ,
an amplifier for varying the modulation index of said signal processor,
said amplifier receiving said filtered input signal and providing an
amplified input signal;
a splitter receiving said amplified input signal and providing cross
correlated data streams; and
a signal processor having an in phase and quadrature phase channel each
receiving one of said cross correlated data streams, each of said in phase
and quadrature phase channel having a first delay gain filter, means for
generating Cosine and Sine values for said in phase and quadrature phase
channel datastream, a wave shaper and a second delay gain filter, such
that said signal processor provides in phase and quadrature phase cross
correlated data signals for quadrature modulation with a modulated signal
adaptable for coherent demodulation of the quadrature frequency modulated
(FM) signal.
12. A cross correlated quadrature architecture signal processor for
producing cross correlated in phase and quadrature phase data streams for
modulation by a Quadrature Modulator and subsequent coherent quadrature
demodulation of the quadrature FM modulated signal comprising:
a splitter for receiving an input signal selected from the group of binary,
multi-level, and analog signals and combinations thereof and providing a
pair of identical data signals; and
a signal processor including an in phase and quadrature phase channel each
receiving one of said pair of identical data signals, each of said
channels including
a delay element for receiving said one of said pair of identical data
signals and producing a delayed signal;
an amplifier for receiving said delayed signal and producing an amplified
data signal;
a filter for receiving said amplified signal and producing a filtered data
signal; and
a function generator for generating Cosine and Sine values for said
filtered data signal;
such that said signal processor provides in phase and quadrature phase
cross correlated data signals for quadrature modulation with a modulated
signal adaptable for coherent demodulation of the quadrature FM signal.
13. A cross correlated quadrature architecture signal processor for
producing cross correlated in phase and quadrature phase data streams for
modulation by a Quadrature Modulator and subsequent demodulation of the
quadrature modulated signal comprising:
a splitter for receiving an input signal selected from the group of binary,
multi-level, and analog signals and combinations thereof and providing a
pair of identical signals; and
a signal processor including an in phase and quadrature phase channel each
receiving one of said pair of identical signals, each of said channels
including
a delay element for receiving said one of said pair of identical signals
and producing a delayed signal;
an amplifier for receiving said delayed signal and producing an amplified
signal;
a filter for receiving said amplified signal and producing a filtered
signal;
such that said signal processor provides in phase and quadrature phase
cross correlated signals for quadrature modulation with a modulated signal
suitable for amplification in linear and non-linear mode adaptable for
coherent and noncoherent demodulation.
14. A cross correlated quadrature architecture signal processor for
producing cross correlated in phase and quadrature phase data streams for
modulation by a Quadrature Modulator and subsequent conventional BPSK or
QPSK demodulation of the quadrature modulated signal comprising:
a splitter for receiving an input signal selected from the group of binary,
multi-level, and analog signals and combinations thereof and providing a
pair of identical data signals; and
a signal processor including an in phase and quadrature phase channel each
receiving one of said pair of identical data signals, each of said
channels including
a delay element for receiving said one of said pair of identical data
signals and producing a delayed signal;
an amplifier for receiving said delayed signal and producing an amplified
data signal;
a filter for receiving said amplified signal and producing a filtered data
signal;
such that said signal processor provides in phase and quadrature phase
cross correlated data signals for quadrature modulation with a modulated
signal suitable for amplification in linear and non-linear mode and
adaptable for conventional BPSK or QPSK demodulation.
15. A method of cross correlating an input data signal for use in a
quadrature architecture modulator for producing cross correlated in phase
and quadrature phase data streams for modulation by a Quadrature Modulator
and subsequent conventional BPSK demodulation of the quadrature modulated
signal comprising the steps of:
splitting an input signal selected from the group of binary, multi-level,
and analog signals and combinations thereof and providing a pair of
identical data signals;
delaying each of said pair of identical data signals and producing a pair
of delayed signals;
amplifying each of said pair of delayed signals and producing a pair of
amplified data signals; and
filtering each of said pair of said amplified signals and producing a
filtered data signal;
such that said signal processor provides in phase and quadrature phase
cross correlated data signals for quadrature modulation characterized by a
modulated signal suitable for amplification in linear and non-linear mode
and adaptable for conventional BPSK demodulation.
16. A quadrature architecture spectral and power efficient modem
comprising:
a splitter for receiving an input signal selected from the group of binary,
multi-level, and analog signals and combinations thereof and providing a
pair of identical data signals;
a signal processor including an in phase and quadrature phase channel each
receiving one of said pair of identical data signals, each of said
channels including
a delay element for receiving said one of said pair of identical data
signals and producing a delayed signal;
an amplifier for receiving said delayed signal and producing an amplified
data signal;
a filter for receiving said amplified signal and producing a filtered data
signal;
a quadrature modulator for receiving said filtered signals from each of
said channels and producing a modulated output signal; and
amplification means operated in non-linear mode for maximum power
efficiency receiving said modulated output signal and for transmitting a
band limited output signal with substantially limited spectral regrowth.
17. A quadrature architecture modem with out of band spectral density
attenuated at least 30 dB at 11 MHz away from the carrier frequency for an
11M-chip/sec system comprising:
a splitter for receiving an input signal selected from the group of binary,
multi-level, and analog signals and combinations thereof and providing a
pair of identical data signals;
a signal processor including an in phase and quadrature phase channel each
receiving one of said pair of identical data signals, each of said
channels including
a delay element for receiving said one of said pair of identical baseband
data signals and producing a delayed signal;
an amplifier for receiving said delayed signal and producing an amplified
data signal;
a filter for receiving said amplified signal and producing a filtered data
signal;
a quadrature modulator for receiving said filtered signals from each of
said channels and producing a modulated output signal; and
amplification means operated in non-linear mode for receiving said
modulated output signal and for transmitting a band limited output signal
with spectral regrowth limited to a 30 dB spectral density attenuation.
18. A quadrature architecture modem comprising:
a splitter for receiving an input signal selected from the group of binary,
multi-level, and analog signals and combinations thereof and providing a
pair of identical data signals;
a signal processor including an in phase and quadrature phase channel each
receiving one of said pair of identical data signals, each of said
channels including
a delay element for receiving said one of said pair of identical data
signals and producing a delayed signal;
an amplifier for receiving said delayed signal and producing an amplified
data signal;
a filter for receiving said amplified signal and producing a filtered data
signal;
a quadrature modulator for receiving said filtered signals from each of
said channels and producing a modulated output signal; and
amplification means operated in a non-linear saturation amplification mode
for maximum power efficiency receiving said modulated output signal and
for transmitting a band limited output signal with out-of-band spectral
density attenuated at least 30 dB at N Mhz away from the carrier frequency
for N Megachip/sec and N megabit/sec systems.
19. The structure as in claim 18 wherein N is an integer selected from the
group consisting of 1, 2, 4, 10, 11 and 22.
20. A cross correlated quadrature architecture signal processor for
producing cross correlated in phase and quadrature phase data streams for
modulation by a Quadrature Modulator and subsequent demodulation of the
quadrature modulated signal in digital, binary, multi-level or analog FM
systems comprising:
a variable gain element for reducing the modulation index of said
quadrature modulator, said variable gain element receiving an input signal
selected from the group of binary, multi-level, and analog signals and
combinations thereof and outputting an attenuated input signal;
a splitter for receiving said attenuated input signal and providing a pair
of identical data signals; and
a signal processor including an in phase and quadrature phase channel each
receiving one of said pair of identical data signals, each of said
channels including
a delay element for receiving said one of said pair of identical data
signals and producing a delayed signal;
a function generator for generating Cosine and Sine values for said delayed
signal and producing a shaped signal;
an amplifier for receiving said shaped signal and producing an amplified
data signal;
a filter for receiving said amplified signal and producing a filtered data
signal;
such that said signal processor provides in phase and quadrature phase
cross correlated data signals for quadrature modulation with a modulated
signal suitable for amplification in linear and non-linear mode.
21. A binary phase shift keyed quadrature cross coupled structure suitable
for linear and non-linear amplified system applications comprising:
a input port for receiving input data;
a splitter having an input coupled to said input port, and serving to split
said input data into in phase (I) and quadrature phase (Q) channel cross
coupled datastreams such that said I and Q datastreams are identical,
proportional in gain and phase to said input data; and
a signal processing network for receiving said I and Q channel datastreams
and providing cross-correlated processed in phase and quadrature phase
signals, said signal processing network including
a delay element for delaying one of said I and Q channel datastreams by a
selectable time delay;
amplifiers in the I and Q channel for providing gain adjusted datastreams;
and
filtering means for filtering said gain adjusted datastreams in the I and Q
channels such that said signal processor provides in phase and quadrature
phase cross correlated data signals for quadrature modulation with a
modulated signal suitable for amplification in linear and non-linear mode.
.
22. A structure as in claim 21 which further comprises a quadrature
modulator for receiving said processed in phase and quadrature phase cross
correlated data signals and providing a quadrature modulated output
signal.
23. A structure as in claim 21 which further comprises switching means for
disconnecting one of said in phase and quadrature phase cross correlated
data signals allowing for conventional BPSK, QPSK and offset QPSK
modulation.
24. A structure as in claim 21 in which said selectable time delay is one
half of a chip duration for a spread spectrum system and one half of a bit
duration for a non-spread spectrum system.
25. A Gaussian Filtered Frequency Shift Keyed (GFSK) quadrature cross
coupled structure suitable for linear and non-linear amplified system
applications comprising:
a input port for receiving input data;
a Gaussian lowpass filter and presetable gain integrator for processing
said input data and providing filtered input data;
a splitter having an input coupled to said input port, and serving to split
said filtered input data into in phase (I) and quadrature phase (Q)
channel cross coupled datastreams such that said I and Q datastreams are
identical, proportional in gain and phase to said input data; and
a signal processing network for receiving said I and Q channel datastreams
and providing processed in phase and quadrature phase signals, said signal
processing network including
a signal processor for varying the modulation index for said signal
processing network;
means for generating Cosine and Sine values for said I and Q channel
datastreams;
a delay element for delaying one of said I and Q channel datastreams by a
selectable time delay;
amplifiers in the I and Q channel for providing gain adjusted datastreams;
and
filtering means for filtering said gain adjusted datastreams in the I and Q
channels such that said signal processor provides in phase and quadrature
phase cross correlated data signals for quadrature modulation with a
modulated signal suitable for amplification in linear and non-linear mode.
.
26. The structure as in claim 25 wherein said signal processor is selected
from the group consisting of a filter, an integrator, and a signal level
and gain adjustor.
27. A frequency modulation pre-processor for multistate digital signals
suitable for linear and non-linear amplified system applications
comprising:
a input port for receiving input data;
a converter for converting said input data into a multilevel N level
datastream where N is an integer greater than 1;
a splitter having an input coupled to said input port, and serving to split
said multilevel N level datastream into in phase (I) and quadrature phase
(Q) channel cross coupled datastreams such that said I and Q datastreams
are identical, proportional in gain and phase to said multilevel N level
datastream; and
a signal processing network for receiving said I and Q channel datastreams
and providing cross-correlated processed in phase and quadrature phase
signals, said signal processing network including
a signal processor for varying the modulation index for said signal
processing network;
means for generating Cosine and Sine values for said I and Q channel;
a delay element for delaying one of said I and Q channel datastreams by a
selectable time delay;
amplifiers in the I and Q channel for providing gain adjusted datastreams;
and
filtering means for filtering said gain adjusted datastreams in the I and Q
channels such that said signal processor provides in phase and quadrature
phase cross correlated data signals for quadrature modulation with a
modulated signal suitable for amplification in linear and non-linear mode.
28. A frequency modulation pre-processor for digital signals suitable for
linear and non-linear amplified system applications comprising:
a input port for receiving digital input data;
a converter for converting said digital input data converting said digital
input signal into a predetermined coded, filtered and processed signal;
a splitter having an input coupled to said input port, and serving to split
said input data into in phase (I) and quadrature phase (Q) channel
cross-correlated datastreams such that said I and Q datastreams are
identical, proportional in gain and phase to said input data; and
a signal processing network for receiving said I and Q channel datastreams
and providing processed in phase and quadrature phase signals, said signal
processing network including
a signal processor for presetting the modulation index for said signal
processing network;
means for generating Cosine and Sine values for said I and Q channel
datastreams;
a delay element for delaying one of said I and Q channel datastreams by a
selectable time delay;
amplifiers in the I and Q channel for providing gain adjusted datastreams;
and
filtering means for filtering said gain adjusted datastreams in the I and Q
channels such that said signal processor provides in phase and quadrature
phase cross correlated data signals for quadrature modulation with a
modulated signal suitable for amplification in linear and non-linear mode.
29. The structure as in claim 28 wherein said signal processor is selected
from the group consisting of a filter, an integrator, a delay element, a
Cosine and Sine value generator and an amplifier and combinations thereof.
30. A frequency modulation pre-processor for analog signals suitable for
linear and non-linear amplified system applications comprising:
a input port for receiving analog input signal;
a splitter having an input coupled to said input port, and serving to split
said input signal into in phase (I) and quadrature phase (Q) channel cross
coupled signal streams such that said I and Q signal streams are
identical, proportional in gain and phase to said input signal; and
a signal processing network for receiving said I and Q channel signal
streams and providing cross-correlated processed in phase and quadrature
phase signals, said signal processing network including
a delay element for delaying one of said I and Q channel signal streams by
a selectable time delay;
amplifiers in the I and Q channel for providing gain adjusted signal
streams; and
filtering means for filtering said gain adjusted signal streams in the I
and Q channels such that said signal processor provides in phase and
quadrature phase cross correlated signals for quadrature modulation with a
modulated signal suitable for amplification in linear and non-linear mode. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to signal processors and particularly to
crosscoupled signal processors for increasing the spectral and power
efficiency of modulated NRZ (non return to zero) signals, of digital
multilevel and of analog modulated signals in power efficient
partly-linearized and nonlinearly amplified systems. Crosscoupled binary,
quadrature phase, frequency and amplitude modulated systems are described.
BACKGROUND
In radio, infrared, cable, fiber optics and practically all communication
transmission systems, power and spectral efficiency combined with robust
bit error rate (BER) performance in a noisy and/or strong interference
environment is a most desirable system requirement. Robust BER performance
is frequently expressed in terms of the BER as a function of Energy per
Bit (E.sub.b) divided by Noise Density (N.sub.o), that is, by the
BER=f(E.sub.b /N.sub.o) expression. Cost, reduced size, compatibility and
interoperability with other conventional or standardized systems is highly
desired. Several recently-developed draft standards have adopted
modulation techniques such as conventional binary phase shift keying
(BPSK), quadrature phase shift keying (QPSK), and .pi./4-QPSK techniques
including differential encoding variations of the same. For
spectrally-efficient (i.e. bandlimited) signalling, these conventional
methods exhibit a large envelope fluctuation of the modulated signal, and
thus a large increase in peak radiation relative to the average radiated
power. Within the present state of the art, for numerous transmitter
applications, it is not practical to introduce bandpass filtering after
the radio frequency (RF) final amplifier stage. Here we are using the term
"radio frequency" in its broadest sense, implying that we are dealing with
a modulated signal. The RF could be, for example, as high as the frequency
(inverse of the wavelength) of infrared or fiber optic transmitters, it
could be in the GHz range, e.g., between 1 GHz and 100 GHz, or it could be
in the MHz range or just in the kHz range.
In conventional BPSK and differentially-encoded phase-shift keying systems
such as DBPSK and DQPSK, large envelope fluctuations require linearized or
highly linear transmitters including upconverters and RF power amplifiers
and may require expensive linear receivers including linear automatic gain
control (AGC) circuits. A transmitter nonlinear amplifier (NLA) reduces
the time domain envelope fluctuation of the bandlimited signal and this
reduction of the envelope fluctuation, being a signal distortion, is the
cause of spectral restoration or spectral regrowth and the cause of
unacceptable high levels of out-of-band spectral energy transmission, also
known as out-of-band interference. Additionally, for conventional BPSK,
QPSK, and also QAM (Quadrature Amplitude Modulation) signals, in phase
channel (I) to quadrature channel (Q) crosstalk is generated which
degrades the BER=f(E.sub.b /N.sub.o) performance of the modulated radio
transmitter.
Experimental work, computer simulation, and theory documented in many
recent publications indicates that for bandlimited and standardized BPSK,
QPSK, .pi./4-QPSK, and QAM system specifications, a highly linear
amplifier is required to avoid the pitfalls of spectral restoration and of
BER degradation. Linearized or linear amplifiers are less power efficient
(during the power "on" state, power efficiency is defined as the transmit
RF power divided by DC power), considerably more expensive and/or have
less transmit RF power capability, are larger in size, and are not as
readily available as NLA amplifiers. As an illustrative example of
technology achievements on two recently-released radio frequency
integrated circuit (RFIC) amplifiers, we measured a maximum possible
output power of 18 dBm in a linear mode of operation and as much as 24 dBm
in a nonlinear or saturated mode of operation practically with the same DC
current and DC power requirement at 2.4 GHz (Minicircuits amplifier MRFIC
2403). The RF power to DC drive power ratio, which is a practical measure
of power-efficiency of an RF output stage, was doubled in the saturated
mode. The reduced linearly amplified output power of 18 dBm is required to
meet the stringent spectral efficiency requirements of the IEEE 802.11
direct sequence spread spectrum draft standard for conventional DBPSK and
DQPSK operation, as depicted in FIG. 1. From FIG. 1 note that the linearly
amplified filtered BPSK signal could meet the spectral specifications of
this 11M chip/second system. The nonlinearly amplified, filtered BPSK of
the prior art does not meet the specifications. The power efficiency (RF
power to DC power ratio) of these systems in the "on" mode with linear
low-cost commercial amplifiers driven by a 3V battery was found to be as
low as 10%.
In an extremely critical power-efficient requirement such as all wireless
and cellular telephones, computers, and other devices, it is very wasteful
to operate at such low power efficiency, which leads to frequent
replacement of the battery. The so-called "talk time" is not efficient
with these very-recently standardized IEEE 802.11 modulated conventional
BPSK and DQPSK systems. As a specific example, the out-of-band power
spectral density is specified by the IEEE 802.11 US and international
standard to be attenuated at least 30 dB at 11 MHz away from the carrier
frequency for an 11M-chip/sec System as illustrated in FIG. 1, by the
shaded area of specification limits. In simple modulated signal terms the
11 M-chip/sec rate is similar to an 11M-chip/sec DBPSK modulator. To
satisfy this 30 dB out-of-band spectral density requirement, an "output
backoff" (OBO) of the RF amplifiers of 4 dB to 6 dB is required. See K.
Feher, "Wireless Digital Communications: Modulation and Spread Spectrum
Techniques," book, Prentice Hall, 1995, and H. Mehdi, K. Feher, "FBPSK,
Power and Spectrally Efficient Nonlinearly Amplified (NLA) Compatible BPSK
Modems for Wireless LAN" submitted to RF Expo 95 San Diego proceedings to
be published, March 1995 and H. Mehdi, K. Feher, "FQPSK, Power and
Spectral Efficient Family of Modulations For Wireless Communication
System." Proceeding IEEE-VTC-94, June 94, FIG. 2a depicts DBPSK modulation
utilizing an amplifier (MRFIC 2403 available from Motorola) with an output
power of approximately 18.5 dBm, which is linearly amplified with an
output-backoff (OBO) of 5 dB.
FIG. 2b depicts a pre-modulation filtered conventional DBPSK signal
operated at saturation at approximately 24 dBm, in which spectral
restoration is evident. In FIG. 2c, the FBPSK modulated signal power is 24
dBm at full saturation, with 0 dB OBO. The term OBO is for the output
power reduction required from the maximal or saturated output power of the
amplifier. In this case saturated output power corresponds to 24 dBm while
the 6 dB OBO reduces the output power from 24 dBm to only 18 dBm. The DC
power consumption of the evaluated RF devices did not change significantly
between the saturated full-output RF power and the 6 dB OBO reduced-output
power. Thus if we could have a modulated system which could operate at
full saturation of 24 dBm and meet the standardization requirements and
specifications we could achieve approximately a 6 dB (400%) increased
output power. Thus a modulation technique which could attain 24 dBm from
existing RF devices and meet the standardized system specifications as
well as the desired compatibility with conventional standardized BPSK or
QPSK systems would be very attractive. To put things even more into
perspective for this illustrative application, at 2.4 GHz FCC Part 15
permits transmission of 1 watt=+30 dBm transmit power. The IEEE 802.11
Standardization Committee specifies the same +30 dBm maximal output power.
In a strongly interference polluted environment of the unregulated FCC-15
band it is very desirable to transmit the strongest possible and permitted
RF signal in order to achieve good performance and the best possible
coverage. With conventional BPSK modulators (such as specified by IEEE
802.11) utilizing linearly operated amplifier devices (such as a MRFIC
2403 amplifier available from Motorola) the practical achievable limit of
output power is around +18 dBm to 20 dBm, which is about 10 dB less than
permitted by the FCC and the IEEE standard. Thus, due to technology
limitations, conventional modems must operate at an approximately 10 dB
lower linearly amplified output power than permitted by FCC and allowed by
the IEEE specification, for best performance.
SUMMARY OF THE INVENTION
The present invention avoids the tremendous technological gap between RF IC
amplifiers and their use in, for example, PCMCIA (credit card sized 3V)
system specifications. This invention alleviates the above weaknesses of
wireless systems such as illustrated above for the 2.4 GHz band
application. Similar advantages are obtained also for infrared and many
other transmission systems. This invention presents the technology,
method, structure, and functions to implement spectrally and power
efficient crosscoupled Quadrature BPSK, QPSK, QAM, and FM systems such as
nonlinearly amplified fully-saturated BPSK, which we call Feher's BPSK
(FBPSK). The present invention teaches that FBPSK can operate with linear,
partly nonlinear, and completely nonlinear amplified systems such as class
C Or other classes of amplifiers and devices as well as nonlinear
receivers. The FBPSK system of this invention has a tremendous power
efficiency advantage over conventional BPSK and QPSK systems and retains
the spectral efficiency and robust bit rate performance advantages of
linearly amplified PSK systems. An additional advantage of FBPSK is that
it is fully compatible and interoperable with some of the preliminary
draft-standardized systems such as the IEEE 802.11 BPSK-based
direct-sequence spread spectrum system. For practically the same cost
power requirement, size, power dissipation, and bit error rate performance
as the standardized BPSK, the present invention provides an approximately
400% (6 dB) output power advantage over the present state of the art, for
comparable spectral efficiency. With the knowledge that 1 dB increase in
RF power of 3V driven integrated circuits results in many millions of
dollars of added R&D costs, this invention discloses a significant
pioneering technology which will lead to considerably better performance
and lower cost wireless and other communications, broadcast, consumer
electronics, and variety of other applications which may include
television, VCR remote applications, radio-controlled home security,
medical uses, etc.
Health hazard caused by radio waves has been a recently-documented concern
in the US and internationally. The FBPSK invention reduces the peak
radiation of conventional BPSK by 6 dB to 9 dB which corresponds to two to
three times reduction of peak radiation with the same average power as
conventional BPSK. At this point in time medically it has not been proven
that increased peak radiation is or could be truly harmful. However, even
intuitively, it is apparent that given that in the prior art we transmit,
say an average 1W power at 900 MHz and that the peak power of such a DBPSK
signal would be 3W peak, while that of our invention having the same 1W
average power would reduce the peak radiation to 1W. Thus in this
illustrative case FBPSK reduces peak radiation threefold. Deployment of
FBPSK instead of its compatible BPSK at the same average power authorized
by FCC reduces the peak radiation of potentially millions of systems. It
is believed that the reduction of peak radiation is a very important
potential human health hazard reduction of which communications engineers
and implementers should be aware.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a graph depicting computer simulated power spectral density of
bandlimited BPSK linearly amplified, BPSK nonlinearly amplified, and the
novel FBPSK nonlinearly amplified signal of this invention, together with
an indication of the spectral efficiency requirements of the IEEE 802.11
standard;
FIG. 2a depicts linearly amplified DBPSK modulation of the prior art
utilizing 5 dB OBO;
FIG. 2b depicts an output signal of prior art nonlinearly amplified DBPSK;
FIG. 2c depicts an FBPSK modulated nonlinearly amplified signal with 0 dB
OBO in accordance with one embodiment of this invention;
FIG. 3a is a diagram depicting one embodiment of the structure constructed
in accordance with the teachings of this invention;
FIG. 3b is a diagram depicting one embodiment of baseband processing
circuitry 103 of FIG. 3a;
FIG. 3c is a block diagram depicting one embodiment of a splitter circuit
suitable for use as splitter 102 of FIG. 3a;
FIGS. 4 and 5 are constellation diagrams depicting the output signal
obtained from one embodiment of this invention;
FIG. 6a depicts a NRZ data signal before and after input to the FBSK
processor according to one embodiment of the present invention;
FIG. 6b illustrates the crosscoupled binary data fed into the I and Q
quadrature modulators of the present invention;
FIG. 7a is an eye diagram obtained from one embodiment of this invention;
FIG. 7b are I and Q baseband eye diagrams obtained from one embodiment of
this invention;
FIG. 8 is a block diagram of one embodiment of a FBPSK/BPSK modem and test
set-up according to the teachings of this invention;
FIG. 9 is a diagram depicting one embodiment of a modulator suitable for
use as modulator 85 of FIG. 8;
FIG. 10 is a graph displaying the FPBSK and BPSK output spectra of the
embodiment of FIG. 8;
FIG. 11 is a graph depicting the 70 MHz spectral component provided by
frequency doubler 95 of FIG. 8;
FIG. 12 is a block diagram depicting one embodiment of a PLL suitable for
use as PLL 96 of FIG. 8;
FIG. 13 is a graph depicting the recovered 70 MHz carrier signal available
as an output from PLL 96 of FIG. 8;
FIG. 14 is a diagram depicting one embodiment of a divide by two circuit
suitable for use as divided by two circuit 97 of FIG. 8;
FIG. 15 is a diagram depicting one embodiment of a 35 MHz demodulator
suitable for use as demodulator 98 of FIG. 8;
FIG. 16 is a graph depicting the BER performance of linear and nonlinear
BPSK modulation utilizing the embodiment of FIG. 8; and
FIG. 17 is a diagram depicting one embodiment of this invention suitable
for use in analog or digital FM, phase modulation (PM or PSK) and QAM
quadrature cross-correlated modulation utilizing either linear or
nonlinear amplification.
DETAILED DESCRIPTION
In general the present invention is a signal processor-filter having an
input for receiving one or more input signals and providing one or more
output signals which are cross coupled. The signal processor includes
signal coupling between the in-phase and quadrature output signals of the
baseband I and Q drive signals with means for generating BPSK, QPSK,
Frequency Modulated (FM) and Quadrature Amplitude Modulated (QAM) digital
and analog signals through a quadrature structure which is suitable for
nonlinear amplification and demodulation by a conventional compatible BPSK
demodulator or by coherent and noncoherent FM or QAM demodulators. In one
of the specific embodiments, a digital communications application for
nonlinearly amplified BPSK is illustrated, however the present invention
is suitable for use with quadrature amplitude modulation (QAM), quadrature
phase shift keying (QPSK), frequency shift keying (FSK), Gaussian FSK
(GFSK), Gaussian Minimum Shift keying (GMSK), multilevel digital FM and
many other digital as well as analog modulation systems. One of the first
and simplest embodiments is for nonlinearly amplified BPSK which we call
Feher's BPSK (FBPSK) .
In this embodiment we refer to FIG. 3a in which an input binary data stream
having an NRZ data format is received on lead 101 and split into the I and
Q channels by splitter 102, and fed to baseband processing circuitry 103.
Splitter 102 combined with baseband processors 103 provides crosscoupling
and filtering between the I and Q channels. By this architecture and by
connection of baseband processor 103 to quadrature modulator 104 a
QPSK-like signal is attained, however the information content is that of
BPSK. FIG. 4 and FIG. 5 show the "binary" constellation diagrams obtained
by this configuration. FIG. 6a shows the NRZ datastream and FBPSK
processed initial signal while FIG. 6b shows the crosscoupled binary data
fed into the I and Q quadrature modulators. FIG. 7a illustrates the binary
BPSK eye diagram obtained at the output of a conventional BPSK
demodulator, and FIG. 7b depicts the in phase(I) and quadrature (Q)
demodulated eye diagrams.
In one embodiment, as depicted in FIG. 3b, baseband processing circuitry
103 is shown with input signal splitter 102 (FIG. 3) and circuitry 103
includes, delay elements 132I and 132Q, amplifiers 133I and 133Q, and
filters 134I and 134Q, as well as a second cross coupler 135. In the
preferred embodiment, elements 102, 103 and 135 are symmetrical, but may
be asymmetrical as required for a given application. In one embodiment,
baseband processor 103 provides a delay of half a bit period in the Q
channel and no delay in the I channel, that is d.sub.Q =T.sub.b /2, and
the I channel and Q channel NRZ signals, which are identical to the input
NRZ signal, are filtered by the same type of filters 134I and 134Q. In one
embodiment, these filters are simple lowpass filters having a 3 dB
attenuation frequency close to the Nyquist frequency. For an f.sub.b =1
Mb/s example, the 3 dB attenuation of these filters is a variable
typically between 100 kHz and 900 kHz, depending on particular system
spectral efficiency, degradation budget allowance, and power efficiency
requirements. Thus the output signals of baseband processor 103 of FIG. 3a
(the I and Q drive signals to quadrature modulator 104) are offset by a
delay which could be, for example d.sub.2 =0.5*T.sub.b. This setup is in
appearance similar to conventional offset QPSK (OQPSK) with the important
distinction being that in OQPSK the I channel and Q channel drive signals
are independent (not correlated) bit streams obtained at the outputs of
Parallel to Serial (P/S) converters while in the present invention the
same input data is split (coupled) prior to any baseband processing to
form the so-called I and Q channels of data. Thus, in accordance with this
invention, the I and Q signals are crosscoupled. In contrast, a
conventional BPSK mod | | |
