A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal. The encoder provides a "systematic" encoding scheme in which for many code strings the encoded bits are the same as the input bits used to generate the encoded bits. This systematic approach of the present invention provides an encoder that is easy to implement because a majority of the bits directly "feed through" and non-trivial logic circuits are only needed to generate the control bits. The systematic encoding also dictates a decoder that is likewise easy to construct and can be implemented in a circuit that simply discards the control bit. The encoder preferably comprises a serial-to-parallel converter, a code generator, and a parallel-to-serial converter. The code generator produces a rate 16/18 or 16/17 code. The present invention also includes a method that is directed to encoding bit strings and comprises the steps of: 1) converting the input strings to input bits, and 2) adding at least one bit to produce an encoded string with many ones and a Hamming distance greater than one after precoding.

A data detection apparatus retrieved binary data modulated in conformity with the (d, k) constraint from an analog signal includes a timing extracting unit for generating a timing signal representing the timing at which the analog signal crosses the threshold value, a clock generating unit for generating a clock signal having a cycle corresponding to one bit of the binary data from the timing signal, a timing position detector for detecting the position in the cycle of the timing, and an error correcting unit for correcting an error in the binary data in accordance with the detected position.

A combined channel and entropy decoder is provided that achieves a significant bit-error rate improvement using likelihood values (61) instead of conventional bits. The likelihood values are stored in a buffer (62). A unique code-word is searched in the bit pattern or in the likelihood value. When a unique code-word is found at the identifier (63), candidate code-words are loaded into computation units where each unit computes code-word likelihood for a given code-word bit pattern. The code-word likelihood values are compared and the selected code information is fed back to the code-word controller 67 to proceed to the next-step decoding.

Even if an element such as a ROM is not used, a code reverse conversion can be realized by a sufficiently small scale circuit to be effective for integration. When code data group converted from 8-bit to 15-bit according to a predetermined rule is converted to original 8-bit code data group, an exclusive logic processor 11, a bit shift processor 12, a six-to-four decoder and an eleven-to-eight decoder 14 divides the 15(m) bit code (dividing by m at the maximum) into a plurality of areas, converts "1" (in the case of positive logic) in response to the generated bit position in the respective areas, and the numeric codes obtained by the numeric value converting means are added by an adder 15.

Disclosed is an error tolerant binary encoded synchronization mark concatenated with a known pattern, such as a VFO pattern, comprising an encoded pattern of a fixed plurality of bits, the encoded synchronization pattern being at maximum Hamming distance from the concatenated known pattern for the number of bits in the fixed plurality of bits. The error tolerant synchronization mark may also be concatenated with the VFO pattern seen in reverse, and the synchronization pattern additionally is at maximum Hamming distance from the concatenated known VFO pattern seen in reverse.