WikiPatents - Community Patent Review
Create Free Account  |  License or Sell Your Patent  |  WikiPatents Marketplace  |  WikiPatents Blog
Username:  Password:  
    
Advanced Search
Method of fabricating semiconductor device and method of processing substrate    
United States Patent5492843   
Link to this pagehttp://www.wikipatents.com/5492843.html
Inventor(s)Adachi; Hiroki (Kanagawa, JP); Goto; Yuugo (Kanagawa, JP); Zhang; Hongyong (Kanagawa, JP); Takayama; Toru (Kanagawa, JP)
AbstractMethod of fabricating a semiconductor device. A glass substrate such as Corning 7059 is used as a substrate. A bottom film is formed. Then, the substrate is annealed above the strain point of the glass substrate. The substrate is then slowly cooled below the strain point. Thereafter, a silicon film is formed, and a TFT is formed. The aforementioned anneal and slow cooling reduce shrinkage of the substrate created in later thermal treatment steps. This makes it easy to perform mask alignments. Furthermore, defects due to misalignment of masks are reduced, and the production yield is enhanced. In another method, a glass substrate made of Corning 7059 is also used as a substrate. The substrate is annealed above the strain point. Then, the substrate is rapidly cooled below the strain point. Thereafter, a bottom film is formed, and a TFT is fabricated. The aforementioned anneal and slow cooling reduce shrinkage of the substrate created in later thermal treatment steps. Thus, less cracks are created in the active layer of the TFT and in the bottom film. This improves the production yield. During heating of the substrate, it is held substantially horizontal to reduce warpage, distortions, and waviness of the substrate.
   














 Title Information Submit all comments and votes
 
Patent Text Patent PDF Print Page Summary File History
Plain text PDF images Print Summary File History
Drawing from US Patent 5492843
Method of fabricating semiconductor device and method of processing

     substrate - US Patent 5492843 Drawing
Method of fabricating semiconductor device and method of processing substrate
Inventor     Adachi; Hiroki (Kanagawa, JP); Goto; Yuugo (Kanagawa, JP); Zhang; Hongyong (Kanagawa, JP); Takayama; Toru (Kanagawa, JP)
Owner/Assignee     Semiconductor Energy Laboratory Co., Ltd. (Kanagawa, JP)
Patent assignment
All assignments
Publication Date     February 20, 1996
Application Number     08/282,598
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     July 29, 1994
US Classification     438/479 117/8 117/106 148/DIG.16 257/E21.119 257/E21.413 257/E21.703 438/166 438/486 438/974
Int'l Classification     H01L 021/84 H01L 021/324
Examiner     Hearn; Brian E.
Assistant Examiner     Radomsky; Leon
Attorney/Law Firm     Ferguson, Ferguson, Jr.; Gerald J. Sixbey, Friedman, Leedom &
Address
Parent Case    
Priority Data     Jul 31, 1993[JP]5-209053 Jul 31, 1993[JP]5-209055 Sep 20, 1993[JP]5-256569
USPTO Field of Search     437/248 437/40 437/41 437/21 437/101 437/173 437/174 437/907 437/909 65/117 65/41 117/94 117/106 148/DIG. 16 148/DIG. 90
Patent Tags     fabricating semiconductor processing substrate
   
Enter a comma (,) or semicolon (;) between multiple tag words/phrases.
Describe this patent:
 Amusing   
 Clever   
 Complex   
 Efficient   
 Historic   
 Important   
 Innovative   
 Interesting   
 Practical   
 Simple   
[no votes]
Patent WIKI

Share information and news about this patent, including information and news about the technology, inventors, company, ligation and licensing.

 References Submit all comments and votes
 
*references marked with an asterisk below are user-added references
 U.S. References
 
Add a new US reference:  
ReferenceRelevancyCommentsReferenceRelevancyComments
3250605



[0 after 0 votes]
5426064
Zhang
438/166
Jun,1995

[0 after 0 votes]
5403772
Zhang
438/166
Apr,1995

[0 after 0 votes]
5308998
Yamazaki
257/57
May,1994

[0 after 0 votes]
5306651
Masumo
438/166
Apr,1994

[0 after 0 votes]
5297956
Yamabe

Mar,1994

[0 after 0 votes]
5294238
Fukada
65/60.2
Mar,1994

[0 after 0 votes]
5275851
Fonash
438/479
Jan,1994

[0 after 0 votes]
5262654
Yamazaki
257/53
Nov,1993

[0 after 0 votes]
5254208
Zhang
438/479
Oct,1993

[0 after 0 votes]
5252140
Kobayashi
136/258
Oct,1993

[0 after 0 votes]
5147826
Liu
438/486
Sep,1992

[0 after 0 votes]
5112764
Mitra
438/163
May,1992

[0 after 0 votes]
5064775
Chang

Nov,1991

[0 after 0 votes]
4977748
Diedrich
62/51.1
Dec,1990

[0 after 0 votes]
4894080
Reese
65/106
Jan,1990

[0 after 0 votes]
4851363
Troxell
438/151
Jul,1989

[0 after 0 votes]
4709466
McCandless
438/94
Dec,1987

[0 after 0 votes]
4547256
Gurtler
438/535
Oct,1985

[0 after 0 votes]
4152535
Deminet
136/258
May,1979

[0 after 0 votes]
 Foreign References
 Other References
 Market Review Submit all comments and votes
   
Market Size
Estimate the gross annual revenues of the relevant market sector:
> $10B
$5B - $10B
$2B - $5B
$500M - $2B
$100M - $500M
$10M - $100M
$1M - $10M
$500K - $1M
$100K - $500K
< $100K
[No votes]
$0
 
$0   $2.5B   $5B   $7.5B   $10B
Market Share
Estimate the percentage of the relevant market sector this invention will capture:
75% - 100%
50% - 74.99%
25% - 49.99%
10 - 24.99%
5 - 9.99%
2 - 4.99%
1 - 1.99%
< 1%
[No votes]
0.0%
 
0%   25%   50%   75%   100%
Reasonable Royalty
What percentage of gross sales should the inventor or assignee be paid?
75% - 100%
50% - 74.99%
25% - 49.99%
10 - 24.99%
5 - 9.99%
2 - 4.99%
1 - 1.99%
< 1%
[No votes]
0.0%
 
0%   25%   50%   75%   100%
Public's "Guesstimation" of Royalty Value
Market SizeN/A[No votes]
xMarket ShareN/A[No votes]
xReasonable RoyaltyN/A[No votes]

N/A

License Availablity
If you are NOT the owner or assignee, answer here:
Yes, license is available for purchase

No, license is not currently available



[No votes]
License Availablity
If you ARE the owner or assignee, answer here:
Yes, license is available for purchase

No, license is not currently available



[No votes]
Competitive Advantage
Does this invention have a significant competitive advantage over similar technologies?
Yes

No



[No votes]
Most helpful competitive advantage comment
[No comments]

Commercial Alternatives
Are there viable commercial alternatives for this invention?
Yes

No



[No votes]
Most helpful commercial alternative comment
[No comments]

 Technical Review Submit all comments and votes
 Claims Submit all comments and votes
 


What is claimed is:

1. A method of fabricating a semiconductor device, comprising the steps of:

forming a bottom film on a glass substrate having a strain point;

thermally annealing said glass substrate at a first temperature higher than said strain point of said glass substrate after said bottom film forming step;

cooling said substrate from said first temperature to a second temperature lower than said strain point at a rate of less than 2.degree. C./min;

forming a semiconductor film comprising silicon on said bottom film; and

thermally annealing said substrate at a third temperature not exceeding said strain point of the glass substrate after said semiconductor film forming step,

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

2. The method of claim 1 wherein at least one patterning step is carried out between said step of forming a silicon film on said bottom film and said step of thermally annealing said substrate at a third temperature.

3. The method of claim 1 wherein a metal element for promoting crystallization is intentionally added to said silicon film.

4. The method of claim 1 wherein said bottom film comprises a silicon oxide layer, a silicon nitride layer, an aluminum nitride layer or a multi-layer thereof formed by plasma-assisted CVD.

5. The method of claim 1 wherein said step of thermally annealing said glass substrate at a first temperature higher than said strain point of said glass substrate is carried out in an oxidizing ambient or a nitriding ambient.

6. The method of claim 1 wherein said thermally annealing step at said third temperature is carried out by a lamp annealing using visible or near infrared light.

7. The method of claim 1 wherein said thermal annealing step at said third temperature is carried out by a laser.

8. The method of claim 1 wherein said thermally annealing step at said third temperature is carried out by thermal and laser energies.

9. A method of fabricating a semiconductor device comprising the steps of:

forming a bottom film on a glass substrate having a strain point;

thermally annealing said glass substrate at a first temperature higher than said strain point of said glass substrate after said bottom film forming step;

cooling said substrate from said first temperature to a second temperature lower than said strain point at a rate of less than 2.degree. C./min;

forming a non-single crystal semiconductor film comprising silicon on said bottom film;

selectively providing in contact with said semiconductor film a catalytic element which promotes crystallization of said semiconductor film;

thermally annealing said substrate at a temperature less than said strain point of said glass substrate and within a range from a temperature 30.degree. C. lower than a crystallization temperature of said semiconductor film to a temperature 30.degree. C. higher than said crystallization temperature;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

10. The method of claim 9 wherein said thermally annealing step at said temperature less than said strain point is carried out by a lamp annealing using visible or near infrared light.

11. The method of claim 9 wherein said thermally annealing step at said temperature less than said strain point is carried out by a laser.

12. The method of claim 9 wherein said thermally annealing step at said temperature less than said stain point is carried out by thermal and laser energies.

13. A method of fabricating a semiconductor device comprising the steps of:

forming a bottom film on a glass substrate having a strain point;

thermally annealing said glass substrate at a first temperature higher than said strain point after said bottom film forming step to shrink said glass substrate 1000 ppm or more;

forming a non-single crystal semiconductor film comprising silicon on said bottom film;

selectively providing in contact with said semiconductor film a catalytic element which promotes crystallization of said semiconductor film; and

crystallizing said non-single crystal semiconductor film from a location of said catalytic element by thermal annealing at a temperature less than said strain point of the glass substrate;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

14. The method of claim 13 wherein said crystallizing step is carried out by said thermal annealing and a laser annealing of said non-single crystal semiconductor film after said thermal annealing.

15. The method of claim 13 wherein said crystallizing step is carried out by said thermal annealing and an annealing of said non-single crystal semiconductor film by a visible or near infrared light after said thermal annealing.

16. A method of fabricating a semiconductor device comprising the steps of:

preparing a glass substrate having a strain point;

thermally annealing said glass substrate at a first temperature higher than said strain point of said glass substrate;

cooling said substrate from said first temperature to a second temperature lower than said strain point at a rate of less than 2.degree. C./min;

forming a bottom film on said substrate after said cooling step;

forming a non-single crystal semiconductor film comprising silicon on said bottom film; and

heat-treating said substrate and said semiconductor film at a third temperature not higher than said strain point of the glass substrate;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

17. The method of claim 16 wherein said semiconductor film comprises silicon.

18. The method of claim 16 wherein at least one patterning step is carried out between said step of forming a bottom film on said substrate at a third temperature.

19. The method of claim 17 wherein a metal element for promoting crystallization is intentionally added to said silicon film.

20. The method of claim 16 wherein said bottom film comprises a silicon oxide layer, a silicon nitride layer, an aluminum nitride layer or a multi-layer thereof formed by plasma-assisted CVD.

21. A method of fabricating a semiconductor device comprising the steps of:

thermally annealing a glass substrate at a first temperature higher than a strain point of said glass substrate;

forming a bottom film on said glass substrate after said thermally annealing step;

cooling said substrate from said first temperature to a second temperature lower than said strain point at a rate of less than 2.degree. C./min;

forming a non-single crystal semiconductor film comprising silicon on said bottom film;

selectively providing in contact with said semiconductor film a catalytic element which promotes crystallization of said semiconductor film; and

thermally annealing said substrate at a temperature less than said strain point of said glass substrate and with a range from a temperature 30.degree. C. lower than a crystallization temperature of said semiconductor film to a temperature 30.degree. higher than said crystallization temperature;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

22. The method of claim 21 wherein said thermally annealing step at said temperature less than said stain point is carried out by a lamp annealing using visible or near infrared light.

23. The method of claim 21 wherein said thermally annealing step at said temperature less than said stain point is carried out by a laser.

24. The method of claim 21 wherein said thermally annealing step at said temperature less than said strain point is carried out by thermal and laser energies.

25. A method of fabricating a semiconductor device comprising the steps of:

thermally annealing a glass substrate at a first temperature higher than a strain point of said glass substrate to shrink said glass substrate;

forming a bottom film on said glass substrate after said thermally annealing step;

forming a non-single crystal semiconductor film comprising silicon on said bottom film;

selectively or wholly providing in contact with said semiconductor film a catalytic element which promotes crystallization of said semiconductor film; and

crystallizing said semiconductor film from a location of said catalytic element by thermal annealing at a temperature less than said strain point of the glass substrate;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

26. A method of heat-treating a substrate, comprising the steps of:

heating said substrate at a temperature greater than the strain point of the substrate while holding said substrate substantially within .+-.30.degree. from horizontal;

cooling said substrate at a rate of 2.degree. C./min or less;

forming a buffer layer on said substrate after said cooling step; and

forming a semiconductor film comprising silicon on said buffer layer; and

processing said semiconductor film at a temperature less than said strain point;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

27. The method of claim 26 wherein said substrate is held substantially horizontal.

28. The method of claim 26 wherein said substrate is made of glass having a strain point, and wherein said substrate is heated above said strain point.

29. The method of claim 26 wherein said buffer layer is a film of silicon oxide.

30. The method of claim 26 further comprising the step of cooling said substrate at a rate of 0.1.degree. to 0.5.degree. C./min in an ambient of nitrogen, ammonia, dinitrogen monoxide or oxygen stream after said step of heating said substrate to shrink said substrate.

31. The method of claim 26 wherein said substrate is made of glass, and wherein said semiconductor film is formed as said semiconductor film over said glass substrate with a buffer layer interposed therebetween.

32. The method of claim 31 wherein said silicon film is doped with an impurity for promoting crystallization and is crystallized by being heated.

33. The method of claim 26 wherein a silicon film in the form of an island is formed on said substrate.

34. The method of claim 26 wherein said semiconductor film is formed over said substrate made of glass with a buffer layer interposed therebetween, and wherein a thin-film transistor is formed, using said semiconductor film.

35. The method of claim 26 wherein a silicon film in the form of an island is formed on said substrate, and wherein said step of processing said substrate is carried out in an oxidizing ambient to form an oxide film on said silicon film.

36. A method of heat-treating a substrate comprising:

a first step of heating said substrate at a first temperature greater than the strain point of the substrate while holding said substrate substantially horizontal;

a second step of heating said substrate at a second temperature lower than said first temperature after said first step;

cooling said substrate at a rate of 10.degree. to 300.degree. C./min at least through said strain point of said substrate;

forming a bottom film on said substrate after said cooling step; and

forming a non-single crystal semiconductor film comprising silicon on said bottom film; and

processing said semiconductor film at a temperature less than said strain point;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

37. A method of fabricating a semiconductor device on a glass substrate, comprising the steps of:

heat-treating said glass substrate at a temperature higher than the strain point of the glass substrate while holding said substrate substantially within .+-.30.degree. from horizontal prior to formation of said semiconductor device; and

cooling said glass substrate at a rate of 0.01.degree. to 2.degree. C./min in an ambient of nitrogen, ammonia, or dinitrogen monoxide while holding said substrate substantially horizontal;

forming a bottom film on said glass substrate after said cooling step;

forming a non-single crystal semiconductor film on said bottom film; and

processing the semiconductor film at a temperature less than the strain point of the glass substrate;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

38. The method of claim 37 wherein said substrate is held substantially horizontal.

39. A method of processing a substrate comprising the steps of:

heat-treating a substrate made of glass at a temperature higher than the strain point of the glass;

cooling said substrate at a rate of 0.01.degree. to 2.degree. C./min after said heat-treating step;

forming a buffer film on said substrate after said cooling step;

forming a non-single crystal semiconductor film comprising silicon on said glass substrate after said cooling step;

selectively or wholly providing in contact with said semiconductor film a catalytic element which promotes crystallization of said semiconductor film before or after said non-single crystal semiconductor film forming step;

heat-treating said substrate together with said semiconductor film to crystallize said semiconductor film at a temperature less than said strain point;

wherein all steps subsequent to said semiconductor film forming step are performed at a temperature less than said strain point.

40. The method of claim 39 wherein during said steps of heat-treating said substrate, said substrate is held substantially horizontal or within .+-.30 degrees from horizontal.

41. The method of claim 39 further comprising the step of cooling said substrate together with said crystallized silicon film at a rate exceeding 2.degree. C./min.
 Description Submit all comments and votes
 


FIELD OF THE INVENTION

The present invention relates to a method of fabricating a semiconductor device such as a thin-film transistor (TFT) or a thin-film diode (TFD) on an insulating substrate made of glass, for example, or on various other substrates. The invention also relates to a method of fabricating a thin-film integrated circuit utilizing such devices and, more particularly, to a method of fabricating a thin-film integrated circuit for an active-matrix liquid crystal display.

BACKGROUND OF THE INVENTION

A thin-film transistor (TFT)is known as a thin-film semiconductor device fabricated on a glass substrate. TFTs formed on such a glass substrate are disposed in a pixel driver portion and also in a peripheral circuit for a liquid crystal display and are used to display images with high information content. Furthermore, these TFTs are employed in image sensors and in other integrated circuits.

Where a glass substrate is used, the following advantages can be derived:

(1) Since it is optically transparent to visible light, the glass substrate can be easily utilized in an apparatus such as a liquid crystal display through which light is transmitted.

(2) It is inexpensive.

However, the upper limit of the thermal treatment temperature is restricted by the heatproofness, i.e., the maximum usable temperature, of the glass substrate.

Corning 7059 glass is generally used as a glass substrate because of deposition of impurities, prices, and other problems. The transition point of this glass is 628.degree. C. and the strain point is 593.degree. C. Other known practical industrial glass materials having strain points of 550.degree.-650.degree. C. are listed in Table 1.

TABLE 1 __________________________________________________________________________ 7059D (CGW) 7059F (CGW) 1733 (CGW) LE30 (HOYA) TRC5 (OHARA) E-8 (OHARA) __________________________________________________________________________ strain point (.degree.C.) 593 593 640 625 643 thermal expansion 50.1 50.1 36.5 38.0 52.0 37.0 coefficient (.times. 10.sup.-7) transmission (%) 89.5 89.5 91.9 90.0 N.A. 91.0 (400 nm) (400 nm) (400 nm) (450 nm) (450 nm) composition SiO.sub.2 49 49 57 60 59 Al.sub.2 O.sub.3 10 10 16 15 15 B.sub.2 O.sub.3 15 15 11 6 7 R.sub.2 O 0.1 2 1 __________________________________________________________________________ N-0 (NEG) OA2 (NEG) AN1 (AGC) AN2 (AGC) NA35 (HOYA) NA45 (HOYA) __________________________________________________________________________ strain point (.degree.C.) 625 625 616 650 610 thermal expansion -7.0 38.0 44.0 47.0 39.0 48.0 coefficient (.times. 10.sup.-7) transmission (%) N.A. 90.0 90.0 89.8 N.A. N.A. (450 nm) (500 nm) (500 nm) composition SiO.sub.2 60 56 53 51 Al.sub.2 O.sub.3 15 15 11 11 B.sub.2 O.sub.3 6 2 12 13 R.sub.2 O 2 0.1 0.1 0.1 __________________________________________________________________________

Where an amorphous silicon film formed on a glass substrate by CVD is crystallized by heating, a high temperature, e.g., above 600.degree. C., is needed. Therefore, where a Corning 7059 glass substrate is used, the substrate is shrunk by the heating.

An active-matrix liquid crystal display is known as an apparatus utilizing TFTs formed on a glass substrate. To fabricate this liquid crystal display, it is necessary to form tens of thousands to several millions of TFTs on the glass substrate in rows and column. To manufacture the TFTs, processes using numerous masks are necessitated. Consequently, shrinkage of the substrate is a great impediment to the manufacturing process.

Especially, where it is necessary to make a mask alignment before thermal treatment, substrate shrinkage caused by the thermal treatment is a problem.

In a process for heat-treating substrates, it is common practice to place these plural substrates in vertical posture within a heating furnace, taking account of the processing speed. Where the substrates are heated above their strain point, warpage of the substrates is conspicuous.

In recent years, semiconductor devices having TFTs on a glass substrate or on other insulating substrate, e.g., an active-matrix liquid crystal display using TFTs for driving pixels and image sensors, have been developed.

As the glass substrate, Corning 7059 glass is generally used taking the price problem and the problem of impurity precipitation from the glass substrate into consideration. The Corning 7059 glass has a transition temperature of 628.degree. C. and a strain point of 593.degree. C. Other known industrial glass materials having a strain point of 550.degree. to 650.degree. C. are shown in Table 1 above.

TFTs used in these devices are generally made of silicon semiconductor in the form of a thin film. Silicon semiconductors in the form of a thin film are roughly classified into amorphous silicon semiconductors (a--Si) and crystalline silicon semiconductors. Amorphous silicon semiconductors are fabricated at low temperatures and can be fabricated relatively easily by CVD. Hence, they are adapted for mass production. In consequence, they are used most commonly. However, they are inferior in physical properties such as electrical conductivity to crystalline silicon semiconductors. Therefore, in order to obtain higher-speed characteristics, it is eagerly required that a method of fabricating TFTs consisting of crystalline silicon semiconductor be established. It is known that crystalline silicon semiconductors include polycrystalline silicon, crystallite silicon, amorphous silicon containing crystalline components, and semi-amorphous silicon having a state midway between crystalline state and amorphous state.

One known method of obtaining these crystalline thin films of silicon semiconductor consists of forming an amorphous thin semiconductor film and applying thermal energy to the film for a long time by thermal annealing to crystallize the amorphous film. This method requires that the substrate be heated above 600.degree. C. As a result, the substrate irreversibly shrinks. After a patterning step, it is impossible to perform this processing at such a high temperature. Furthermore, the heating step required for crystallization persists for as long as tens of hours. Therefore, it is necessary to shorten the heating time.

In relation to these problems, it has been recently discovered that addition of some metal element acting as a catalyst for promoting crystallization lowers the crystallization temperature and shortens the crystallization time. It has been confirmed that Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au, and Ag are catalytic metal elements that are effective in promoting crystallization.

If these elements are introduced uniformly over the whole surface of a silicon film, crystals grow perpendicularly to the film, i.e., in the direction of the film thickness. However, if they are introduced into a certain portion and crystallization is caused, a crystallized region grows to the surroundings from this certain portion, i.e., grows laterally. A silicon film crystallized in this way exhibits a higher field mobility than that of a silicon film in which a catalytic metal element has been introduced uniformly.

In order to introduce such a catalytic metal element selectively, a patterning step must be carried out before a thermal annealing step for crystallization. The aforementioned shrinkage of the substrate may cause the pattern of the introduced catalytic metal element to deviate from patterns of other elements and circuits greatly. FIGS. 4(A)-4(C) show an example in which TFTs are fabricated, using the means described above. A region 402 indicated by one broken line in FIG. 4(A) shows a position at which an active layer, or a silicon film, should be patterned. A region 403 indicated by another broken line in FIG. 4(A) shows a position at which a gate electrode should be patterned. A rectangular region 401 indicated by the solid line shows a pattern in which a catalytic metal element should be introduced.

In this scheme, if a thermal annealing step is effected after a catalytic metal element has been introduced, then an elliptical region 404 shown in FIG. 4(B) is crystallized. That is, the region 404 is a laterally crystallized region. The size of this ellipse depends on the concentration of the catalytic metal element, on the thermal annealing time, and on the thermal annealing temperature. As shown in FIG. 4(B), if the gate electrode and the active region are formed in position, then channel formation regions of TFTs are formed inside the laterally crystallized region and so no problems take place. In practice, however, thermal annealing results in shrinkage of the substrate. In consequence, the gate electrode and the active layer are formed as indicated by 405 and 406, respectively. The region 404 and the channel formation region do not overlap each other. That is, of the channel formation region, a region indicated by hatching 407 remains amorphous, thus greatly deteriorating the characteristics of the TFTs.

In this way, shrinkage of the substrate makes it quite difficult to perform a patterning step before processing at a high temperature is carried out. This high temperature varies, depending on the kind of the substrate. For Corning 7059 glass which is relatively often used, the high temperature is above 500.degree. C.

SUMMARY OF THE INVENTION

In the present invention, thermal annealing is performed to a glass substrate at a first temperature not lower than the strain point of the glass substrate (strain temperature), preferably at a temperature not lower than a glass-transition temperature. The glass substrate is gradually cooled to e.g. a second temperature lower than the strain point at a speed of 2.degree. C./min. or less, preferably at 0.5.degree. C./min. or less, more preferably at 0.3.degree. C./min. or less, thus the glass substrate itself is prevented from shrinking in a thermal treatment later. In general, the less the speed of temperature-decrease is, the better characteristics can be obtained. However, the less the speed of temperature-decrease is, the longer the process time is. Thus mass-productivity will fall down. Therefore, it is necessary to consider the process time and characteristics needed in selecting a speed of temperature-decrease. This thermal treatment may be employed in an oxidizing or nitriding atmosphere.

Thereafter an appropriate base film is formed on a substrate processed in this manner. Thereafter, an amorphous silicon film (non-single crystal silicon film)is formed and crystallized e.g. at a temperature not higher than the first temperature. As this base film, it is desirable to utiliz