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| United States Patent | 5495179 |
| Link to this page | http://www.wikipatents.com/5495179.html |
| Inventor(s) | Wood; Alan G. (Boise, ID);
Farnworth; Warren M. (Nampa, ID) |
| Abstract | A carrier for testing a singularized semiconductor die prior to packaging
the die utilizes a removable die supporting substrate. The die is placed
in the carrier and is electrically connected to the substrate, thereby
allowing for the packaging or other use of only known good die. A bridge
clamp presses against a rigid cover which, in turn, bias the die against a
plurality of die contacting members located on the die supporting
substrate. The use of the removable die supporting substrate permits a
single carrier design to accommodate different die types and further
permits handling equipment to mechanically handle the one carrier design.
This facilitates the handling of the carrier so that the carrier can be
conveniently used during burn-in and test procedures. |
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Title Information  |
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Drawing from US Patent 5495179 |
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Carrier having interchangeable substrate used for testing of
semiconductor dies |
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| Publication Date |
February 27, 1996 |
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| Filing Date |
September 21, 1993 |
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| Parent Case |
CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation-in-part to U.S. patent application Ser. No.
8/046,675, filed Apr. 14, 1993, now U.S. Pat. No. 5,367,253, which is a
continuation-in-part to U.S. patent application Ser. No. 7/973,931, filed
Nov. 10, 1992, now U.S. Pat. No. 5,302,891 which is a continuation of Ser.
No. 7/709,858, filed Jun. 4 1991, now abandoned. |
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Title Information  |
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Claims  |
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What is claimed is:
1. Apparatus for testing a discrete bare semiconductor die, comprising:
a) a substrate for providing an electrical connection between the die and
test circuitry;
b) the substrate including a plurality of contacts in electrical
communication with circuit traces, said contacts adapted to establish
electrical communication with contact locations on the die;
c) a base for retaining the die and substrate;
d) a latching mechanism attached to the base for securing the substrate to
the base, said latching mechanism including terminal contacts adapted to
contact the substrate and establish an electrical connection between the
circuit traces on the substrate and the test circuitry; and
e) clamp means attached to the base for biasing the die and substrate
together and forcing the contacts on the substrate against the contact
locations on the die with a predetermined force.
2. Apparatus as described in claim 1, and wherein:
a) the circuit traces are in electrical communication with contact pads
formed on the substrate; and
b) the terminal contacts of said latching mechanism engage said contact
pads on the substrate.
3. Apparatus as described in claim 2, and wherein:
a) a release member is attached to the base, the release member being
movable relative to the substrate;
b) the terminal contacts are formed as latches releasable by movement of
the release member;
c) the relative movement of the release member is adapted to move the
terminal contacts out of engagement with the substrate.
4. Apparatus as described in claim 1, wherein said substrate further
comprises:
a raised portion formed on each contact, the raised portion adapted to
penetrate its respective contact location on the die while a top surface
of the contact limits a penetration depth, thereby establishing electrical
communication with said contact location.
5. Apparatus as described in claim 4, and wherein:
the plurality of contacts are formed on the substrate using semiconductor
circuit fabrication techniques.
6. Apparatus as described in claim 6, and wherein:
the substrate is formed of silicon material, and the circuit traces are
formed on the silicon material by semiconductor circuit fabrication
techniques.
7. Apparatus as described in claim 4, and further comprising:
a pad which is electrically conductive in a Z-axis, normal to a plane of
the pad, and which provides electrical isolation across the plane of the
pad, the pad being positioned between the die and the plurality of
contacts.
8. An apparatus for testing a discrete, unpackaged semiconductor die
comprising:
a base for retaining the die;
a substrate placed within the base for establishing electrical
communication between the die and test circuitry, the substrate including
a contact adapted to penetrate a contact location on the die, and a
circuit trace in electrical communication with the contact;
a latching mechanism attached to the base for securing the substrate to the
base and having a movable terminal contact adapted to contact the die
supporting substrate to secure the die to the substrate and to establish
electrical communication between the circuit trace and the test circuitry;
and
a bridge clamp removably attached to the base including a spring for
applying a predetermined force to the die to bias the die against the
substrate so that the contact on the substrate penetrates the contact
location on the die.
9. The apparatus as claimed in claim 8 and further comprising:
contact pads formed on the substrate in electrical communication with the
circuit traces for contact with the terminal contact.
10. The apparatus as claimed in claim 8 and wherein:
the contact on the substrate includes a raised portion adapted to pierce
the contact location on the die while the remainder of the contact limits
a penetration depth.
11. The apparatus as claimed in claim 8 and further comprising:
a cover placed between the clamp and die and including an opening to permit
the die to be attached to the cover for loading into the apparatus using a
vacuum.
12. The apparatus as claimed in claim 8 and wherein:
the substrate is formed of silicon using semiconductor circuit fabrication
techniques.
13. The apparatus as claimed in claim 8 and wherein:
the substrate is formed of a ceramic material and the contacts are formed
by doinking.
14. The apparatus as claimed in claim 8 and further comprising:
a Z-axis anisotropic interconnect material placed between the die and
substrate.
15. The apparatus as claimed in claim 8 and wherein:
the base includes a recess for retaining the substrate.
16. An apparatus for testing a singularized, unpackaged semiconductor die
comprising:
a base for retaining the die;
a substrate mounted within the base for establishing electrical
communication between the die and test circuitry, the substrate including
a contact having a raised portion adapted to penetrate a contact location
on the die while a remainder of the contact limits a penetration depth,
and a circuit trace in electrical communication with the contact;
a latching mechanism attached to the base for securing the substrate to the
base and having a movable terminal contact adapted to contact the
substrate to establish electrical communication between the circuit trace
and the test circuitry; and
a clamp removably attached to the base and including a spring for applying
a predetermined force to the die to bias the die against the substrate so
that the contact on the substrate penetrates the contact location on the
die to a predetermined depth.
17. The apparatus as claimed in claim 16 and further comprising:
a cover placed between the die and spring and including an opening for
attaching the die to the cover using a vacuum.
18. The apparatus as claimed in claim 16 and wherein:
the contact is formed as a bump having a pointed projection.
19. The apparatus as claimed in claim 16 and further comprising:
a release member attached to the base for moving the latching mechanism to
move the terminal contact out of contact with the substrate. |
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Claims  |
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Description  |
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FIELD OF THE INVENTION
This invention relates to the field of semiconductor device testing. More
specifically, the invention relates to an apparatus for supporting
semiconductor die in carriers during burn-in and test procedures.
BACKGROUND OF THE INVENTION
Many types of semiconductor devices are made using similar manufacturing
procedures. A starting substrate, usually a thin wafer of silicon, is
doped, masked, and etched through several process steps, the steps
depending on the type of devices being manufactured. This process yields a
number of die on each wafer produced. Each die on the wafer is given a
brief test for full functionality, and the nonfunctional die are
mechanically marked or mapped in software. This brief test is only a gross
measure of functionality, and does not insure that a die is completely
functional or has specifications that would warrant its assembly in a
package.
If the wafer has a yield of grossly functional die, it indicates that a
good quantity of die from the wafer are likely to be fully operative. The
die are separated with a die saw, and the nonfunctional die are scrapped,
while the rest are individually encapsulated in plastic packages or
mounted in ceramic packages with one die in each package. After the die
are packaged they are rigorously electrically tested. Components which
turn out to be nonfunctional, or which operate at questionable
specifications, are scrapped or devoted to special uses.
Packaging unusable die, only to scrap them after testing, is a waste of
time and materials, and is therefore costly. Given the relatively low
profit margins of commodity semiconductor components such as dynamic
random access memories (DRAMs) and static random access memories (SRAMs),
this practice is uneconomical. However, no thorough and cost effective
method of testing an unpackaged die is available which would prevent this
unnecessary packaging of nonfunctional and marginally functional die.
Secondly, the packaging may have other limitations which are aggravated by
burn-in stress conditions, so that the packaging becomes a limitation for
burn-in testing.
It is proposed that multiple integrated circuit devices be packaged as a
single unit, known as a multi chip module (MCM). This can be accomplished
with or without conventional lead frames. This creates two problems when
using conventional test methods. Firstly, discrete testing is more
difficult because a conventional lead frame package is not used.
Furthermore, when multiple devices are assembled into a single package,
the performance of the package is reduced to that of the die with the
lowest performance. Therefore, such dies are tested on an individual basis
at probe, using ambient and "hot chuck" test techniques, while still in
wafer form. In other words, the ability to presort the individual dice is
limited to that obtained through probe testing.
In addition, there is an increased interest in providing parts which are
fully characterized prior to packaging. This is desired not only because
of the cost of the package, but also because there is demand for
multi-chip modules (MCMs), in which multiple parts in die form are tested
and assembled into a single unit. While there are various techniques
proposed for testing, burning in and characterizing a singulated die, it
would be advantageous to be able to "wafer map" the die prior to assembly
with as many performance characteristics as possible. Ideally, one would
want to be able to map the wafer with full device characterization.
MCMs create a particular need for testing prior to assembly, as contrasted
to the economics of testing parts which are discretely packaged as
singulated parts. For discretely packaged parts, if the product yield of
good parts from preliminary testing to final shipment (probe-to-ship) is,
for example, 95%, one would not be particularly concerned with packaging
costs for the failed parts, if packaging costs are 10% of the product
manufacturing costs. Even where packaging costs are considerably higher,
as in ceramic encapsulated parts, testing unpackaged die is economical for
discretely packaged parts when the added costs approximates that of cost
of packaging divided by yield:
##EQU1##
where C=cost
C.sub.DIE =manufacturing cost of functional die
C.sub.ADDL. KGD =additional cost of testing unpackaged die in order to
produce known good die (KGD)
Note that in the case of discretely packaged parts, the cost of the die
(C.sub.DIE) is essentially not a factor. This changes in the case of MCMs:
##EQU2##
Note that again C.sub.DIE is not a factor in modules having identical part
types; however, the equation must be modified to account for varied costs
and yields of die in modules with mixed part types.
With MCMs, the cost of packaging a failed part is proportional to the
number of die in the module. In the case of a .times.16 memory array
module, where probe-to-ship yield of the die is 95%, the costs are:
##EQU3##
so the additional costs of testing for known good die (KGD) may be 16
times the cost of testing an unrepairable module and still be economical.
This, of course, is modified by the ability to repair failed modules.
Testing of unpackaged die before packaging into multichip modules would be
desirable as it would result in reduced material waste, increased profits,
and increased throughput. Using only known good die in MCMs would increase
MCM yields significantly.
Testing unpackaged die requires a significant amount of handling. Since the
test package must be separated from the die, the temporary packaging may
be more complicated than either standard discrete packaging or multichip
module (MCM) packaging. The package must be compatible with test and
burn-in procedures, while securing the die without damaging the die at the
bondpads or elsewhere during the process.
We propose an approach for testing of unpackaged die which utilizes a two
piece reusable burn-in/test fixture. The fixture consists of two halves,
one of which is a die cavity plate for receiving a semiconductor die as
the devices under test (DUT). A die is placed in a cavity in a first half
of the fixture, and a die contact member is used to establish contact with
bondpads on the die, and to conduct between the bondpads and external
connector leads on the fixture.
External connector leads are used, and may be provided in a preferred
configuration, such as a DIP (dual inline package) or QFP (quad flat pack)
configuration. The fixture establishes electrical contact with a single
die and with a burn-in oven, as well as permitting testing of dice in
discretely packaged form.
Such a configuration requires that the die bondpads or other contact points
be aligned with contacts in the fixture. The fixture must then maintain
the die in alignment without damage to the die, and particularly to the
bondpads. The fixture is then manipulated through test procedures.
One advantage of the temporary package is that it need not meet the
requirements of a conventional package in terms of flexibility of
installation; that is, it can be cumbersome and not readily adaptable to
an end use other than the test and burn-in equipment. The die is expected
to be moved out of the temporary package subsequent to testing, so that
the package need only be useful for the various test and burn-in
procedures.
Since the temporary package is specifically intended for test and burn-in
procedures, it is desired that the package be easy to assemble on a
temporary basis, and thereby at least partially facilitate the test and
burn-in procedures.
In U.S. Pat. No. 4,899,107, commonly assigned, a reusable burn-in/test
fixture for discrete TAB die is taught. The fixture consists of two
halves, one of which is a die cavity plate for receiving semiconductor
dies as the units under test (UUT); and the other half establishes
electrical contact with the dies and with a burn-in oven.
The first half of the test fixture contains cavities in which die are
inserted circuit side up. The die will rest on a floating platform. The
second half has a rigid high temperature rated substrate, on which are
mounted probes for each corresponding die pad. Each of a plurality of
probes is connected to an electrical trace on the substrate (similar to a
P.C. board) so that each die pad of each die is electrically isolated from
one another for high speed functional testing purposes. The probe tips are
arranged in an array to accommodate eight or sixteen dies.
The two halves of the test fixture are joined so that each pad on each die
aligns with a corresponding probe tip. The test fixture is configured to
house groups of 8 or 16 die for maximum efficiency of the functional
testers.
There are some testing and related procedures when the parts are
singulated. For this reason, it is inconvenient to retain multiple die in
a single test fixture.
Various forms of connections are used to connect the die to a package or,
in the case of a multichip module (MCM), to other connections. These
include wirebonding, TAB connections, bump bonding directly to substrate,
and conductive adhesives.
The bondpads are conductive areas on the face of the die which are used as
an interconnect for connecting the circuitry on the die to the outside
world. Normally, conductors are bonded to the bondpads, but it is possible
to establish electrical contact through the bondpads by biasing conductors
against the bondpads without actual bonding.
One of the problems encountered with burn in and full characterization
testing of unpackaged die is the physical stress caused by connection of
the bondpads to an external connection circuitry. This problem is
complicated by the fact that in many die configurations, the bondpads are
recessed below the surface level of a passivation layer. The passivation
layer is a layer of low eutectic glass, such as BPSG, which is applied to
the die in order to protect circuitry on the die. (The term "eutectic"
does not, strictly speaking, apply to glass, which is an amorphous fluid;
however, the term is used to describe the characteristic of some glasses
wherein, as a result of their formulation, they readily flow at a given
temperature.)
The ohmic contact between bondpads or test points on a die and a known good
die test carrier package has been a matter of interest. It is difficult to
achieve and maintain consistent ohmic contact without damaging the
bondpads and passivation layer on the die. The design criteria of such
contacts is somewhat different from the design criteria of the carrier
package.
A prior art apparatus for packaging semiconductor devices includes a
carrier tray which accepts a plurality of ceramic type packages, such as
DIP (dual in-line package) or QFP (quad flat pack) packages. With the
carrier supporting the package, the die is inserted, secured to the
package and electrically attached to the package. A metallic lid is
supported on the package by a bridge clamp which is clamped to the carrier
tray over the package. The bridge clamp, in turn, clamps the lid against
the package. The lid is then fused to the package, typically by soldering.
The packages are then removed from the carrier tray.
SUMMARY OF THE INVENTION
According to the invention, a semiconductor die is inserted into a carrier
tray and positioned so that bondpads on the dies or similar contacts on
the die are in alignment with die contacting members on a substrate. The
die contacting members, in turn, connect the dies to external conductors.
The dies are secured against movement by means of bridge clamps which bias
the die against the substrate within the carrier. When the die is secured,
the carrier is used as a test fixture in order to perform burn-in and test
procedures on the dies.
In a preferred embodiment, the bridge clamp presses against a rigid cover
which biases the die against the die contacting members on the substrate.
In a preferred embodiment, the substrate with the die contacting members
is below the die, on an opposite side of the die from the cover, and are
mounted to the carrier by the use of a plurality of electrical terminal
contacts on the carrier which engage contact pads on the substrate. The
contact pads are in electrical communication with the die contacting
members.
In a preferred embodiment, the bridge clamp engages the die carrier,
thereby allowing the die carrier to be handled as a singulated package
when the die is secured inside the die carrier.
According to the invention, semiconductor dies are inserted into a carrier
tray and positioned so that bondpads on the dies or similar contacts on
the die are in alignment with die contacting members on a substrate. The
die contacting members, in turn, connect the dies to external conductors.
The dies are secured against movement by means of bridge clamps which
extend to the carrier tray. When the dies are secured, the carrier tray is
used as a test fixture in order to perform burn-in and test procedures on
the dies.
The use of a separate die supporting substrate allows substituting
substrates. This enables the construction of a module which can accept a
wide variety of dies. Therefore the requirement of burnin and test
equipment to mechanically handle different types of die carriers for the
different types of dies is reduced or eliminated. In addition, different
substrates can be designed to accommodate a wide variety of die bondpad
configurations, such as edge connect, end connect, and lead over chip
(LOC). This allows the die carrier to accept these different bondpad
configurations.
Since the die carrier is intended for burnin and test applications, it need
not be excessively compact, and may be robust in construction. This
permits the carrier to accept external connections from a variety of test
equipment, such as edge connections, top and bottom contacts and, in one
embodiment, plug or DIP connections.
In one embodiment, a carrier tray supports a plurality of die carriers
which individually support the dies. The carrier tray then supports the
plurality of carriers during burnin and/or test procedures, thereby
expediting handling of multiple dies.
In an alternative embodiment, the invention uses the carrier tray in
cooperation with bridge clamps for retaining the dies in place. This
enhances the stability of the connection of the dies to external
connection terminals on the die carrier fixtures, since the die carrier
fixtures need not be moved (or in some configurations cannot be moved)
with respect to the carrier tray. The invention allows the tray which
supports the bridge clamps to be used as a part of burnin and test
fixtures, thereby facilitating the burn-in and test process. As is the
case with the singulated carriers, the bridge clamps press against a rigid
cover which biases the die against the die contacting members on the
substrate.
BRIEF | | |