An output buffer circuit for a high density programmable logic device. The output buffer includes inverters having n-channel pull up and pull down transistors for driving pull up and pull down transistors providing the buffer output. By utilizing inverters with n-channel replacing p-channel transistors, crowbar resulting from a different number of inverters required to drive the pull up and pull down transistors which provide the buffer output is prevented. By utilizing n-channel rather than p-channel transistors, mobility is increased and Miller capacitance is reduced, reducing loading of the buffer input. To provide the rail-to-rail voltage of p-channel transistors which can further increase switching speed, p-channel pull up transistors are provided with circuitry to turn the p-channel transistors on after the n-channel transistors have turned on and turn the p-channel transistors off after the buffer output switches. To further increase switching speed, the buffer includes circuitry to reduce voltage on the gates of the pull up or pull down transistors providing the buffer output after the p-channel transistor driving its gate turns off. To enable control of additional power consumption occurring with increased buffer operation speed, the buffer provides a selectable fast/slow mode wherein features of the buffer which increase operation speed may be selectively enabled or disabled.
A CMOS circuit prevents feedthrough current and has a small-scaled circuit constitution. An output stage has a P-channel MOS transistor and an N-channel MOS transistor with drains connected to each other to form an output terminal and gates respectively connected to output terminals of first and second series circuits. The first and second series circuits control supply of power and each includes an N-channel MOS transistor and a P-channel MOS transistor with drains connected together to form the output terminal and gates connected together to form an input terminal. A delay circuit receives an input signal and produces a delayed input signal which drives the input terminals of the first and second series circuits. P-channel and N-channel MOS transistors control power potentials applied to sources of the respective P-channel and N-channel MOS transistors of the second and first series circuits and are driven by the input signal which is applied to their gates. The P-channel and N-channel MOS transistors are thereby controlled such that current feedthrough is prevented.
An output buffer circuit for a semiconductor device, capable of uniformly maintaining an output level regardless of an increase of a variable supply voltage VCC and improving an output speed, which includes a constant voltage generation circuit receiving the variable VCC and generating a constant voltage at a predetermined level, an inverter outputting data signals in accordance with the constant voltage outputted from the constant voltage generation circuit and first and second clock signals, a clock signal generation unit generating a third clock signal having a predetermined interval in accordance with the first clock signal and the data signals outputted from the inverter, and a pull-up transistor pulling up the output data signals of a high level at a predetermined level in accordance with the third clock signal.
A buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix on a high to low input signal transition. The buffer further includes a negative hysteresis circuit to prevent oscillations on slow rate low to high input signal transitions.
A low-power CMOS driver circuit capable of operating at high frequencies includes a CMOS output driver circuit and a pair of CMOS predriver circuits for driving the CMOS output driver circuit. A timing circuit is provided for generating three different timing signals for switching the predriver circuits in such a manner that the CMOS driver circuit is capable of operating at frequencies above 1 MHz without dissipating significant power.
A technique includes, in response to a first signal transitioning to a first logic state and first drive circuit being deactivated, activating a second drive circuit to provide a second signal. In response to the second drive circuit being deactivated and the first signal transitioning to a second logic state that is different from the first logic state, the first drive circuit is activated to provide the second signal.
