A synchronizing signal separator receives synchronizing signals from a remote source. A window generator opens a window for a period and a counter regenerates synchronizing signals detected when the window is open. Detection of an incoming synchronizing signal when the window is open causes a window counter to be stopped to reduce the window duration to approach a set minimum width. The window generator and the counter are controlled by a voltage controlled oscillator whose oscillation frequency varies according to a feedback signal derived from the sense of the phase error between an external counter of the window generator and the regeneration counter.
A counter control circuit of a counter for measuring a pulse period of a video synchronization signal includes a main control unit having a synchronization signal input Sync, and a control signal producing unit including a stop signal generator, a latch signal generator, and a start signal generator. The outputs of the stop, latch and start signal generators are supplied to the counter for controlling the counter to count clock pulses fed from a clock generator in response to receipt of a start signal and output a count value in response to receipt of a latch signal. The main control unit produces sequential control signals during the input of the video synchronization signal differentiated by the clock pulses. The counter control circuit allows the counter to measure a pulse period of an input synchronization signal in a stable state that results in an accurate count value, since the count operation is first stopped and the count value is latched by the clock signal.
An output timebase corrector converts orthogonal sampled video (VS) into asynchronous sampled video (VOS) with asynchronous sample values occurring at clock instants (TC) of a clock signal (CLK). The asynchronous sampled video (VOS) is displayed on a display screen of a display device (DD). A discrete time oscillator (DTO) of a time-discrete phase-locked loop (PLL) supplies a time base signal (OS). The time-discrete phase-locked loop (PLL) determines a phase difference (PE) between the time base signal (OS) and reference instants (FB) indicating a timing of a line deflection of the display device (DD) to obtain the time base signal (OS) being locked to the reference instants (FB). The time base signal (OS) controls a sample rate converter (SRC) such that the asynchronous video values (VOS) which occur at the clock instants (TC) are interpolated from the orthogonal sampled video (VS) by the sample rate converter (SRC) such that the video signal is displayed on the correct position on the display screen. In the output timebase corrector according to the invention all circuits are clocked by clock signals (CLK) originating from one and the same clock generator (OSC).
A multimedia communication arrangement communicating video and at least one other data type using a communication channel includes a first interface arrangement for communicating video and the at least one other data type using the communication channel. A second interface arrangement exchanges data with, and provides power to, at least one of a variety of peripheral devices. A video data signal processor circuit processes the video data and sends the video data along with the at least one other data type over the first interface arrangement and communicates with the peripheral devices over the second interface arrangement.
A method and apparatus for detecting video signal dropout. The method includes the step of generating a video signal, and then electronically isolating at least one component of the video signal. The at least one component is representative of the absence of the video signal itself. Next, the absence of the at least one component is electronically sensed. The step of electronically isolating can include the step of passing the video signal through a comb filter, and in particular isolating a luminescence signal from the video signal. The step of electronically isolating can also include passing the video signal through a sync separator. The step of electronically sensing can include passing the at least one component through a comparator. The method can also include the step of generating the video signal for a predetermined time duration, and simultaneously generating an audio signal to indicate the end of the predetermined time duration. In this embodiment, the step of electronically sensing is then terminated in response to the audio signal.
The invention pertains to a digital video horizontal synchronization pulse detector and processor comprising pulse detector for generating a timing pulse in response to each horizontal synchronization pulse. A sync position error device generates a time position error signal for each timing pulse relative to a corresponding window pulse. A window pulse generator generates the window pulses and limits the time position error signals to a maximum value. An acquisition device tracks when the timing pulses occur inside and outside the corresponding window pulses. An averaging device averages the time position error signals to generate an average error signal. A counter phase locks to the timing pulses to generate processed horizontal sync pulses such that when the timing pulses occur within the corresponding window pulses the counter is adjusted by the average error signal and when a predetermined number of timing pulses occur outside the corresponding window pulses, the counter is loaded with a predetermined value during a timing pulse to align the timing pulses with the corresponding window pulses.
