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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to an arithmetic processor and more
particularly to an improved floating point processor which can perform
arithmetic operation on the fraction of a floating point number, obtain
the absolute value of the result of the operation and round the result of
the operation at high speed by using a small number of circuit elements.
2. Description of the Related Art
Ordinary floating point operation is performed by a processor having
typical construction as shown in FIG. 1. In this figure, reference
characters XI, Ex and Fx indicate input data, an exponent part (hereunder
sometimes referred to simply as an exponent) and a fraction part
(hereunder sometimes referred to simply as a fraction) of the input data,
respectively. Further, reference characters YI, Ey and Fy denote another
input data, an exponent part and a fraction part of the input data YI,
respectively. Moreover, reference characters ZO, Ez and Fz indicate output
data, all exponent part and a fraction part of the output data,
respectively. Furthermore, reference numerals 500 and 501 indicate a
processor for arithmetic operation of a fraction and an exponent
comparator, respectively. Reference numerals 502, 503 and 504 indicate
selection circuits. Furthermore, 505, 507, 509 and 510 indicate a shifter,
an adder, a rounding circuit and a normalization circuit, respectively.
Additionally, reference numerals 506 and 508 indicate complement data
generators.
The operation of a conventional processor illustrated in FIG. 1 is now
described in detail. First, the exponent parts Ex and Ey of the input data
XI and YI are compared by the exponent comparator 501 by subtracting one
of these exponent parts from the other thereof. Further, the selection
circuits 502 and 508 are controlled such that the fraction part of the
input data, of which the exponent part is less than that of the other
data, of the parts Ex and Ey is inputted into the shifter 505 and on the
other hand that of the other of the input data XI and YI is inputted into
the complement data generator 506. Moreover, the selection circuit 504 is
controlled such that the larger one of the exponent parts Ex and Ey is
inputted into the normalization circuit 510. The absolute value of the
difference between the exponent parts Ex and Ey is then inputted into the
shifter 505. Next, the fraction inputted into the shifter 505 is shifted
to right by the number of digits corresponding to the difference between
the exponent parts Ex and Ey and the weight of corresponding bits of two
fraction parts Fx and Fy are made equal to each other. At this time,
additional three bits are obtained from the bits "crowded out of" the
shifter 505 from the right end thereof by the shift of digits to right
therein. The most significant bit of these three bits is called "a guard
bit" and is the most significant one of the "crowded out" bits. The second
most significant bit of the additional three bits is called "a round bit"
and is the second most significant one of the "crowded out" bits. The
least significant bit of the three bits, called "a sticky bit" is obtained
by the logical OR of the remaining ones of the "crowded out" bits. These
three bits are added to the least significant bit of the fraction part
supplied to and shifted in the shifter 505 below the least significant bit
thereof and are used to round the numerical value of the result of the
arithmetic operation. Thereafter, if the arithmetic as to the fraction is
addition, the fraction outputted from the selection circuit 502 is further
outputted by the complement data generator 506 to the adder 507 as it is.
On the other hand, if the arithmetic operation relating to the fraction is
subtraction, the two's complement of the fraction outputted is generated
and then outputted by the complement data generator 506 to the adder 507.
Further, the fractions, of which the weight of corresponding bits are made
equal to each other, are added by the adder 507. Then, in order to obtain
the absolute value of the result of the addition of the fractions, in case
that the result of the addition effected by the adder 507 is positive, the
result of the addition is outputted by the complement data generator 508
to further output the rounding circuit 509 as it is. 0n the other hand, if
the result of the addition is negative, the two's complement of the result
of the addition effected by the adder 507 is generated and further
outputted to the rounding circuit 509by the complement data generator 508.
In the rounding circuit 509, the value of the result of the arithmetic
operation of the fraction received from the generator 508 is rounded.
Finally, the value resulted from the above described arithmetic operations
of the fractions (hereunder referred to simply as "the interim or
temporary result") is shifted to right or left by the number of digits
required to the normalization thereof by the normalization circuit 510.
Thereafter, in case that the "interim result" is shifted to right, the
amount of the shifted number of digits is added to the exponent inputted
to the normalization circuit 510. Further, in case that the "interim
result" is shifted to left, the amount of the shifted number of digits is
subtracted from the exponent inputted to the normalization circuit 510.
Moreover, floating point overflow or floating point underflow is detected
by judging whether or not the result of floating point this operation of
the exponent exceeds a predetermined range. If not detected, the result of
this operation is outputted as it is. Contrarily, if detected, the result
of this operation is modified and thus the process of the above described
operations is completed.
As above stated, in order to obtain the absolute value of the fraction, the
output of the adder 507 is inputted to the rounding circuit 509 as it is
if the output of the adder 507 is positive. Further, if negative, two's
complement of the output of the adder 507 is to be generated and further
outputted to the rounding circuit 509. Practically, the generation of the
two's complement by this complement data generator 508 is effected by
logically inverting each bit of the input data and further adding 1 to the
least significant bit of the inverted input data. Accordingly, the
conventional arithmetic circuit has a drawback that if the result of the
arithmetic operation such as the addition of the fractions is negative,
two's complement is to be generated and thus it takes much of the
operation time and further the configuration of the circuits is complex.
Furthermore, in the arithmetic circuit, on completion of the addition of
the fractions, the rounding of the result of the addition is effected by
the rounding circuit 509. In this rounding operation, the digit to be
rounded should be detected in the result, of which the absolute value is
obtained, of the arithmetic operation and further a carry generated by the
rounding should be added to the detected to digit. Thus, the prior art
arithmetic circuit has a defect that in such a case, the rounding
operation cannot be started unless the absolute value of the result of the
arithmetic operation is determined and that it takes much of the operation
time to round the result of the arithmetic circuit and the complex circuit
is required for the rounding operation.
Further, the exponent comparator 501 is a circuit for comparing the two
input data with each other, detecting the relation in magnitude between
the two input data and obtaining the absolute value of the difference in
magnitude between the two input data. Concurrently, the exponent
comparator 501 subtracts a second input data from a first input data and
judges from the overflow whether the result of the subtraction is positive
or negative. Further, the exponent comparator 501 outputs the result of
the subtraction as it is if the result of the subtraction is positive. If
negative, the comparator 501 outputs two's complement of the result of the
subtraction is outputted to obtain the value of the result when the sign
of the value is reversed. The generation of the two's complement is
concretely effected by logically reversing each bit of the input data and
adding 1 to the least significant bit of the logically reversing data.
Thus, if the result of the subtraction is negative, an operation of
further adding 1 to the result thereof is additionally required.
Therefore, the conventional arithmetic circuit has another drawback that
it takes much time to obtain the absolute value of the difference and
further the adder as well as the subtracter is needed so that the
arithmetic processor becomes large in size.
Further, in the normalization circuit 510, a floating point underflow and a
floating point overflow are detected. According to IEEE 754 Floating Point
Arithmetic Standard, the number of digits of exponent Dart is determined
to be 8 in case of single precision; 11 in case of double precision; and
15 in case of extended double precision, respectively. Further, the range
of the exponent of the ordinary normalized floating point data Exp is as
follows:
0<Exp<2.sup.n -1 (where n is the number of digits in an exponent).
If the arithmetic operation of the exponent results in that Exp.ltoreq.0, a
floating point underflow occurs. Further, if Exp.ltoreq.2.sup.n -1, a
floating point overflow occurs. Namely, it is necessary to determine the
range of the result of the operation of the exponent. Thus, the
conventional arithmetic processor has still another drawback that if a
floating point underflow or a floating point overflow is detected after
the exponent correction operation accompanied by the normalization of the
fraction is fully completed, the output of the detection signal is
delayed.
SUMMARY OF THE INVENTION
The present invention is accomplished to eliminate the above described
drawbacks of the conventional arithmetic processor.
It is, accordingly, a first or primary object of the present invention to
provide an arithmetic processor which can perform arithmetic operation on
fractions, obtain the absolute value of the result of the arithmetic
operation and round the result at high speed in floating point operation
by using circuit elements which are smaller in number than that of the
circuit elements of the prior art processor.
Further, it is a second object of the present invention to provide an
arithmetic processor which can output the absolute value of the difference
between two data at high speed by using circuit elements which are smaller
in number than that of the circuit elements of the prior art processor.
Moreover, it is a third object of the present invention to provide an
arithmetic processor which can perform the arithmetic operation of
exponents and detect a floating point overflow and a floating point
underflow at high speed in the floating point operation by using circuit
elements which are smaller in number than that of the circuit elements of
the prior art processor.
Furthermore, it is a fourth object of the present invention to provide an
arithmetic processor which can detect the relation in magnitude between
two data at high speed.
In accordance with one aspect of the invention, an arithmetic processor
comprises a first arithmetic means for subtracting second data from first
data and deriving an overflow signal, in combination with a second
arithmetic means for subtracting the sum of the second data and "1" from
the first data and deriving another overflow signal, and a detection means
for detecting the magnitude relation between the first and second data
from the overflow signals derived from the first and second arithmetic
means.
Another aspect of the invention is concerned with an arithmetic processor
comprising a carry generation and propagation producing means for
subtracting second data from first data and deriving an overflow signal
and for subtracting the sum of the second data and "1" from the first data
and deriving another overflow signal. A detection means detects the
magnitude relation between the first and second data from the overflow
signals derived from the carry generation and propagation producing means.
BRIEF DESCRIPTION OF THE DRAWINGS
Other features, objects and advantages of the present invention will become
apparent from the following description of preferred embodiments with
reference to the drawings in which like reference characters designate
like or corresponding parts throughout several views, and in which:
FIG. 1 is a block diagram of a conventional arithmetic processor for
performing floating point operation;
FIG. 2 is a block diagram of a first embodiment of the present invention;
FIG. 3 is a truth table of a "carry for rounding" signal at an addition
effected in the first embodiment of the present invention;
FIG. 4 is a truth table of a "carry for rounding" signal at a subtraction
effected in the first embodiment of the present invention;
FIG. 5 is a diagram of the logic circuit of the first embodiment of the
present invention implemented by employing CMOS circuits;
FIG. 6 is a block diagram showing a second embodiment of the present
invention;
FIG. 7 is a diagram of the logic circuit of the second embodiment of the
present invention implemented by employing CMOS circuits;
FIG. 8 is a block diagram of a third embodiment of the present invention;
FIG. 9 is a diagram of the logic circuit of the third embodiment of the
present invention implemented by employing CMOS circuits; and
FIG. 10 is a block diagram of a fourth embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, preferred embodiments of the present invention will be
described in detail with reference to the drawings.
FIG. 2 is a block diagram of a first preferred embodiment of the present
invention. In this figure, reference numerals 501, 502, 503, 504, 505 and
510 indicate circuits similar to those indicated by the same reference
numerals in FIG. 1, respectively. Circuit 100 performs arithmetic
operations on fractions of data which acts as the circuit 500 for
performing the arithmetic operations on the fractions shown in FIG. 1; 101
a carry generation and propagation producing circuit; 102 a "carry for
rounding" generation circuit; 103 and 104 sum and difference generating
circuit; 105 an reversing or inverting circuit; and 106 indicates a
"result selection signal" generating circuit; 107 a selection circuit.
Moreover, reference characters X indicates a fraction of data having a
large exponent (hereunder referred to as an operand); Y a fraction of data
having a small exponent and shifted to right (hereunder referred to as an
operand); GRS a guard bit, a round bit and sticky bit (hereunder referred
to simply as GRS) of the operand Y; MSUB a subtraction signal; and Z
indicates the result of the operations including rounding and obtaining
the absolute value of data.
First, an operation of the arithmetic circuit 100 for effecting an
arithmetic operation on a fraction of FIG. 100 will be described
hereinbelow. When the operand X and the operand Y are inputted into the
carry generation and propagation producing circuit 101, a carry signal
C.sup..quadrature. 10S generated at each digit in case of addition of the
fractions X and Y is obtained and another carry signal C.sup.1 109
generated at each digit in case of adding the fractions X and Y when there
is a carry of 1 added to the least significant bit is also obtained. On
the other hand, if the arithmetic operation on the fractions is
subtraction, a borrow signal C.sup..quadrature. 108 generated at each
digit in case of subtracting the fraction Y from the fraction X, as well
as a borrow signal C.sup.1 109 generated at each digit in case of
subtracting the fraction Y from the fraction X when there is a borrow of 1
to the least significant bit, is obtained. Further, the borrow signals
C.sup..quadrature. 108 and C.sup.1 109 are added to the sum and difference
circuits 103 and 104, respectively. The signals C.sup..quadrature. and
C.sup.1 will be referred to as carry signals hereafter. The carry
generation circuits for generating these carry signals can be constructed
such that the most part of one of the carry generation circuits is in S
common with each other. Moreover, in the carry generation and propagation
producing circuit 101, an intermediate sum S of the outputs of the
exclusive OR of each pair of corresponding bits of the fractions X and Y
is obtained. Furthermore, the "carry for rounding" generation circuit 102,
part of each of the operand X and the operand Y, as well as GRS, is
inputted to the "carry for rounding" generation circuit 102, whereupon is
obtained a "carry for rounding" signal 111 indicating a "carry for
rounding", that is, a carry (a borrow (in case of subtraction)) to a digit
corresponding to the least significant bit of the carry generation and
propagation producing circuit 101, which carry is generated at a digit
where rounding is effected in operations on X and Y and GRS. Further, the
"carry for rounding" signal 111 is inputted to the result selecting signal
generation circuit 106. Next, the sum and difference generating circuit
103 (or104) evaluates the result 112 (or 113) of an operation on the
fractions X and Y, that is, (X.+-.Y) (or X.+-.(Y+1) in case that a carry
or borrow has occurred to the least significant bit) from the carry
signals C.sup..quadrature. 108 (or C.sup.1 109) and the exclusive OR of
each pair of the corresponding bits thereof at each digit, which are
obtained in the carry generation and propagation producing circuit 101.
The results of the operations are inputted to the selection circuit 107.
Only the result 113 of the operation X.+-.(Y+1) is also inputted to the
inverting circuit 105. The data at two bits 114 and 115 of higher order
including the overflows occurred in the results of these operations are
inputted to the result selecting signal generation circuit 106. Further,
the inverting circuit 105 evaluates the result 116 of the operation
X.+-.(Y+1) by reversing each bit of the result 113 of the operation
X.+-.(Y+1). The obtained result 116 of the operation X.+-.(Y+1) is added
to the contents of the selection circuit 107. Furthermore, the value of
the result 116 of the operation X.+-.(Y+1) is equal to the value of
-(X-Y) obtained by reversing the sign of the X-Y in case the arithmetic
operation is a subtraction. Finally, a selection signal 117 for selecting
an appropriate result from the results 112, 113 and 116 is generated in
response to the "carry for rounding" signal 111 obtained in the "carry for
rounding" signal generation circuit 102, the two bits 114 and 115 of
higher order of the result of the operation and the subtraction signal
MSUB. The appropriate result is selected by the selection circuit 107 and
further the result Z of the arithmetic, rounding operations and obtaining
the absolute value thereof is outputted.
Next, each of the circuits will now be specifically described. First, the
carry generation and propagation producing circuit 101 is a circuit for
obtaining a carry C.sup..quadrature. generated at each digit in case of
the addition or subtraction of two data X and Y inputted to this circuit
and another carry C.sup.1 generated at each digit in case of the addition
or subtraction of the two data X and Y when there is a carry in the least
significant bit.
In the following description, the number of digits of inputted data is
assumed to be n (n is a positive integer) and the inputs data X and Y are
assumed to be as follows:
X=x.sub.n-1 . . . x.sub.1 x.sub..quadrature. ; and
Y=y.sub.n-1 . . . y.sub.1 y.sub..quadrature..
First, a carry generation function g.sub.i.j and a carry propagation
function p.sub.i.j will be described hereinbelow. Here, it is assumed that
i.gtoreq.j. Further, g.sub.i.j means that if an addition or a subtraction
is effected from the j-th to the i-th bit, a carry or a borrow to a bit of
higher order is generated. On the other hand, p.sub.i.j means that if an
addition or a subtraction is effected from the j-th to the i-th bit, a
carry or a borrow is propagated to a higher order bit when a carry or a
borrow from a bit of lower order occurs. (Hereunder, for simplicity of
description, only the term "carry" is used in the description even in case
that it is applicable to a borrow.) From these definitions, the carry
generation function g.sub.i.i and the carry propagation function p.sub.i.i
of each digit are given by using the values x.sub.i and y.sub.i of each
digit of the input data as follows:
##EQU1##
where MSUB indicates a subtraction signal of which the value is "1" in
case that the arithmetic operation to be effected is subtraction and "0"
in case that the arithmetic operation to be effected is addition. As
described above, p.sub.i.i can be represented by either of the
representations (2a) and (2b). This is because, if a carry from a digit
concerned to a higher order digit is generated, there are two cases that a
carry is included in the carry propagation and that a carry is not
included in the carry propagation. Either of these representations can be
used in generating a carry.
In case where i.gtoreq.j.gtoreq.k, the following equations hold for such i,
j and k:
g.sub.i.k =g.sub.i.j +p.sub.i.j .multidot.g.sub.j-i.k (3)
p.sub.i.k =p.sub.i.j .multidot.p.sub.j.k (4)
From these equations (1) thru (4) above, the carry generation functions
g.sub.i.k and the carry propagation functions p.sub.i.k from the k-th
digit, which is a reference digit, to the i-th digit can be obtained. That
is, the values of the carry generation function g.sub.i.i and the carry
propagation function p.sub.i.i of each digit itself as represented by the
equations (1) and (2) are first obtained from the data of each digit at
which an operation is performed. Further, the carry generation function
and the carry propagation function of each of the digits from a reference
digit to a concerned digit can be obtained by iteratively applying the
equations (3) and (4). Taking addition or subtraction performed at each of
the bits from the reference bit to the concerned bit into considerations
by using the above described definitions of the carry generation function
and the carry propagation function, the carry generated at the i-th digit
is given by the following equation:
c.sub.i =g.sub.i.j +p.sub.i.j .multidot.c.sub.j-1 (5)
Moreover, in case where j=0 in the equation (5), the carry is given by
c.sub.i=g.sub.i..quadrature. +p.sub.i..quadrature. .multidot.c.sub.-1(6)
where c.sub.-1 indicates a carry to the least significant digit. If
c.sub.-1 is "0", a carry c.sup..quadrature..sub.i from each digit in the
operation X.+-.Y can be obtained. Further, if c.sub.-i is "1", a carry
c.sup.1.sub.i from each digit in The operation X.+-.(Y+1) can be obtained.
In the configuration of circuits for generating carry signals
C.sup..quadrature. and C.sup.1, the parts for generating the carry
generation function g.sub.i.j and the carry propagation function p.sub.i.j
can be implemented by the same circuit and thus the most part of the
circuits is used in common. Therefore, only the parts for generating the
carries are made independently with each other. Further, in the carry
generation and propagation producing circuit 101, the interim or temporary
sum S is obtained by computing The exclusive OR of each pair of the
corresponding bits of the input data X and Y. Namely, the i-th bit s.sub.i
of the interim sum S is represented by
s.sub.i =x.sub.i .sym.y.sub.i (7)
This interim sum s.sub.i as well as the carries C.sup..quadrature..sub.1
and C.sup.1.sub.1 is used to evaluate a final sum of the operation.
Next, the sum and difference generating circuits 103 and 104 are described
in detail. These circuits are used to obtain the results of the arithmetic
operations (X.+-.Y) and {X.+-.(Y+1)} from the carries C.sup..quadrature.
and C.sup.1 generated at the time of operations of the input data X and Y
and the interim sum S. For example, the i th bit z.sup..quadrature..sub.i
of the result of the operation (X.+-.Y) is obtained by the following
equation from the carry c.sup..quadrature..sub.i-i in case that the carry
c.sub.-i to the least significant digit is "0".
##EQU2##
Moreover, the i-th bit z.sup.1.sub.i of the result of the operation X
.+-.(Y+1) is obtained by the following equation from the carry
c.sup.1.sub.i-1 to the i-th digit in case the carry c.sub.-1 to the least
significant bit is "1".
##EQU3##
Furthermore, the "carry for rounding" generation circuit 102 will now be
described in detail. This circuit is used to obtain a "carry for rounding"
signal 111, that is, a signal indicating a carry to a digit corresponding
to the least significant bit of the carry generation and propagation
producing circuit 101 which signal is generated when the addition (or
subtraction) the rounding are performed at the digit, at which the
rounding is to be effected, in the operation on the input data including
X, Y and GRS in response to signals indicating part of lower order bits of
the input data X and Y and GRS.
The rounding will now be described. The operand X is the fraction of the
input data of which the exponent is larger than that of the other data Y
and the value of the normalized fraction. Therefore, there are two digit
positions at which the rounding may be effected when the addition is
performed. That is, one of the digits is the digit place where no overflow
results from the addition and the other is the digit place where an
overflow results from the addition. When no overflow occurs, the rounding
is to be effected at the digit place one bit below the least significant
bit of the input data X, that is, at the guard bit. On the other hand,
when an overflow occurs, the rounding is to be effected at the least
significant bit of the data X. Similarly, in case of subtraction, there
are two digit positions where rounding may be performed. In case no
overflow occurs in the subtraction result, that is, the result of the
subtraction is positive and the most significant bit of the subtraction
result is 1, rounding is performed at the guard bit. Further, if the
result of the subtraction is positive and the most significant bit of the
result is 0, rounding is performed at the round bit. At that time, there
is a case that more than one digit from the most significant bit of the
result is 0. Such result of the subtraction is obtained only in case the
data exponents are equal or different by one and thus the values at the
digit places, which are the same with or below the round bit, are 0.
Therefore, in such a case, the processor has only to round the data at the
round bit. There is another case of an overflow occurring in the
substraction result, that is, the substraction result is negative. This
occurs only if the data exponents are equal. Thus, the values at the digit
places, which are the same with or below the guard bit, are 0. Therefore,
in such a case, there is no need to round. As can be understood from the
foregoing description, there are three digit places (hereunder sometimes
referred to simply as "digit places for rounding"), where rounding is to
be preformed, (1) in the addition and substraction operations that is, the
least significant bit of the result (2), the guard bit and (3) the round
bit. There are several methods. For instance, four modes of rounding, that
is, "round to nearest", "round toward+.infin.", "round toward -.infin."
and "round toward 0" are prescribed in the IEEE 754 Floating Point
Arithmetic Standard. Therefore, the processor must only obtain the "carry
for rounding" signals corresponding to the "digit places for rounding" and
the modes of rounding. For example, the "round to nearest" mode, the mode
often employed in the processor, is described in detail herein. The "round
to nearest" method is devised such that the result of rounding the data
according to this method becomes nearest to the accurate result. Thus, if
there are two values nearest to the accurate result, the least significant
bit of the result of the rounding pursuant to this method is set to be 0.
If the "carry for rounding" is that to the least significant bit of the
data X, the "carry for rounding" according to this method is effected by
using the truth table of FIG. 3 in case of addition, or the truth table of
FIG. 4 in case of subtraction In these truth tables,
z.sup..quadrature..sub.1 and z.sup..quadrature..sub..quadrature. indicate
the values of two bits from the least significant bit of the result of the
operation on the data X and Y, respectively. Further, y.sub.G, y.sub.R and
y.sub.s indicate the values at the guard bit, the round bit and the sticky
bit, respectively. Moreover, y.sub.R +y.sub.s indicates the logical OR of
y.sub.R and y.sub.s. Further, CRU denotes a "carry for rounding" signal
corresponding to the rounding effected at the least significant bit that
is the bit z.sup..quadrature..sub..quadrature. ; CRM another "carry for
rounding" signal corresponding to the rounding effected at the guard bit,
that is, the bit y.sub.G ; and CRL still another "carry for rounding"
signal corresponding to the rounding effected at the round bit, that is,
the bit y.sub.R. Further, in case of subtraction, "-1" means a borrow of
1. The "carry | | |
