Packet transmission system and method utilizing both a data bus and dedicated control lines

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This invention pertains to a voice/data packet transmission system and is especially suited for a packet transmission system which must accommodate a variety of different peripheral devices.

BACKGROUND OF THE INVENTION

Voice and data switches are known in the prior art. Packet switching is also known. In the past, however, synchronization for the control of the devices sending and receiving information packets in a voice/data packet switch has been a problem. This problem has been related to the problem of dynamically allocating the packet bandwidth between the various peripheral devices attached to the switch for voice information and data information. Another related factor has been the network interface architecture for the switch. The network interface architectures of past switches have used the same bus for both data and control. When coupled with the problem of dynamically allocating bandwidth on the bus, this network interface architecture has resulted in the switch having a low switching capacity and throughput. These performance problems become even more significant in the context of modern fast packet protocols. It would be desirable, therefore, to provide a voice/data packet switch with an improved network interface architecture.

In a synchronous system a clock signal corresponding to intervals of data transmission is either made directly available to terminals within the network or it is derived from signals sent by the transmitting terminal. In such a system, a master terminal defines the clock information which is derived by slave terminals. Mainframe computer networks which maintain constant communication with slave devices are an example of such networks.

Asynchronous communications differ in that clock information is not provided. Another mechanism must be utilized in order to define the beginning and end of each character or period. In modem networks start and stop bits are utilized by the transmitting modem so that the receiving modem can identify the beginning and end of a transmitted character.

In a TDMA packet network in which each frame contains a plurality of time slots allocated for different users or purposes, it is critical that the receiving terminal be able to properly correlate the beginning of each frame and of each time slot in order to properly decode the transmitted information. It is known in packet systems to utilize a time stamp which is transmitted as part of the packet. For example, see U.S. Pat. No. 4,530,091 and U.S. Pat. No. 4,894,823.

In a wireless packet TDMA system, two types of synchronization is required. First, the beginning of each frame and each time slot (packet) within each frame must be identified. Such identification can be accomplished by transmitting a known data pattern for a predetermined number of bits. This pattern is recognized by the receiving terminal and the beginning of the frame or packet is determined. In a TDMA network in which a master node defines the frame and packet timing for remote terminals, each terminal must be aligned in time relative to the start of the node frame in order to properly receive and transmit information at a predefined time slot within the frame. Problems in acquiring and maintaining this type of synchronization exist especially in a wireless TDMA packet network in which different directional antennas are used for communications. Thus there exists a need for an improved method for maintaining time synchronization in a wireless TDMA packet network in which multiple antennas are utilized.

Packet data networks convey information from an originator to a specified addressee by incorporating the information into packets. Each packet contains a preamble (control data) and information (message data). The preamble typically includes packet network control data, synchronization information, and addressee destination information. The information portion contains part of the total originator's message.

The packet originated by the addressor is typically not directly received by the addressee. The packet may be relayed by several intermediate stations before reaching the final addressee destination. As the transmission speeds of packet networks increase, it becomes increasingly important for relay stations to be able to efficiently handle and process packets.

In a direct method for handling packets, received packets are stored in a memory location. The destination of the packet contained at the preamble is checked as well as other packet network control information. Correct receipt or validation of the control information and the packet data information is checked. Assuming no errors are detected, a new packet corresponding to the received packet is created and stored in a different memory location for transmission. At the appropriate time, the reconstituted packet is retransmitted by the relay station towards its final destination.

Packets are handled in a different manner in an Ethernet local area network. A buffer ring structure comprised of a series of contiguous fixed length byte buffers are utilized for storage of received packets. The beginning and end location of the stored packet is identified by addresses held in a page start and a page stop register. Successive buffers in the ring are utilized to store the packet. Multiple packets can be consecutively stored in the ring structure. The packets are normally removed from the receive buffer ring in FIFO order and are reconstituted for retransmission in memory separate from this ring.

There exists a need for an improved method for organizing and handling packets that minimizes intermediate data transfer to additional memory locations prior to retransmission of the packet

Packet protocols become increasingly inefficient as the amount of data to be transmitted per packet decreases because of the required packet overhead required for each packet. Although short commands can be transmitted from one point to another using packets, a substantial delay exists before the receiving device can act upon the command due to the time requirements of packet transmission and packet disassembly before the command can be forwarded to the destination device.

In a conventional direct control systems each function to be controlled is assigned a separate wire or communication channel which carries a predetermined command from a controller to the device implementing the function. Such systems exist for a variety of applications and are efficient where a limited number of commands are to be transmitted to specific devices. These systems become increasingly complex as the number of commands and devices to be controlled increase. No addressing is required in these systems since each dedicated path has a preassigned single function to control.

There exists a need for a system and method which can carry information utilizing packets while minimizing the inefficiencies related to the transmission of commands to associated devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a first embodiment of a packet/fast packet switch for voice and data.

FIG. 2 shows the network interface bus for the first embodiment.

FIG. 3 shows a packet.

FIG. 4 is a high-level block diagram for the network interface.

FIG. 5 shows a network interface memory map.

FIG. 6 shows address registers.

FIG. 7 shows processor data memory area for the network interface.

FIG. 8 shows network interface base registers.

FIG. 9 shows a status/control register.

FIG. 10 shows a virtual circuit register.

FIG. 11 is a timing diagram showing the network interface control transfer timing.

FIG. 12 is a timing diagram showing a data transfer from a device to the network interface with no additional bytes.

FIG. 13 is a timing diagram showing a data transfer from a device to the network interface with additional bytes.

FIG. 14 is a timing diagram showing a data transfer from the network interface to a device.

FIG. 15 is a timing diagram showing a data transfer from a device to the network interface with a maximum packet size error or a space available error.

FIG. 16 is a timing diagram showing a data transfer from a device to the network interface with a CRC error.

FIG. 17 is a timing diagram showing a data transfer from a device to the network interface with an address error.

FIG. 18 illustrates a format for information in one time slot in a packet environment.

FIG. 19 illustrates the information contained in the packet header as shown in FIG. 18.

FIG. 20 is a diagram representing the packet addressing method and organization in accordance with the present invention.

FIG. 21 illustrates the contents and format for the virtual circuit register as shown in FIG. 20.

FIG. 22 shows the content and format of the queue control block as shown in FIG. 20.

FIG. 23 shows the contents and format of a packet descriptor as shown in FIG. 20.

FIG. 24 shows the contents and format of a buffer descriptor as shown in FIG. 20.

FIG. 25 is a diagram illustrating an exemplary wireless TDMA packet network incorporating the present invention.

FIG. 26 is a block diagram illustrating control modules and user modules utilized in the packet system as shown in FIG. 25.

FIG. 27 is a flow diagram illustrating the generation of frame synchronization packets by the control module.

FIG. 28A illustrates the format of a frame synchronization packet generated by the control module.

FIG. 28B illustrates the format of one frame as defined by the control module.

FIG. 28C illustrates the format of a frame as received by a user module.

FIG. 29 is a flow diagram illustrating the generation of a frame start interrupt by a user module.

FIG. 30 is a flow diagram of the steps used in the user module for determining the frame time synchronization relative to the control module frame.

FIG. 31 is a flow diagram of the steps taken by the user module for adjusting a received frame to maintain time synchronization with the control module frame.

FIG. 32 illustrates a wireless packet communication system suited for incorporating the present invention.

FIG. 33 illustrates a packet format utilized in a preferred embodiment of the present invention.

FIG. 34 is a flow diagram illustrating the transmission of data from a communication controller to a peripheral device.

FIG. 35 is a timing diagram illustrating control signals utilized in accordance with the flow diagram of FIG. 34.

FIG. 36 is a flow diagram illustrating the transmission of data from a peripheral device to the communication controller.

FIG. 37 is a timing diagram illustrating controls utilized to transmit information in accordance with the steps of FIG. 36.

DESCRIPTION OF A PREFERRED EMBODIMENT

Referring now to FIG. 1, it is seen that the Network Interface 105 is the focus of the LAN device (both Node and UM). It connects the various interfaces on the LAN (both cable and radio) to one another and to the Control Processor 107, providing time-division and fast-packet switching. Information is transferred among these interfaces via the Network Interface Memory 111 that is accessible both by the control sections of the Network Interface (both input and output), and by the Control Processor 107. The memory 111 preferably consists of a control memory portion and a data memory portion. Information flow on the LAN side is via the Network Interface Bus (NI-Bus) 101, which is designed to pass data at rates up to, for example, 5 million bytes per second, and to handle the corresponding control information at a similar rate. The microprocessor bus 103 couples the network interface 105 to the control processor 107, hereinafter collectively referred to as the communications controller.

Referring now to FIG. 2, the interaction between the Network Interface Memory 111 and the NI-Bus 101 is shown. The Output Control circuitry 206 of the Network Interface chip 109, sequentially steps through the Control memory 211 and presents address and command bytes to the Control Bus 203. This information controls which device is driving the NI-Bus 101 and which device is listening. All NI-Bus devices, including the Network Interface 105, listen to the Control Bus 203 to determine what the activity is on the Data Bus 201. The Output Control circuitry also sequentially steps through the Data memory. If the Network Interface 105 is driving the bus 101, the information in the Data memory 213 will be output to the Data Bus 201. If the Network Interface 105 is listening to the Data Bus 201, the Input Control 205 will accept the data and put it in the proper area of Network Interface Memory 111. The Network Interface 105 can both listen and drive the bus 101 at the same time. This allows the Network Interface 105 to be put in a loopback mode.

FIG. 3 shows the configuration of a standard packet 300. When a start packet signal (described in a later section) is received from a NI-Bus 101 peripheral (for instance, the radio link 125, 127, 129), the first byte 301 received by the Network Interface is the Virtual Circuit ID. T