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Description  |
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RELATED APPLICATIONS
This application is related to co-pending application for U.S. patent Ser.
No. 08/271,384, filed Jul. 6, 1994, entitled "Integrated Test Circuit",
incorporated herein by reference.
This application is related to co-pending application for U.S. Pat. No.
5,084,874 issued Jan. 28, 1992, entitled "Enhanced Test Circuit",
incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to integrated circuits, and more
particularly to a test cell used in an integrated circuit for providing a
boundary scan test structure.
BACKGROUND OF THE INVENTION
Due to advances in the fields of board interconnect technology, surface
mount packaging and IC density, board level testability is becoming
increasingly complex. The combination of advanced board interconnect
technology, such as buried wire interconnects and double-sided boards,
along with surface mount packaging creates problems for in-circuit testing
of the boards. In-circuit testing, the most common board level testing
method, depends upon the ability to physically probe the nodes of a
circuit board. As board density (the number of ICs on a board) increases,
the process of probing the board using traditional techniques becomes more
difficult, due to the lack of physical access.
As the IC density (amount of logic on a chip) increases, the number of test
patterns required for proper testing likewise increases. In-circuit
testing relies on back-driving techniques to force input conditions to
test a particular IC in a circuit. When such test is being applied to one
IC on a board, neighboring ICs, whose output buffers are tied to the same
nodes, may be damaged. The chance of damaging a neighboring IC increases
with the length of time it takes to perform a test, which is directly
related to the number of test patterns applied, and therefore, related to
the IC density.
Therefore, a need has arisen in the industry to provide a test structure
which provides access to particular ICs on a board, and allows testing of
particular ICs without risk of damage to neighboring ICs.
SUMMARY OF THE INVENTION
In accordance with the present invention, a boundary scan test system is
provided which substantially eliminates the disadvantages and problems
associated with prior testing systems.
The boundary scan test system of the present invention provides
partitioning devices, such as registers, latches, transceivers and
buffers, with boundary scan test ability, in order to provide observation
and control of input to and from combinational logic which does not have
boundary scan test ability. Each of the test devices includes an input
test register for observing inputs to the test device and controlling
outputs to the internal logic (register, latch, buffer or transceiver). An
output test register is provided to observe the output from the internal
logic and to control the outputs to the combinational logic. Similarly,
test cells are used to observe and control signals input to the test
device for control purposes, such as clock signals. The test devices may
include enhanced features such as signature analysis, pseudo-random
pattern generation, and polynomial tap capabilities.
The input and output test register may include a plurality of test cells,
each comprising a first multiplexer connecting a plurality of inputs to a
first memory, responsive to control signals provided by a control bus. The
output of the first memory is connected to a second memory. The output of
the second memory is connected to an input to a second multiplexer along
with one or more other inputs. The second multiplexer is controlled by
another control signal on the control bus. The output of the first memory
and the output of second memory are connected to the first multiplexer as
inputs.
The present invention provides several technical advantages over the prior
art. Because the testing ability is provided in conjunction with
conventional parts such as buffers, latches, registers and transceivers,
the testing features can be easily incorporated into existing designs.
Further, the test devices can be used with a minimal overhead into
existing designs. Further, the test devices are capable of performing test
functions simultaneous with normal operation of the combinational logic,
thereby reducing testing time.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the
advantages thereof, reference is now made to the following descriptions
taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates circuit diagram of an integrated circuit having test
cells disposed at the boundary of the internal application logic;
FIG. 2 illustrates a circuit diagram of preferred embodiment of the test
cell of the FIG. 1;
FIG. 3 illustrates a circuit diagram interconnections between test cells on
an integrated circuit;
FIG. 4a illustrates a circuit diagram of a preferred embodiment of a
bidirectional test cell;
FIG. 4b illustrates a diagram of the bidirectional test cell of FIG. 4a as
disposed within an integrated circuit; and
FIG. 5 illustrates an implementation of the test cell of the present
invention.
FIG. 6 illustrates a test circuit comprising a base test cell with compare
logic circuitry;
FIG. 7 illustrates a test circuit comprising a base test cell with PSA
logic circuitry;
FIG. 8 illustrates a test circuit comprising a base test cell with PSA
logic circuitry and programmable polynomial tap logic circuitry;
FIGS. 9a-b illustrate interconnections between test circuits having
programmable polynomial tap logic circuitry;
FIG. 10 illustrates a bidirection test cell having PSA test circuitry;
FIG. 11 illustrates a bidirectional test cell having PSA test circuitry and
programmable polynomial tap circuitry;
FIG. 12 illustrates a circuit using test devices to observe inputs and
control outputs to and from standard combinational logic;
FIG. 13 illustrates a circuit diagram of a preferred embodiment of a test
device of FIG. 12;
FIG. 14 illustrates a circuit diagram of a test device performing PSA
operations; and
FIG. 15 illustrates a circuit diagram of a test device performing
simultaneous PSA and PRPG operations.
FIG. 16 illustrates the attachment of test cells to a Count Enable Logic
section to allow outputting of a binary count up pattern.
DETAILED DESCRIPTION OF THE INVENTION
The preferred embodiment of the present invention is best understood by
referring to FIGS. 1-5 of the drawings, like numerals being used for like
and corresponding parts of the various drawings.
FIG. 1 illustrates a block diagram of an integrated circuit (IC) 10 having
test cells 12a-h disposed about its boundary to control and observe data
flow through the application logic 14 of the IC 10. The integrated circuit
10 comprises a plurality of pins 16 which provide an electrical connection
between the integrated circuit 10 and other integrated circuits. For
purposes of illustration, the integrated circuit 10 is shown with four
pins receiving input signals, IN1, IN2, IN3 and IN4, and four pins
providing output signals, OUT1, OUT2, OUT3 and OUT4. Other signals to the
chip include a serial data input (SDI), a control bus 17, and a serial
data output (SDO). The input signals IN1-IN4 are connected to input
buffers 18 which output to respective test cells 12a-d. Each test cell
12a-h has its own serial data input and serial data output, enumerated SDI
1-8 and SDO 1-8. In the illustrated configuration, the SDI input to the IC
10 is connected to SDI1 of test cell 12a; the SDI inputs of subsequent
cells 12b-h receive the SDO of the previous cell. Hence, SDO1 is connected
to SDI2, SDO2 is connected to SDI3, and so on. SDO8 is connected to the
SDO pin of the IC 10. The control bus 17 is connected in parallel to each
of the test cells 12a-h.
Each test cell includes a data input (DIN) and a data output (DOUT). For
the input test cells 12a-d, DIN is connected to the output of respective
buffers 18 and DOUT is connected to the inputs of the application logic
14. The inputs of the application logic 14 are enumerated IN1'-IN4',
corresponding to the inputs IN1-IN4. IN1'-IN4' would be the inputs to the
chip were not the test structure provided.
The output from the application logic 14 are referenced as OUT1', OUT2',
OUT3' and OUT4'. The outputs of the application logic OUT1'-OUT4' are
connected to the data inputs (DINs) of the output test cells 12e-h. The
data outputs (DOUTs) of the output test cells 12e-h are connected to
output buffers 20 corresponding to OUT signals OUT1-OUT4.
The test cells 12a-h provide the basis for a great deal of test
functionality within the integrated circuit 10. The SDI enters the IC 10
through test cell 12a and may propagate to each subsequent cell 12b-h,
eventually being output from test cell 12h through SDO8. The serial data
path is used to shift data into and out of each of the test cells 12a-h.
The control bus provides signals for operating each of the test cells 12a-h
during testing, and is described in more detail in connection with FIGS.
2-3. When placed in a test mode, the test cells 12a-h inhibit the normal
flow of data into and out of the IC 10. In the test mode, each test cell
12a-h controls the logic node attached to its output and observes the
logic node attached to its input. For example, in FIG. 1, the test cells
12a-d attached to the four inputs IN1-IN4, can observe the logic levels on
the IN1-IN4 inputs and control the logic levels on the IN1'-IN4' outputs.
Similarly, the test cells 12e-h, connected to the four outputs can observe
the logic levels on the OUT1'-OUT4' inputs and control the logic levels on
the OUT1-OUT4 outputs.
In FIG. 2, a detailed block diagram of an individual test cell 12 is
provided. The test cell 12 has three data inputs: data in (DIN),
observability data in (ODI), and serial data in (SDI). Two data outputs
are provided: data out (DOUT) and serial data out (SDO). The control bus
17 comprises five signals, data input multiplexer selects, A and B, a
register clock signal (CLK), a latch enable (HOLD), and a data output
multiplexer select (DMX).
A first multiplexer 22 receives the ODI and SDI signals, along with the
output of a D-type flip-flop 24 and the inverted output of a D-type latch
26. The output of the multiplexer 22 is connected to the input of the
flip-flop 24. The CLK signal is connected to the flip-flop clock input.
The output of the flip-flop 24 is connected to the input of the latch 26
and also provides the SDO signal. The output of the latch 26 is connected
to the input of a second multiplexer 28 along with the DIN signal. The
HOLD signal is connected to the latch enable. The output of the
multiplexer 28 provides the DOUT signal. The multiplexer 28 is enabled by
the DMX signal.
In operation, the 4:1 multiplexer 22 allows the input to the flip-flop 24
to be selected from one of four possible sources: ODI, SDI, the output of
the flip-flop 24 or the inverted output of the latch 26. The latch 26 can
be controlled to propagate the output of the flip-flop 24 or to hold its
present state, depending upon the logic level applied by the HOLD input.
The 2:1 multiplexer 28 allows the DOUT output to be driven by either the
DIN input or the output of the latch 26, depending upon the logic level
applied by the DMX input. The combination of the 4:1 multiplexer 22,
flip-flop 24, latch 26 and 2:1 multiplexer allows the test cell 12 to
operate in four synchronous modes: load, shift, toggle and idle.
In load mode, the test cell 12 clocks the logic state of the ODI input into
the D flip-flop 24 through the multiplexer 22. The ODI input is coupled to
a signal that is to be observed during tests and, in most cases, the ODI
input will be attached to the same boundary signal that is connected to
the test cell's DIN input. However, the ODI can be connected to other
signals as well. To cause a load operation to occur, the A and B inputs
are set to predetermined levels, allowing the ODI input to be connected to
the flip-flop 24 via the 4:1 multiplexer 22. Normally, the HOLD input to
the latch 26 is low, forcing the latch output to remain in its present
state during a load operation.
In shift mode, the test cell clocks the logic state of the SDI input into
the flip-flop 24 and outputs this logic state via the SDO output. The
shift mode allows the test cells 12 in the boundary scan path to be
interconnected together so that serial data can be shifted into and out of
the boundary scan path. In a boundary scan configuration, the SDI input of
the test cell is coupled to a preceding test cell's SDO output, as shown
in FIG. 1. To cause the shift operation to occur, the A and B inputs are
set to predetermined levels, allowing the SDI input to be connected to the
flip-flop 24 via the 4:1 multiplexer. Normally, the HOLD input to the
latch 26 is kept low, forcing the latch output to remain in its present
state during the shift operation.
In toggle mode, the output of the flip-flop 24 toggles between two logic
states at the rate of the CLK input, regardless of the condition of the
SDI or ODI inputs. In this configuration, the HOLD input is set to a high
logic level to enable the latch 26 and the A and B inputs are set such
that the inverted output of the latch 26 is propagated to the flip-flop
24. With the control input set in this manner, a feedback path is formed
from the output of the flip-flop 24 to the input of the latch 26 and from
the inverted output of latch 26 to the input of the flip-flop 24. Because
of the data inversion at the inverted output of the latch 26, the opposite
logic state is clocked into the flip-flop 24 on each CLK input, creating
the toggle effect.
In idle mode, the test cell remains in present state while the CLK is
active, regardless of the condition of the SDI or ODI inputs. In this
configuration, the output of the flip-flop 24 is passed through the 4:1
multiplexer 22; hence, the input of the flip-flop 24 is connected to its
output, allowing the present state of the flip-flop 24 to be refreshed on
every clock input.
The test cell 12 can be in either "normal" mode or "testing" mode. In
normal mode, the test cell 12 provides the data path through which the
inputs (IN1-IN4) and output (OUT1-OUT4) propagate freely. The normal mode
is achieved by setting the DMX signal such that the DIN signal passes
through the multiplexer 28 to DOUT. While in the normal mode, the test
cell 12 can operate in any of the four synchronous modes (load, shift,
idle or toggle) without disturbing the normal operation of the IC 10.
A control signal can be issued via the A and B inputs to cause the test
cell 12 to execute a load operation. The load operation causes the test
cell 12 to capture the logic level present on the ODI input. Once the data
has been captured, it can be shifted out of the test cell 12 by performing
a shift operation. The load operation occurs synchronous with the CLK
input. Following the shift operation, the test cell 12 typically returns
to the idle mode. This capability allows the test cell 12 to sample an
IC's input and/or output boundary signals and shift the sample data out
for inspection during normal operation of the IC. The ability to sample
boundary data during normal operations allows the test cell 12 to verify
the functional interactions of multiple ICs on a circuit board without
having to use expensive test equipment and external test probes.
Also while in normal mode, control can be issued via the DMX input to cause
the test cell 12 to insert a predetermined test data bit into the normal
input/output boundary path of the IC. The test data bit to be inserted is
shifted into the flip-flop 24 via a shift operation. The HOLD input to the
latch 26 is set high to allow the test data in the flip-flop to pass
through the latch and input to the 2:1 multiplexer 28. To insert the test
data, the DMX input is set to a level causing the multiplexer to propagate
the test data from the output of the latch 26 to the DOUT output. After
the test data has been inserted, the DMX input is switched to cause the
2:1 multiplexer 28 to propagate normal data from DIN to DOUT.
The ability to insert test data during normal operations allows the test
cells to modify the normal behavior of one or more ICs in a circuit. One
particular usage of the insert capability is to propagate a fault into the
input and/or output boundary of one or more ICs of a circuit board to see
if the fault can be detected and corrected. In order to perform the sample
and insert test functions during normal operation, the test cell 12 must
receive control via the control bus 17 at a qualified point in time.
The test cell 12 can also perform a self-test while in the normal mode
without disturbing the normal operation of the IC 10. A shift operation
may be performed to initialize the flip-flop 24 to a known state.
Following the shift operation, control is issued to cause the test cell 12
to enter the toggle mode for one CLK transition. During this transition,
the flip-flop is loaded with the inverse of its state. Following this
inversion of data, another shift operation is performed to retrieve the
contents of the flip-flop 24 and verify the inversion operation. This test
verifies the combined operation of each of the test cell's flip-flop 24,
4:1 multiplexer 22, and latch 26, along with the integrity of the overall
boundary scan path.
In the test mode, the test cell 12 inhibits the normal flow of data from
the DIN input to the DOUT output. The test mode is entered by setting the
DMX input to a level such that the output of the latch 26 is connected to
the DOUT output. Normally, prior to entering the test mode, the test cell
12 will have been prepared to output an initial test pattern, via a shift
pattern. Also, the test cell 12 will usually be in an idle state and the
HOLD input to the D latch will be set low, such that its present output is
maintained.
While in the test mode, a load operation may be executed, causing the test
cell 12 to capture the logic level present on the ODI input. The load
operation occurs synchronous with the CLK input. During a load operation,
the HOLD input is set low, such that the D latch remains in its present
state. Likewise, the DOUT output remains in its present state, since it is
driven by the latch output.
Following the load operation, a shift operation is performed, causing the
test cell 12 to shift data through the flip-flop 24 from the SDI input to
the SDO output. The shift operation allows the test cell to shift out the
data captured during a previous load operation and shift in the next
output test data to apply to the DOUT output. The shift operation occurs
synchronous with the CLK input. During a shift operation, the HOLD input
is held low, such that the output of the latch 26 remains in its present
state. Likewise, the DOUT output remains in its present state, since it is
driven by the latch output.
Following the load and shift operation sequence, the test cell 12 returns
to the idle mode and the HOLD input will be set high, such that the latch
26 is updated with the new output test data residing in the flip-flop 24.
When the latch 26 is updated, the new output test data is applied to the
DOUT output. Following the update operation, the HOLD input is set low
such that the latch 26 remains in its present state during subsequent load
and shift operations.
The HOLD, load, shift, and update/apply sequence is repeated during
boundary scan testing of the internal and external logic elements attached
to the ICs test circuitry. By providing separate memory elements for
output test control (i.e., latch 26) and input test observation and
shifting (i.e., flip-flop 24), the test cell 12 can test the internal
logic of an IC 10 and the external logic and/or wiring interconnects
attached to the IC's boundary simultaneously. This feature reduces test
time significantly.
While in the test mode, the test cell 12 can perform a toggle operation.
Since the output of the latch 26 is coupled to the DOUT output during test
mode, the DOUT output can be made to toggle at the rate of the CLK input
when the toggle operation is performed. The advantage of using a D latch
instead of a second D flip-flop is that the D latch can be made to
propagate the Q output of the D flip-flop by setting the HOLD input high.
The toggle mode can be used as a simple test pattern generator or for
measuring parameters of the output buffers 20 of the IC 10.
FIG. 3 illustrates a simplified view of an IC design having one input (IN),
one output (OUT), an application logic section 14, and a boundary scan
path consisting of two test cells 12i and 12j. The input to the
application logic 14 is connected to the output of the 2:1 multiplexer 28
of test cell 12i, and is denoted as IN'. The output of the application
logic is denoted as OUT' and is connected to the DIN and ODI signals of
the test cell 12j.
The IN input enters the DIN input of the input test cell 12i, passes
through the 2:1 multiplexer 28, and is output to the application logic 14
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