Variable delay circuit and clock signal supply unit using the same

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BACKGROUND OF THE INVENTION

This invention relates to a variable delay circuit suitable for use in an information processor such as a computer, and a clock signal supply unit using the same variable delay circuit.

Examples of the clock signal supply unit are disclosed in U.S. Pat. No. 5,184,027 issued on Feb. 2, 1993 and U.S. Pat. No. 5,043,596 issued on Aug. 27, 1991, both assigned to Hitachi Ltd., as is as the present patent application; on JP-A-2-168308, filed on Sep. 13, 1989 by Hitachi Ltd.

In the clock signal supply units disclosed in these publications, a source signal and a reference signal from a clock generator are supplied to destinations which require clock signals. Each destination has a variable delay circuit and uses this variable delay circuit to adjust the source clock signal so as to be in phase with the reference signal.

In order for a clock signal having high phase accuracy to be available for the destinations, it is required to raise the phase accuracy of the reference signal and compare the phases of the clock signal and the reference signal with high accuracy. In the above-mentioned publications, there are revealed reference signal supply circuits and methods as well as phase comparator circuits and methods which meet the above-mentioned requirement.

In JP-A-63-106816, filed on Oct. 24, 1986 by NEC Corporation, there is shown a method for adjusting the phase of the clock signal by a variable delay circuit. In this laid-open publication, no consideration has been made of the automatic phase adjustment for the clock signal, nor the variable range and the resolution in the adjustment of the variable delay circuit.

In JP-A-2-254809, filed on Mar. 28, 1989 by Mitsubishi Electric Corporation, there is shown a method for controlling a delay time by connecting a plurality of transfer gates in the clock signal transmission line and controlling the number of the conducting transfer gates. In this method disclosed in this laid-open publication, if one wishes to increase the phase adjusting range, it is necessary to increase the number of transfer gates directly connected to the clock signal transmission line, which results in an increase in the minimum delay time.

In the phase adjusting device in the conventional clock signal supply unit, immediately after the phase adjustment a clock signal with high phase accuracy can be obtained, but thereafter if the temperature of the device changes, the phase of the clock signal changes, too. Therefore, unless this device is used in a system subject to a limited range of temperature change in steady state (an expensive system equipped with a water cooling device, for example), the phase accuracy deteriorates if there is no means that follows up changes in temperature in controlling the delay time.

JP-A-2-168308 discloses an example of a variable delay circuit which can follow changes in temperature. However, if one wishes to increase the follow-up range of temperature change without coarsening the resolution (a difference between a delay time that occurs when a control signal is applied and a delay time that occurs when this control signal is varied by one step) in delay time control, in this variable delay circuit, it is necessary to increase the stages of selectors, which results in an increase of the minimum delay time (a delay time that is produced by applying such a control signal is applied so as to minimize the delay time of the variable delay circuit). A result of this is an increase in the range of phase change in relation to a given change in temperature. In order to correct this, a wider follow-up range is required. In consequence, when the technique disclosed in JP-A-2-168308 is used to follow up temperature changes, there is no other choice but to coarsen the resolution in phase control to some extent.

In the technique disclosed in JP-A-2-168308, to prevent a spike-like noise from occurring in the clock signal output, flip-flops are used to inhibit the switch-over timing of the selector from being superposed on a rise or a fall of the clock signal. However, for such flip-flops, a high-speed circuit is required which can follow up the frequency of the clock signal.

With a variable delay circuit used in the conventional clock phase adjusting device, increasing the variable range of the variable delay circuit requires an increase in the stages of selectors, resulting in an increase in the minimum delay time. The skew increases' which is attributable to variations in the manufacture of semiconductor devices constituting this variable delay circuit. To correct this, a greater variable range is required. Particularly in a CMOS circuit widely used in a less expensive system, this problem is conspicuous because of the great variations in delay time.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a novel variable delay circuit meeting the conflicting requirements of reducing the minimum delay time as much as possible and obtaining a wider variable range of the delay time, and also to provide a clock signal supply unit using this variable delay circuit.

Another object of the present invention is to provide a novel variable delay circuit capable of varying the delay time without allowing noise to occur while a clock signal is supplied, and additionally to provide a clock signal supply unit using this variable delay circuit.

In the variable delay circuit of the present invention, which includes a delay device having a plurality of delay units connected successively, only some of the delay units of the delay device are connected to the signal transmission line, and in compliance with a control signal given to control input terminals attached respectively to the plurality of the delay units, the plurality of delay units are activated or inactivated to control the delay time.

The clock signal supply device of the present invention comprises a clock signal generator for generating a first clock signal and a reference signal, and a phase adjusting device for adjusting the phase of the first clock signal based on a phase difference between the first clock signal and the reference signal, and outputting this phase-adjusted signal as a second clock signal, wherein the phase adjusting unit includes a first variable delay circuit capable of a delay operation in the initial adjustment of the first clock signal, a second variable delay circuit capable of changing a delay time after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

Other objects of the present invention will become apparent from the description made with reference to the following drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an embodiment of a variable delay circuit according to the present invention;

FIG. 2 is a circuit diagram showing another embodiment of a variable delay circuit according to the present invention;

FIG. 3 is a circuit diagram showing a further embodiment of a variable delay circuit according to the present invention;

FIG. 4 is a circuit diagram showing yet another embodiment of a variable delay circuit according to the present invention;

FIG. 5 is a circuit diagram showing a still further embodiment of a variable delay circuit according to the present invention;

FIG. 6 is a circuit diagram showing an example of a selector circuit used in a variable delay circuit according to the present invention;

FIG. 7 is a circuit diagram showing an embodiment of a control circuit for controlling a variable delay circuit according to the present invention;

FIG. 8 is a circuit diagram showing an additional embodiment of a variable delay circuit according to the present invention;

FIG. 9 is a circuit diagram showing an example of a variable delay circuit used as a part of the circuit of FIG. 8;

FIG. 10 is a circuit diagram showing another embodiment of a control circuit for controlling a variable delay circuit according to the present invention;

FIGS. 11A and 11B are circuit diagrams showing embodiments of parts of the circuit of FIG. 10;

FIG. 12 is a circuit diagram showing an embodiment of a clock phase adjusting device according to the present invention;

FIG. 13 is a circuit diagram showing an embodiment of a first part of the circuit of FIG. 12;

FIG. 14 is a circuit diagram showing an embodiment of the first part of the circuit in FIG. 13;

FIG. 15 is a circuit diagram showing an embodiment of a second part of the circuit of FIG. 13;

FIG. 16 is a circuit diagram showing an embodiment of the second part of the circuit of FIG. 12;

FIG. 17 is a circuit diagram showing an embodiment of another part of the circuit of FIG. 16;

FIG. 18 is a circuit diagram showing another embodiment of the second part of the circuit of FIG. 12;

FIG. 19 is a circuit diagram showing a further embodiment of the second part of the circuit of FIG. 12;

FIG. 20 is a circuit diagram showing an embodiment of a part of the circuit of FIG. 19;

FIG. 21 is a circuit diagram showing yet another embodiment of the second part of the circuit in FIG. 12;

FIG. 22 is a circuit diagram showing a still further embodiment of the second part of the circuit of FIG. 12;

FIG. 23 is a circuit diagram showing an embodiment of a part of the circuit of FIG. 22;

FIG. 24 is a circuit diagram showing an additional embodiment of the second part of the circuit of FIG. 12;

FIG. 25 is a circuit diagram showing another embodiment of the second part of the circuit of FIG. 12;

FIG. 26 is a circuit diagram showing a still further embodiment of the second part of the circuit of FIG. 12;

FIG. 27 is a circuit diagram showing an embodiment of a part of the circuit of FIG. 26;

FIG. 28 is a circuit diagram showing another embodiment of the second part of the circuit of FIG. 12;

FIG. 29 is a circuit diagram showing a further embodiment of the second part of the circuit of FIG. 12;

FIG. 30 is a circuit diagram showing yet another embodiment of the second part of the circuit of FIG. 12;

FIG. 31 is a circuit diagram showing another embodiment of a part of the circuit of FIG. 27;

FIG. 32 is a diagram showing signal waveforms in the circuit of FIG. 31; and

FIG. 33 is a circuit diagram showing an embodiment of a selector circuit used in a clock signal phase adjusting device according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a first embodiment of the variable delay circuit according to the present invention. In FIG. 1, reference numerals 101 to 104 denote PMOS devices used as transfer gates, 111 to 114 denote NMOS devices used as transfer gates, 121 and 122 denote buffer circuits to prevent effects of waveform distortions due to load variations from being transmitted to other circuits, and 131 denotes a capacitive device constituting a part of the load. Numeral 151 denotes an input terminal of a clock signal, 100 denotes a clock signal transmission line, 152 denotes an output terminal of the clock signal, and 161 to 164 denote control terminals for inputting control signals. When a transfer gate array as shown in FIG. 1 is formed on a common semiconductor substrate, stray capacitances 11, 12, 13, 14 exist at all junctions between PMOS transistors and NMOS transistors as indicated by the dotted lines. When the transfer gates formed by the PMOS transistors and the NMOS transistors are cut off, only the stray capacitance 11 is connected between the signal transmission line 100 and ground. When all the transfer gates are conducting, all the stray capacitances 11, 12, 13, 14 and the capacitor 131 are connected between the signal transmission line 100 and ground. In this circuit, if the control signals applied to the control terminals are all "high", all transfer gates conduct, thus maximizing the load on the buffer circuit 121, and making the signal propagation time from the signal input terminal 151 to the signal output terminal 152 the longest. However, if only the control signal applied to the control terminal 164 is switched to the low level, only the transfer gates 104, 114 are cut off, and as a result, the load on the buffer circuit 121 is lessened by the amount of power consumption corresponding to the drain-side gate capacitances of the MOS devices 104, 114 and the capacitance of the capacitive device 131. Therefore, the signal propagation time from the input terminal 151 to the output terminal 152 is shortened, accordingly.

Similarly, if the control signal applied to the control terminal 163 is switched to the low level, the transfer gates 103, 113 are cut off, and the load on the buffer circuit 121 is further lessened by the amount of power consumption corresponding to the gate capacitances on the source sides of the MOS devices 104, 114. The signal propagation time from the input terminal 151 to the output terminal 152 is further decreased in proportion to the increased reduction of load. Likewise, when the control signal applied to the control terminal 161 is switched to the low level, the signal propagation time from the input terminal 151 to the output terminal 152 becomes the shortest. It ought to be noted here that the signal propagation time at this time is determined only by the basic delay times and the load drive capacity of the buffer circuits 121, 122, the gate capacitances of the MOS devices 101, 111, and the stray capacitance 11, regardless of the number of stages of transfer gates. More specifically, if the circuit in FIG. 1 is used, even though the number of transfer gates is increased to decrease the resolution in delay time control, the minimum delay time can be set at a fixed level, leaving no chances of its increase. Moreover, in the circuit of FIG. 1, no circuit is provided to switch over the clock signal transmission line 100 itself as it was used in the conventional variable delay circuit. Therefore, there is no possibility of a spike-like noise occurring unless the control signals applied to the gate electrodes of the transfer gates 101 to 114 are switched over extremely quickly. Therefore, it is not necessary to provide a control circuit which operates at the same speed as or faster than the buffer circuits 121, 122 through which the clock signal propagates.

Incidentally, the transfer gates can be formed by independent PMOS devices or NMOS devices instead of combinations of PMOS devices and NMOS devices used in the embodiment in FIG. 1. In using combinations of PMOS devices and NMOS devices, there is an advantage that delay characteristics can be obtained which are uniform at the rising and falling edges of a clock pulse. Moreover, the transfer gates need not necessarily be formed by PMOS and NMOS devices only, but can be formed by other switching devices. Generally, the transfer gates can cause the signal line to conduct or cut off bidirectionally by signals applied to the control terminals.

FIG. 2 shows a second embodiment of the variable delay circuit according to the present invention. In FIG. 2, reference numerals 101 to 108 denote PMOS devices used as the transfer gates, 111 to 118 denote NMOS devices used as the transfer gates, 121 and 122 denote buffer circuits to prevent the effects of waveform distortions due to load variations from being transmitted to other circuits, and 131 and 132 denote capacitive devices constituting a part of the load. Numeral 151 denotes a clock signal input terminal, while 152 denotes a clock signal output terminal, and 161 to 168 control terminals for inputting control signals. The circuit in FIG. 2 is formed by arranging in parallel the transfer gates of the circuit of FIG. 1, and this circuit changes the magnitude of the load by opening and closing the transfer gates in the same manner as in the circuit of FIG. 1 to thereby control the delay time. In the circuit in FIG. 1, when the number of stages of transfer gates is increased to more than a certain number, the series resistance of the transfer gates becomes so large that the load remote from the buffer circuit 121 is unable to contribute much to switching over the delay time. In this embodiment, this problem is circumvented by arranging the transfer gates in parallel.

FIG. 3 shows a third embodiment of the variable delay circuit according to the present invention. In FIG. 3, reference numerals 101 to 108 denote PMOS devices used as the transfer gates, 111 to 118 denote NMOS devices used as the transfer gates, 121 and 122 denote buffer circuits to prevent the effects of waveform distortions due to load variations from being transferred to other circuits, 123 denotes a buffer circuit to avoid a decrease in the signal amplitude in this variable delay circuit, and 131 and 132 denote capacitive devices constituting a part of the load. Numeral 151 denotes a clock signal input terminal, while 152 denotes a clock signal output terminal, and 161 to 168 denote control terminals for inputting control signals.

In the circuits shown in FIGS. 1 and 2, if the variable range of delay time is made greater than about 1/4 of the period of the clock signal, the output amplitude of the buffer circuit 121 begins to decrease, and if the variable range is made greater than about 1/2 of the period of the clock signal, the clock signal becomes unable to be transmitted to the buffer circuit 122. In order to circumvent this problem, a buffer circuit 123 is interposed between the buffer circuits 121 and 122. For example, by setting the delay time variable range at 1/4 of the period of the clock signal between the buffer circuits 121 and 123, and between the buffer circuits 123 and 122, respectively, the delay time variable range as a whole can be made 1/2 of the period of the clock signal without causing any large decrease in the signal amplitude in the variable delay circuit. Since the load drive capacity of the buffer circuit 121 generally differs between the rise and fall of the signal, if the load is made heavier in the circuits of the first and second embodiments, the duty ratio of the clock signal changes while the signal propagates from the input to the output of the circuit. In contrast, when the circuit of this embodiment is used, a resulting effect is that the change of the duty ratio can be corrected by substantially equalizing the magnitude of the load before and after the buffer circuit 123.

FIG. 4 shows a fourth embodiment of the variable delay circuit according to the present invention, which is a combination of the circuit of FIG. 2 with the circuit of FIG. 3. To be more specific, a buffer circuit 123 is disposed between the buffer circuits 121 and 122, and as the load, the buffer circuits 121 and 123 are connected with multiple gate arrays, arranged in parallel, each gate array including a plurality of transfer gates connected in series. As shown in FIG. 4, in this embodiment, each capacitive device 131 comprises a MOS device with the source and drain electrodes connected to a power source and a MOS device with the source and drain electrodes connected to the ground. Also, it is possible to obtain a variable delay circuit with a greater variable range by making ready a plurality of variable delay circuits as shown in FIGS. 1 to 4, and connecting them in as many stages as desired.

According to the embodiments of the present invention shown in FIGS. 1 to 4, by controlling the transfer gates connected to the buffer circuits in the clock signal transmission line 100, the load on the buffer circuits is changed to vary the delay time. Thus, it becomes possible to finely set the resolution in delay time control without increasing the minimum delay time. And, since there is no need to temporarily cut off the clock signal transmission line 100 itself when varying the delay time, a spike noise or the like does not occur attending a change of delay time.

FIG. 5 shows a fifth embodiment of the variable delay circuit according to the present invention. In FIG. 5, reference numerals 501 to 508 denote selector circuits, and 521 to 529 denote inverter circuits for setting the polarities of the clock signal. Numeral 551 denotes an input terminal of a clock signal, 552 denotes an output terminal of the clock signal, and 561 to 568 denote control terminals for inputting control signals.

In this embodiment, when all selector circuits receive control signals that cause them to select the inputs on the lower side shown in FIG. 5 (the node 511 for the selector circuit 501, for example), a clock signal applied to the input terminal 551 passes through all inverter circuits and all selector circuits, and is output to the output terminal 552. The variable delay circuit set in this state produces the maximum delay time. At this time, if the control signal applied to the control terminal 568 is switched over, the selector circuit 508 selects a signal from the inverter 527, so that a signal which does not pass through the inverters 528, 529 is output. Therefore, the signal propagation time is reduced by delay times of the inverter circuits 528, 529.

In addition, if the control signal applied to the control terminal 567 is switched over, the selector circuit 507 selects a signal from the inverter circuit 526, a signal which does not pass through the inverter circuit 527 and the selector circuit 508 is output. Consequently, the signal propagation time is further reduced accordingly. Similarly, if the control signal applied to the control terminal 561 is switched over, a signal which passes through no circuit other than the selector circuit 501 is output. At this time, the signal propagation time from the input terminal 151 to the output terminal 152 is determined only by the delay time of the selector circuit 501 regardless of the number of selector circuits, and is, in other words, the shortest. More specifically, according to this embodiment, by selecting as the channel of a clock signal either a channel of a fixed delay time or a channel of a variable delay time, it is possible to arbitrarily design the maximum delay time without increasing the minimum delay time.

FIG. 6 is a circuit diagram showing an example of a selector circuit 501 as a component part of the delay circuit in FIG. 5. In FIG. 6, reference numerals 601 to 604 denote PMOS devices, 611 to 614 denote NMOS devices, and 621 denotes an inverter circuit. Numeral 551 denotes a clock signal input terminal, 552 denotes a clock signal output terminal, 561 denotes a control terminal for inputting a control signal, 511 denotes a terminal to be connected to the output of the selector circuit 502 in FIG. 5, and Vdd denotes a terminal connected to a power source of a positive polarity. In this selector circuit, when a low-level control signal is applied to the control terminal 561, the PMOS device 604 and the NMOS device 613 are cut off, and the PMOS device 603 and the NMOS device 614 are put into the conducting state. Therefore, the signal which appears at the output terminal 552 is determined by the states of the PMOS device 602 and the NMOS device 612.

In other words, a signal of a polarity inverted with respect to the polarity of the signal applied to the input terminal 551 appears at the output terminal 552. This is not affected by the signal applied to the input terminal 511. Conversely, if a high-level control signal is applied to the control terminal 561, the PMOS device 603 and the NMOS device 614 are cut off, and the PMOS device 604 and the NMOS device 613 are put into conduction. In this case, a signal of an inverted polarity of the polarity of the signal applied to the input terminal 511 appears at the output terminal 552, and this is not affected by a signal applied to the input terminal 551. In this manner, the circuit 501 shown in FIG. 6 operates as a selector circuit.

The other selector circuits in FIG. 5 can be formed in the same circuit configuration. When clock signals are sent by transmission of differential signals of opposite polarity, a selector circuit such as shown in FIG. 23 in JP-A-2-168308 can be used. Note that when clock signals are sent in the differential signal transmission, the inversion or noninversion of the polarity can be set freely only by a way of connection, and therefore, obviously, the inverter circuits 521 to 528 in FIG. 5 become unnecessary.

FIG. 7 shows an embodiment of a control circuit for generating a control signal applied to the variable delay circuits in the first to fifth embodiments described above.

In FIG. 7, reference numerals 901 to 906 denote flip-flop circuits. Numerals 961 to 966 denote output terminals of control signals applied to the variable delay circuit. To control the delay time in the variable delay circuits in FIGS. 1 to 4, output terminals 961 to 966 are connected to the control terminals 161 to 166, and to control the delay time of the variable delay circuit in FIG. 5, the output terminals 961 to 966 are connected to the control terminals 561 to 566.

Numeral 971 denotes a terminal for inputting an UP signal to increase the delay time, while 981 denotes a terminal for inputting a DOWN signal to decrease the delay time, and 991 denotes a terminal for inputting, for example, a clock signal of a low frequency, to operate this control circuit. In this control circuit, when l