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Description  |
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FIELD OF THE INVENTION
The invention relates to boundary scan testing of electronic circuit
networks having individual integrated circuit chips testable by the IEEE
1149.1 Standard and other individual integrated circuit chips not testable
by the IEEE 1149.1 Standard, but testable by Level Sensitive Scan Design.
Modern boundary scan testing technology consists of IEEE 1149.1 Standard
boundary scan testing and other methodologies, many of which are
incompatible with the IEEE 1149.1 Standard. Generating test patterns for
both types of boundary scan testing, as when both types of integrated
circuit chips are present in the same circuit network, i.e., on the same
printed circuit board or card, has heretofore been accomplished only
through special custom programming. According to the system and method of
the invention described herein, commonly available software can be used to
automatically generate test patterns for circuit networks with mixed
integrated circuit types.
BACKGROUND OF THE INVENTION
Boundary Scan Testing
Boundary scan testing is described in many papers, including R. W. Bassett,
M. E. Turner, J. H. Panner, P. S. Gillis, S. F. Oakland, and D. W. Stout,
"Boundary Scan Design Principles for Efficient LSSD ASIC Testing," IBM
Journal of Research and Development, Vol. 34, No. 2/3, March/May 1990, pp.
339-354.
Heretofore functional testing of printed circuit boards has been carried
out by test fixtures that facilitated "bed of nails" contact of the
individual integrated circuit leads. The development of high pin count
devices and surface mount technology, with high populations of high I/O
density, grid array components, on both sides of a card or board, has made
bed of nails testing prohibitively expensive. To allow bed of nails
testing, surface mount packages must either sacrifice their high I/O
advantage and chip density, or even more complex and costly testing
fixtures must be used.
Boundary scan testing provides an alternative to bed of nails testing.
Boundary scan testing provides board signal node access while avoiding in
circuit test fixturing. Boundary scan techniques replace the physical
access points needed for in-circuit testing with equivalent logical access
points. These equivalent logical access points are the boundary scan
latches. The boundary scan latches correspond to the signal I/O pins of
each component.
The board testing applications of boundary scan methodology have led to
development of many boundary scan testing technologies, including Level
Sensitive Scan Design devices and IEEE 1149.1 Standard devices.
IEEE 1149.1 Standard Boundary Testing
The IEEE 1149.1 Standard requires a chip architecture where each conforming
chip has a standard Test Access Port (TAP) designed and incorporated as an
internal component thereof. This integral Test Access Port is operated by
means of a four pin test signal interface. The signal pins of the Test
Access Port comprise a Test Clock (TCK), a Test Mode Select (TMS), a
serial Test Data Input (TDI), and a serial Test Data Output (TDO).
The basic elements of the IEEE 1149.1 Standard architecture are illustrated
in FIGS. 1 through 6. FIG. 1 shows a schematic overview of an IEEE 1149.1
Standard integrated circuit chip, with peripheral boundary scan cells,
internal system logic, and the Test Access Port, with the TCK and TMS
inputs to the test access port, the TDI input to the Instruction and
Bypass Registers, the multiplexer, and the TDO output from the test access
port. FIG. 2 shows an individual IEEE 1149.1. Standard Boundary Scan Cell.
FIG. 3 shows the IEEE 1149.1. Standard boundary scan architecture and
logic flow. FIG. 4 shows all of the IEEE 1149.1 Standard Data Register,
and FIG. 5 shows the Instruction Register outputs.
The Test Access Port is controlled by an internal, synchronous, finite
state machine with sixteen states. Its behavior is controlled by the
values placed on the TMS input at the time of a rising edge transition on
the TCK signal. The state machine can be initialized to a known reset
state within five clock signals.
The Test Access Port contains a serially loadable instruction register and
a one bit scan bypass register.
According to the IEEE 1149.1 Standard all component signal I/O pins, other
then test signal interface pins, must be directly connected to logically
adjacent boundary scan cells. The boundary scan cells must be
interconnected to form a single boundary scan shift register operated
under Test Access Port control.
Under the IEEE 1149.1 Standard there are three mandatory instructions which
must be supported: BYPASS, EXTEST, and SAMPLE. BYPASS permits board level
shift register reconfiguration. This allows more efficient scanning by
using the Bypass Register to bypass a module's boundary scan register when
the module does not need to be included in a certain test. EXTEST permits
test of board level interconnection wiring using the boundary scan
register. SAMPLE permits monitoring of signals entering and leaving a
component during normal system operation using the boundary scan register.
The basic boundary scan cell design is shown in FIG. 1.
Level Sensitive Scan Design Boundary Testing
Level Sensitive Scan Design integrated circuit chips can be fully tested
without contacting all of the product pins simultaneously. In a Level
Sensitive Scan Design integrated circuit chip all of the latches are part
of a scannable chain. Boundary scan testing adds the requirement that each
driver and receiver must have an associated latch that is also part of a
scannable chain. With boundary scan Level Sensitive Scan Design it is
possible to directly control and observe the state of all drivers,
receivers, and latches on a chip while contacting only scan pins,
including boundary scan pins, clocks, and LSSD control pins. Through the
use of Level Sensitive Scan Design a low pin count tester can test all of
a chip's area except for chip circuitry outside the boundary scan latches.
LSSD testing also allows for AC testing.
LSSD testing is based upon logical partionability at Shift Register Latch
boundaries that correspond closely to component signal I/O pin boundaries.
In LSSD a logic network consisting of one or more conforming components is
partitioned into two distinct, independently testable regions. The first
region consists of the internal functional logic enclosed by the Boundary
Shift Register Latches on each component. The second region consists of
the component pins and any logic external to the Boundary Shift Register
Latches, such as the off-chip driver and receiver circuits attached to the
I/O pins and their interconnect wiring between board components.
A Level Sensitive Scan Design device is shown schematically in FIG. 6.
First to be noted is that in a LSSD device there is a distinction between
pins required to perform specific testing functions and those not having
such a requirement. LSSD system clocks, scan clocks, scan gates, and scan
data inputs, that is, the inputs required for LSSD scanning and clocking
operations, are categorized as Test Function Primary Inputs (TFPI's). LSSD
scan data outputs are characterized as Test Function Primary Outputs
(TFPO's). All other data and input pins are classified as Data Primary
Inputs (Data PI's) and Data Primary Outputs (Data PO's).
LSSD devices are subject to the following design rules:
1. There must be a Test Function Primary Input (TFPI) sensitizing condition
consistent with the LSSD scan state and scan sequence that makes all
internal logic signals and all embedded memory controllable and observable
using only the Test Function Primary Inputs (TFPI's), the Test Function
Primary Outputs (TFPO's), and the Shift Register Latches (SRL's). This
excludes data PI's and data PO's from being used during any internal
testing operations.
2. There must be a Test Function Primary Input (TFPI) sensitizing condition
consistent with the LSSD scan state and scan sequence that makes all
external logic signals including all I/O pins (TFPI's, data PI's, TFPO's,
and data PO's) controllable and observable using only the Boundary Shift
Register Latches (SRL's) and the I/O pins themselves. This excludes any
internal Shift Register Latches, i.e., those not designated as Boundary
Shift Register Latches, from being used during external testing
operations.
3. All logic signals must be included in either or both the internal region
or the external region, and each possible value of a signal must be
testable, that is simultaneously controllable and observable, under at
least two of the sensitizing conditions. This states that it must be
possible to fully test all of the logic signals using one of the above
rules.
These three design rules permit two basic BSRL arrangements for data PI's
and data PO's. The data input structures are shown in FIGS. 7 and 8. The
corresponding data output structures are shown in FIGS. 9 and 10. FIGS. 8
and 10 show circuits that must be classified as TFPI's in order to satisfy
controllability and observability conditions of the above design rules.
FIGS. 9 and 10 illustrate the implicit requirement that off-chip
driver-enable signals fed by internal system logic must be intercepted by
BSRL structure. The circuits shown in FIGURES also show that a second
driver-enable output that is controlled by a TFPI. This additional
driver-inhibit control is included for board testing. It provides a test
function input on each component that can be used by the board designer to
prevent contention between three-state drivers on multi-source board
signal nodes during LSSD scanning operations.
Level Sensitive Scan Design devices are testable under the LSSD standard
without incorporation of the IEEE 1149.1 Standard elements, such as the
Test Access Port (including TCK, TDI, TMS, TDO, and TRST I/O connections),
a Test Access Port Controller, an instruction register, a boundary scan
test bypass register, or a test data output multiplexer for multiplexing
between the Bypass, Instruction, and Boundary Scan registers. Moreover,
the LSSD Boundary Scan Latches do not implement the UPDATE signal.
Mixed IEEE 1149.1 Standard and Level Sensitive Scan Design Boundary Testing
Most clearly, Level Sensitive Scan Design differs from IEEE 1149.1 Standard
in the provisions for clocking and scanning, as well as the use of
tristate drivers. There are also other significant architectural and
implementation differences at the chip and I/O level, as noted above.
Notwithstanding these differences, it is frequently necessary to combine
LSSD and IEEE 1149.1 Standard devices on the same printed circuit board or
card. There is, at present, no readily available method of or apparatus
for testing a card or board containing both LSSD and IEEE 1149.1 Standard
devices in a single testing operation.
OBJECTS OF THE INVENTION
It is a primary object of the invention to provide a method of boundary
scan testing a card or board containing both LSSD and IEEE 1149.1 Standard
devices in a single testing operation.
It is a further object of the invention to provide a boundary scan fixture
for testing a card or board containing both LSSD and IEEE 1149.1 Standard
devices in a single testing operation.
SUMMARY OF THE INVENTION
These and other objects are attained by the boundary scan testing method
and apparatus of our invention. According to our invention there is
provided a system, including a fixture and an integrated circuit, that
allows the testing of a circuit network, e.g., a populated printed circuit
card or board, having integrated circuits testable by the IEEE 1149.1
Standard boundary testing, and other integrated circuits, not testable by
IEEE 1149.1 Standard boundary testing, but testable by Level Sensitive
Scan Design (LSSD) testing.
The test system of the invention, including the test fixture and the test
circuitry is useful for boundary scan testing a circuit network
characterized by dissimilar integrated circuits therein. That is, the
circuit under test has at least one first integrated circuit that is
testable by IEEE 1149.1 Standard boundary testing, and at least one second
integrated circuit that is testable by Level Sensitive Scan Design (LSSD)
boundary testing but not by IEEE 1149.1 Standard boundary testing. The
second integrated circuit chip is typically one requiring, among other
things, three clocks for testing.
Panel testing is carried out in a testing fixture. The fixture has an
integrated circuit chip including a Test Access Port interface. The Test
Access Port interface of the fixture's embedded integrated circuit chip
implements the boundary scan testing logic missing in LSSD chips. These
missing items supplied by the fixture include the Test Access Port, with
TCK, TDI, TMS, TDO, and TRST inputs as well as a boundary scan input
register, a boundary scan test output register, a test data output
multiplexer, and a compatible implementation of the UPDATE register. The
test access port interface also includes a Level Sensitive Scan Device
boundary scan register.
The Level Sensitive Scan Device boundary scan register of the system has a
set of control input signals not found in or required by the IEEE 1149.1
Standard. These control signals include the three LSSD clocks: CLK.sub.--
A, CLK.sub.-- B, and CLK.sub.-- C. These signals also include the boundary
scan output, BSCO, and the boundary scan input, BSCI. The controls also
include data inhibit, DI1.
In the test system the BSCO controls boundary scan cells on the Level
Sensitive Scan Device integrated circuit chip associated with drivers, and
the BSCI controls boundary scan cells on the Level Sensitive Scan Device
integrated circuit chip associated with receivers.
The Level Sensitive Scan Device Boundary Scan Register controls the
Boundary Scan Output, BSCO, and the Boundary Scan Input, BSCI, when Test
Access Port control lines Shift Data Register, SHIFTDR, and Boundary Scan
Register Select, BSSEL, are high. The Level Sensitive Scan Device Boundary
Scan Register also controls BSCO and BSCI when Test Access Port control
lines Update Data Register, UPDATDR, and Boundary Scan Register Select,
BSSEL, are high.
The Data Inhibit Signal DI1 is high and data is sent out to the circuit
network from the Level Sensitive Scan Device integrated circuit chip when
the Boundary Scan Select BSSEL and one of Update Data Register, Select
Data Register, or Capture Data Register is high. The Data Inhibit DI1 is
connected to the inhibit pins of the Level Sensitive Scan Device. By this
expedient when DI1 is low no signals are transmitted over the circuit
network from non-selected second integrated circuit chips. When the Data
Inhibit DI1 is high the Level Sensitive Scan Device chip drivers are
enabled and Level Sensitive Scan Device boundary scan cell contents are
transmitted over the circuit network from selected second integrated
circuit chips.
THE FIGURES
The invention may be understood by the reference to the FIGURES appended
hereto.
FIG. 1 shows a schematic overview of an IEEE 1149.1 Standard integrated
circuit chip, with peripheral boundary scan cells, internal system logic,
and the Test Access Port, with its inputs and outputs.
FIG. 2 shows an individual IEEE 1149.1 Standard Boundary Scan Cell.
FIG. 3 shows the IEEE 1149.1 Standard boundary scan architecture and logic
flow.
FIG. 4 shows an IEEE 1149.1 Standard Data Register.
FIG. 5 shows the IEEE 1149.1 Instruction Register outputs.
FIG. 6 shows a schematic overview of a Level Sensitive Scan Device
integrated circuit chip, with peripheral boundary scan cells, and with
test function inputs going directly into the internal system logic, and
test function outputs coming directly out of the internal system logic.
FIG. 7 shows an LSSD boundary scan data input.
FIG. 8 shows an LSSD boundary scan data input.
FIG. 9 shows an LSSD boundary scan data output.
FIG. 10 shows an LSSD boundary scan data output.
FIG. 11 shows a schematic view of a test fixture of the invention with an
IEEE 1149.1 device and an LSSD device in position for testing.
FIG. 12 shows the logic block diagram of the test access port and other
circuitry of the embedded chip.
FIG. 13 shows the state machine schematic diagram of the test access port
of the embedded chip.
FIG. 14 shows the logic diagram for generating clock signals for the LSSD
device from the single clock signal of the TCK input.
FIG. 15, including FIG. 15A and FIG. 15B, is a side by side comparison of
an IEEE 1149.1 Standard Boundary Scan Cell and a Level Sensitive Scan
Device Boundary Scan Cell.
FIG. 15A shows an IEEE 1149.1 Standard Boundary Scan Cell.
FIG. 15B shows a Level Sensitive Scan Device Boundary Scan Cell.
FIG. 16 shows the logic diagram of the Instruction Register.
FIG. 17 shows the logic diagram for the boundary scan control logic.
FIG. 18 shows the logic diagram for the bypass register.
FIG. 19 shows the logic diagram for the instruction decode logic.
FIG. 20 shows the logic diagram for the TDO multiplexer.
FIG. 21 shows the timing diagram for the Test Access Port.
DETAILED DESCRIPTION OF THE INVENTION
According to our invention there is provided a method and a system for
testing integrated circuit chip networks on a printed circuit board or
card. The system, including a fixture and an integrated circuit, allows
the testing of a circuit network. A circuit network is a populated printed
circuit card or board, having integrated circuits testable by the IEEE
1149.1 Standard boundary testing, and other integrated circuits, not
testable by IEEE 1149.1 Standard boundary testing, but testable by Level
Sensitive Scan Design (LSSD) testing.
At the present time software exists to generate infrastructure tests and
interconnect tests between electronic devices, for example, integrated
circuit chips, utilizing the IEEE 1149.1 Standard. Software also exists to
automatically generate tests between devices utilizing other standards,
such as the Level Sensitive Scan Device standard. However, there has
heretofore been no software that will automatically generate interconnect
tests between devices, such as integrated circuit chips, of different and
heretofore incompatible types of boundary scan standards.
Utilizing the method and apparatus described herein, circuit networks, that
is, populated electronic circuit cards, incorporating devices of the IEEE
1149.1 Standard and another standard, as the Level Sensitive Scan Device
standard, can have interconnect tests generated quickly and efficiently
using commercially available boundary scan software.
The fixture of the invention is shown generally in FIG. 11. The fixture
imposes the test access port interface chip of the invention between the
fixture and the LSSD integrated circuit chips under test. The circuit has
a Test Access Port ("TAP"), having the chip logic block diagram shown in
FIG. 12 and the state machine schematic shown in FIG. 13. The TAP
circuitry contains a state machine as well as a pair of registers, the
Instruction Register, and the Bypass Register. This circuit is built
according to the IEEE 1149.1 Standard, as described hereinabove. However,
according to the system and method of our invention this Test Access Port
is not incorporated in the chip or chips under test, but is, instead,
separate from the chips under test, incorporating IEEE 1149.1 Standard
functions not on the LSSD chip, and is free standing, as part of the test
fixture of the invention. However, this separate and distinct circuit is
incorporated within the scan definition of an LSSD module in the card
under test. Incorporation of the scan definition in this way causes the
tester to behave as if the Test Access Port were a part of the Level
Sensitive Scan Device under test. This requires manipulation of the net
data provided by the design tool. Certain nets must be added and other
nets must be deleted so that the tester generates the proper patterns. For
this reason, some nets are defined as linkage pins in the Boundary Scan
Design Language (BSDL) to force the tester to ignore them. To be noted is
that the nets needed to link the clock outputs of the Test Access Port and
the Level Sensitive Scan Device are physically real. However, they must be
ignored for Automatic Test Generation (ATG) purposes but not for test
purposes, since the connections between added circuits and the card must
be tested before the scan test is run.
Test Access is the function of this Test Access Port chip. It is the
interface between the devices that are tested under the IEEE 1149.1
Standard and the devices that are tested under the Level Sensitive Scan
Device standard.
According to one embodiment of the invention the Test Access Port chip is
incorporated in a Field Programmable Gate Array. One suitable Field
Programmable Gate Array is a Xilinix XC4000 Gate Array. The use of a Field
Programmable Gate Array permits the circuit to be adaptable to the special
and unique requirements of the non-IEEE 1149.1 chip, i.e., the Level
Sensitive Scan Device integrated circuit chip. One reason for a special
interface is that while an IEEE 1149.1 Standard chip requires a single
clock signal, a Level Sensitive Scan Device integrated circuit chip
requires two or even three separate clock signals, all of which must be
generated from the single clock signal, TCLK, of the IEEE 1149.1 Standard
interface. This can be accomplished with the simple combinational circuits
shown in FIG. 14. The combinational circuit there shown has a single
input, TCLK. This is the IEEE 1149.1 Standard interface clock. The TCLK
signal is ANDed with a delayed TCLK signal to yield the LSSD A.sub.-- CLK
signal. The TCLK signal is inverted, and the inverted TCLK signal is ANDed
with a delayed inverted TCLK signal to yield the LSSD B.sub.-- CLK signal.
While FIG. 14 illustrates one combinational circuit for use with Level
Sensitive Scan Devices, other scan requirements may include specific scan
and hold requirements which may be custom programmed into the Field
Programmable Gate Array of FIGS. 12 and 13.
The Test Access Port Field Programmable Array can be embedded in the test
fixture as shown in FIG. 11. Utilizing all of the features of the Field
Programmable Gate Array permits the test system to perform a self
diagnosis of the fixture and tester circuit prior to performing actual
tests on actual cards under test. Moreover, the Field Programmable Gate
Array can also have the IEEE 1149.1 Standard embedded therein, so that
fixture tests can be automatically generated by the same software used to
generate the test for the device, i.e., the chip or card, under test. All
that is required is the Netlist describing the circuit under test and the
Boundary Scan Descriptive Language ("BSDL") of the Field Programmable Gate
Array.
Because the Field Programmable Gate Array's pins are connected to a
programmable tester, the Field Programmable Gate Array itself can be
programmed as part of the initialization of the tester. Once the circuit
design of the Field Programmable Gate Array is set, the design software
generates the programming commands that must be applied to the pins of the
Field Programmable Gate Array. These commands are converted to test
vectors by other software routines. The resulting vectors are then placed
in the initialization routine of the tester.
The test system of the invention, including the test fixture and the test
circuitry is useful for boundary testing a circuit network characterized
by dissimilar integrated circuits therein. That is, the circuit under test
has at least one first integrated circuit that is testable by IEEE 1149.1
Standard boundary testing, and at least one second integrated circuit that
is testable by Level Sensitive Scan Design (LSSD) boundary testing but not
by IEEE 1149.1 Standard boundary testing. The second integrated circuit
chip is typically one requiring three clocks for testing.
FIG. 15, including FIG. 15A and FIG. 15B, is a side by side comparison of
an IEEE 1149.1 Standard Boundary Scan Cell and a Level Sensitive Scan
Device Boundary Scan Cell. Both cells have input data from the system
logic and the mode, i.e., test or normal operations. In the IEEE 1149.1
Standard Cell shown in FIG. 15A there is an input from the previous cell,
an input from the system logic and a mode select signal, and an input
ShiftDR. This is outputted to logic clocked by ClockDR, which goes to the
next cell, and to further logic clocked by UpdateDR which goes to the
system logic and also feeds back to the input logic device.
FIG. 15B also shows a Level Sensitive Scan Device Boundary Scan Cell. In
this arrangement, the data from the system logic and mode pass through
logic to a latch with the A.sub.-- CLK, the C.sub.-- CLK, and the data
from the last cell. The resultant of this latch then goes, with the
B.sub.-- CLK to another latch. The resultant is then input to the next
cell and to the first latch of the first cell.
To test circuit networks with these disparate boundary scan logic types a
test fixture as shown in FIG. 11 is utilized. This fixture interfaces
directly with the IEEE 1149.1 Standard device on the card, and through the
Field Programmable Gate Array, including the Test Access Port integrated
circuit chip, to the Level Sensitive Scan Device.
The fixture includes a test access port interface and associated circuitry.
The test access port interface is provided through the separate TAP chip,
having the logic shown in FIG. 12. The TAP interface on the chip includes
a test access port controller with Test Clock, Test Data In, Test Data
Out, Test Mode Select, and Test Reset I/O. The associated circuitry
includes an instruction register, a bypass register, and a clock
generator.
As shown in FIG. 12 the Test Access Port chip has the inputs Test Data
Inhibit (TDI), Test Mode Selector (TMS), Test Reset (TRST), and Test Clock
(TCLK) and the output Test Data Output (TDO). The Test Access Port (TAP)
itself has three outputs to the Test Access Port Controller. These are the
TMS, the TRST, and the TCLK.
The TAP controller is the state machine that interfaces with the test
access port. The TAP controller outputs drive the Instruction Register
(IR) shown in FIG. 16, the Boundary Scan Control Logic shown in FIG. 17,
and the Bypass Register shown in FIG. 18. Test Data Inhibit (TDI) is also
an input to the Boundary Scan Register and the Boundary Scan Control
Logic.
The Instruction Register (IR) drives the Instruction Decode logic, shown in
FIG. 19, which drives the Bypass Register and the Boundary Scan Control
Logic. The Instruction Register, the Bypass Register, and the LSSD
boundary scan outputs are the input to the Test Data Output (TDO)
Multiplexer. The output of the TDO Multiplexer is the Test Data Output,
and it passes through the Test Access Port.
The TAP controller is a four-bit, 16 state machine. It has the states shown
in the table below:
______________________________________
Test Access Port Controller State
DCBA
______________________________________
Exit2-DR 0000
Exit1-DR 0001
Shift-DR 0010
Pause-DR 0011
Select-IR-Scan 0100
Update-DR 0101
Capture-DR 0110
Select-DR-Scan 0111
Exit2-IR 1000
Exit1-IR 1001
Shift-IR 1010
Pause-IR 1011
Run-Test/Idle 1100
Update-IR 1101
Capture-IR 1110
Test-Logic-Reset 1111
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