Method and apparatus for resetting multiple processors using a common ROM

What is claimed is:

1. A method for powering up multiple processors in a computer system that includes a primary processor which commences operation on power-up of said computer system, a secondary processor which enters a hold state on power-up of said computer system, the primary processor and the secondary processor being powered up together, common elements used by both said primary processor and secondary processor, means coupled to said primary processor and said secondary processor for allowing said hold state of said secondary processor to be terminated, means for storing a redirection vector, and means for storing a start-up program which includes as one step determining whether said redirection vector is to be utilized, said start-up program including initialization code used to initialize said secondary processor, the method comprising:

said primary processor commencing said start-up program and not utilizing said stored redirection vector, said start-up program including steps for initializing said primary processor and steps for initializing said common elements of the computer system;

said primary processor completing appropriate initialization of said computer system;

said primary processor placing a redirection vector pointing to said secondary processor initialization code in said redirection vector storing means;

said primary processor activating said secondary processor;

said secondary processor commencing said start-up program and utilizing said stored redirection vector to begin execution of said secondary processor initiation code after said primary processor places said redirection vector, wherein said secondary processor initialization code is only a subset of operations comprised in said start-up program and does not include said steps for initializing said common elements of said computer system; and

said secondary processor executing said secondary processor initialization code.

2. The method of claim 1, wherein said computer system further includes a read only memory coupled to both said primary processor and said secondary processor for storing said start-up program and said initialization code.

3. The method of claim 1, wherein said computer system further includes means for storing information indicating whether said redirection vector should be utilized and wherein said start up program references said storing means to determine redirection vector utilization, the method further comprising:

said primary processor placing information in memory indicating the utilization of said redirection vector before activating said secondary processor.

4. The method of claim 1, wherein said computer system includes only one said primary processor and only one said secondary processor.

5. The method of claim 1, wherein said computer system includes a means for differentiating between said primary processor and said secondary processor and said start up program references said means for differentiating to determine redirection vector utilization.

6. The method of claim 3, wherein said redirection vector utilization information storing means includes CMOS nonvolatile memory.

7. The method of claim 3, wherein said computer system further includes means for storing information indicating that said secondary processor has completed said initialization code, the method further comprising:

said primary processor polling said initialization complete storing means after activating said secondary processor;

said secondary processor placing information in said initialization complete storing means indicating that said initialization code has been executed when said initialization code has been completed; and

said primary processor resuming operation after said secondary processor has placed information in said initialization complete storing means indicating that said initialization code has been completed.

8. The method of claim 3, wherein said computer system further includes means for placing said secondary processor on hold and removing said secondary processor from a hold state, the method further comprising:

said secondary processor placing itself on hold after executing said initialization code.

9. The method of claim 7, wherein said computer system further includes means for temporarily storing the original contents of said redirection vector storing means and said redirection vector utilization information storing means, the method further comprising:

said primary processor placing original contents of said redirection vector storing means into said temporary storing means before placing said redirection vector into said redirection vector storing means;

said primary processor placing original contents of said utilization information storing means into said temporary storing means before placing information into said utilization storing means indicating the utilization of said redirection vector; and

said primary processor restoring said original contents of said redirection vector storing means and said utilization information storing means from said temporary means after said secondary processor places information in said initialization complete storing means indicating that said initialization code has been executed.

10. The method of claim 9, wherein said computer system further includes means for storing information indicating that said secondary processor has completed said initialization code, the method further comprising:

said primary processor halting operation and polling said initialization complete storing means after activating said secondary processor;

said secondary processor placing information in said initialization complete storing means indicating that said initialization code has been executed when said initialization code has been completed; and

said primary processor resuming operation after said secondary processor has placed information in said initialization complete storing means indicating that said initialization code has been completed.

11. The method of claim 9, wherein said computer system includes a means for placing said secondary processor on hold and removing said secondary processor from a hold state, the method further comprising:

said secondary processor placing itself on hold after executing said initialization code.

12. The method of claim 9, where said computer system includes only one said primary processor and only one said secondary processor.

13. A computer system having multiple processors configured in a multiprocessor environment sharing memory and input/output space, said computer system comprising:

a primary processor which commences operation on power-up of said computer system;

a secondary processor which enters a hold state on power-up of said computer system, said secondary processor powering-up at the same time as said primary processor;

means coupled to said primary processor and said secondary processor for allowing said hold state of said secondary processor to be terminated;

means coupled to said primary processor and said secondary processor for storing a start-up program which determines whether a redirection vector is to be utilized, which is begun by both said primary processor and said secondary processor upon activation of operation, said start-up program including steps for initializing said primary processor and steps for initializing common hardware elements usable by both said primary processor and secondary processor, said start-up program further including initialization code for said secondary processor, said secondary processor initialization code being comprised of a subset of operations comprising said start-up program and not including said steps for initializing said common hardware elements;

means for storing a redirection vector pointing to said secondary processor initialization code; and

means for directing said secondary processor to utilize said redirection vector to execute said secondary processor initialization code.

14. The computer system of claim 13, wherein said start up program storing means includes a read only memory.

15. The computer system of claim 13, further including means coupled to said primary processor and said secondary processor for allowing communication between said primary processor and said secondary processor.

16. The computer system of claim 13, incorporating only one said primary and only one said secondary processor.

17. The computer system of claim 13, wherein said means for directing said secondary processor to utilize said redirection vector storing means includes a CMOS memory.

18. The computer system of claim 13, wherein said means for directing said secondary processor to utilize said redirection vector storing means includes a means for differentiating between said primary processor and said secondary processor.

19. The computer system of claim 13, further comprising means for storing information indicating that said secondary processor has completed said initialization code, said storing means being polled by said primary processor while said secondary processor is executing said initialization code.

20. The computer system of claim 13, further comprising means for temporarily storing original contents of said redirection vector storing means and said redirection vector utilization information storing means.

21. The computer system of claim 13, further comprising means for placing said secondary processor on hold and removing said secondary processor from a hold state.

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to multiple processors in computer systems and more particularly to multiple processors having a common reset using a single ROM.

2. Description of the Prior Art

The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful personal computers. New and increasingly more complex applications for personal computers are continually being developed, and the computer programs required to implement these new applications have experienced a corresponding increase in size and complexity, requiring greater amounts of time for the computer to be able to run them properly. As a result, personal computers have been burdened with lengthier amounts of software instructions that take increasing amounts of time for them to execute.

To meet the challenge of these new software applications, computer designers have used various methods to increase the speed with which personal computers can process instructions. Historically, the personal computer has developed as a system utilizing a single microprocessor to handle all instruction execution. The microprocessor is the key working unit or "brains" of the personal computer, and its task is to handle all of the instructions that programs give it in the form of computer software. The methods that have been used to increase speed in the personal computer have generally centered around maximizing the efficiency with which this single microprocessor can handle instructions.

Limits are being reached, however, on the amount of speed that can be obtained from a system based on a single microprocessor. The obvious choice to remove this constraint has been the incorporation of multiple microprocessors operating in parallel into a computer system. With the use of multiple processors, or multiprocessing, each microprocessor can be working on a different task at the same time. The use of multiprocessing has generally increased computer performance, but it has also resulted in numerous difficulties that were not found in a single processor environment.

A problem that has arisen in multiprocessing has been how to start up or initialize each of the processors without them interfering with each other. In a single processor personal computer environment, the microprocessor generally initializes itself by performing a POST (power on self test). The POST program is located in the computer's ROM, which is a special type of memory that is permanently recorded into the computer. This special memory cannot be written to or changed by software and is nonvolatile, meaning that turning off the computer will not disturb it. The ROM holds a key set of programs that provide essential support for the operation of the computer, among these the test and initialization programs known as the POST, which make sure that the computer is in good working order at power on. The POST program usually includes the microprocessor placing the memory in a known state, testing any memory, placing peripherals in a tested, reset and ready condition and loading or booting up the operating system, among other things.

The problem that arises in multiprocessing is that, in a system where multiple processors coexist sharing a common bus and a common memory, it would be catastrophic for more than one processor to perform a complete POST. For example, if one processor had completed a POST and was up and running, a subsequent processor attempting to perform a POST would re-initialize the peripherals and memory that the previous processor was now using to run its code, resulting in a potential error for the first processor.

For this reason it would seem necessary in a multiprocessing environment for each processor to have its own ROM with which to bring itself to a working state so that one processor's initialization would not interfere with another processor that may already be up and running. However, this scheme would require that numerous ROM's be present in the computer, one associated with each processor, resulting in an unnecessarily large amount of nonvolatile memory being used for this purpose. A further problem that would be associated with the use of multiple ROM's would be the resultant complexity and loading effects on the bus that these ROM's share with the processor. Therefore, it would be highly desirable for these multiple processors to be able to start or "boot" up using a single, common ROM as opposed to each processor containing a different ROM in memory.

For further background on the present invention, it is necessary to examine some of the special features and considerations involving the Intel Corporation (Intel) family of microprocessors, which are used in personal computers compatible with those manufactured and sold by International Business Machines Corp. (IBM). The Intel 80286 microprocessor introduced a new feature that allowed it to operate in two different modes: real mode and protected mode. In real mode, the 80286 behaves very much like the 8088 microprocessor that was in the original IBM PC, thus allowing for full compatibility with these older systems. In protected mode, there are no compatibility considerations, and the 80286 is allowed to utilize all of its special features for maximum capability.

A problem soon became apparent, however, in that, while provisions were made for the 80286 microprocessor to switch from real to protected mode, no provisions were made for the 80286 to return from protected to real mode. This problem was corrected in the Intel 80386 microprocessor, but could only be remedied in the 80286 through the use of the reset operation to return the processor to real mode. The reset operation, however, generally required the computer to perform a complete reset and reboot, and this was found to be unnecessary for the purpose of simply returning the computer from protected to real mode. Therefore, it was determined that some method was needed to indicate whether each reset operation was simply a software reset used for protected to real mode switching or a true system reset, and, as a result, a byte was provided in the CMOS nonvolatile memory available in the computer system to reflect whether or not a full reboot of the system was necessary. At power on, this byte reflects a "normal POST" status, informing the processor that a protected mode reset is not occurring and that a full boot is necessary to begin operation. When the processor is up and running, the status of this byte is changed to reflect a "vector on reset" status when a protected to real mode change is desired, thus informing the processor that a complete reboot is unnecessary.

The processor generally polls the status of this reset byte during its POST program so that the protected to real mode switch can be made with a minimum of lost time. At power on, the normal POST boot status of the reset byte directs the microprocessor to perform a complete POST, whereas, when the processor has been up and running and has its RESET pin toggled, the vector on reset status of the reset byte directs the processor away from the remainder of the POST program to an alternate memory location which is contained in a reset vector location. This memory location is the location desired upon entry into real mode to continue operation of the computer.

SUMMARY OF THE INVENTION

The present invention includes two design variations which allow multiple processors to start up using a single, common ROM. These designs, or techniques, are intended for use in a multiprocessing environment and utilize a system whereby each processor is directed to begin a normal POST, but only a single processor is allowed to perform a complete POST, whereas the remaining processors are directed very early in their POST procedure to perform a limited initialization sequence. The first design is intended for more general applications and is adaptable to any system incorporating multiple processors. This design can be implemented either by the operating system of the particular machine, or by software specifically written for this purpose, with minimal hardware requirements. The second technique is intended to be more particularly adapted to a specific computer and is executed from the POST procedure that is stored in the computer's ROM. This design has a hardware requirement in that an identity register is used to differentiate between the microprocessor performing the complete POST and the remaining microprocessors. This second design also includes a method for allocating tasks to the secondary processors once they are running.

In each of these designs, at power on the processor which performs the complete POST, referred to as the primary processor or processor P.sub.1, begins a POST while the remaining processors which perform alternate initialization sequences, referred to as secondary processors or in the singular as Processor P.sub.Z, are held in an inactive state. In the first design, an initialization procedure for each processor P.sub.Z commences when the processor P.sub.1 has completed its POST program. This initialization procedure includes the processor P.sub.1 placing a vector in the reset vector memory location pointing to initialization code that processor P.sub.Z will execute, changing the reset byte in the CMOS non-volatile memory to reflect a vector on reset status, and enabling address line A20. When the processor P.sub.Z is activated, it begins a POST as the processor P.sub.1 did, but the vector on reset status in the CMOS reset byte directs the processor P.sub.Z to vector off to a different location in ROM containing its initialization code, which it executes. When the processor P.sub.Z has been successfully dispatched, it notifies the processor P.sub.1, which then restores the CMOS reset byte and the vector at the reset vector memory location to their original values as well as the original state of A20. This technique is repeated until all the processors have been initialized.

In the second design the initialization process of each processor P.sub.Z occurs during the POST program being executed by the processor P.sub.1. A register in the computer's hardware is used to differentiate between the processor that performs the complete POST, the processor P.sub.1, and the remaining processors, represented by the processor P.sub.Z, which utilize a more limited initialization scheme. Early in the course of the POST sequence, each processor is directed to the identity register, which informs it as to whether it is a primary or secondary processor. If the processor is determined to be the processor P.sub.1, it is allowed to continue with its POST. If the processor is determined to be the processor P.sub.Z, it is instructed by the POST program to use a vector placed in the reset vector memory location by the processor P.sub.1 to transfer operation to a different location in the ROM containing the more limited initialization code.

Generally, at power on the processor P.sub.1 is activated to begin a POST while the processor P.sub.Z remains in a held state. The activation and initialization of the processor P.sub.Z is directed from the latter part of the POST procedure that is executed by the processor P.sub.1. The processor P.sub.1 releases the processor P.sub.Z and then polls a semaphore location to determine if the processor P.sub.Z has completed its initialization. When the processor P.sub.Z has completed its initialization, it notifies the processor P.sub.1 and places itself on hold, at which time the processor P.sub.1 completes the initialization of any other processors P.sub.Z and then completes the POST.

Upon completion of the POST, the processor P.sub.1 is running, and subsequently the operating system begins allocating various tasks to the processor P.sub.Z. When the operating system decides to give the processor P.sub.Z a task, the processor P.sub.1 takes the processor P.sub.Z out of hold and provides it with a vector pointing to the code that the processor P.sub.Z is to execute. The processor P.sub.1 and the processor P.sub.Z communicate back and forth through a semaphore in memory as to when the processor P.sub.Z has begun execution of its task and when it has completed it. When the processor P.sub.Z has finished its task, it generally places itself in a held state to make it ready to receive other tasks from the operating system. This cycle of task allocation then repeats itself. The processor P.sub.1 may optionally direct the processor P.sub.Z to execute a reset code at any time, this having the utility of resetting the processor P.sub.Z to a known state prior to starting an operation.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:

FIG. 1 is a schematic block diagram of a computer system incorporating the present invention;

FIG. 2 is a flow chart diagram of a first design for initializing the multiple processors using a single ROM according to the present invention;

FIG. 3 is a circuit diagram of an identity register called the Who-Am-I port according to the present invention;

FIG. 4 is a flow chart diagram of a second design for initializing the multiple processors using a single ROM according to the present invention;

FIG. 5 is a flow chart diagram of a design for dispatching tasks to secondary processors according to the present invention; and

FIG. 6 is a flow chart diagram of a design for resetting secondary processors after dispatching according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A computer system incorporating the present invention can utilize one of several design variations that allow multiple processors to start up using a single, common ROM with minimal changes to the ROM from single processor ROM's. The following designs will be discussed with specific reference to Intel 80386 or 80486 microprocessors being the microprocessors utilized in the multiprocessor system, but the use of other processors is also contemplated. Throughout the course of this description, the secondary processors will be referred to in the singular as the processor P.sub.Z, but it is understood that multiple secondary processors may coexist in this environment.

Referring now to FIG. 1, the letter C designates generally a computer system incorporating either of the two designs according to the present invention. Many of the details of a typical computer that are not relevant to the present invention have been omitted for the purpose of clarity. The system C generally includes a primary processor P.sub.1, a secondary processor P.sub.Z, and various interprocessor logic circuitry 30 that is connected between the primary processor P.sub.1 and the secondary processor P.sub.Z. Both the primary processor P.sub.1 and the secondary processor P.sub.Z each generally include a cache subsystem (not shown). The interprocessor logic 30 generally includes various option and status registers and circuitry relating to the operation of the processors. The primary processor P.sub.1, the secondary processor P.sub.Z, and the interprocessor logic circuitry 30 are each connected to a system bus 40 which generally includes an address bus and a data bus as well as various control and status lines that allow for the proper functioning of the computer C. Also attached to the system bus is read only memory (ROM) 50, which includes the start-up program that initializes the multiple processors according to the present invention called the power on self test (POST); random access memory (RAM) 52 which forms the main memory of the system C; and CMOS memory 54 which is used to provide nonvolatile, random access memory for use by the system C.

In each of the designs according to the present invention, at power on the primary processor, processor P.sub.1, is activated and begins a POST (power on self test) which is located in the ROM 50 of the computer system, while the secondary processor P.sub.Z, is kept in a held state. This activation of the processor P.sub.1 and holding of the processor P.sub.Z is accomplished in slightly different manners in the two designs. In the first design a reset bit, which is located preferably in a register in the interprocessor logic circuitry 30 referred to as the Processor Option Register is used. The reset bit generally operates similarly for all processors such that a setting of the reset bit, which occurs at power up by hardware control, results in the RESET input of the respective processor being pulsed and causes the respective processor to be placed in a held state. A subsequent clearing of the reset bit releases the respective processor from its held state and allows the respective processor to begin the POST. Therefore, at power on the reset bit of the processor P.sub.1 is toggled, allowing the processor P.sub.1 to begin the POST, while the reset bit of the processor P.sub.Z is set but not cleared, thereby keeping it in a deactivated or held state.

The second design utilizes a sleep bit located in the Processor Option Register in the interprocessor logic 30 associated with each processor P.sub.Z. The sleep bit operates such that, when it is set for a respective processor, requests for the bus 40 by the respective processor are blocked. Therefore, in the second design, the processors P.sub.1 and P.sub.Z each have their reset bit toggled and a sleep bit is set on the processor P.sub.Z. The toggling of the reset bit of the processor P.sub.1 allows it to begin the POST, while the setting of the sleep bit on the processor P.sub.Z, which occurs at power up by hardware control, causes any requests for the bus by the processor P.sub.Z to be blocked, thus effectively placing the processor P.sub.Z in a held state. A subsequent clearing of the sleep bit of the processor P.sub.Z by the processor P.sub.1 allows bus requests by the processor P.sub.Z to be passed, thereby allowing the processor P.sub.Z to begin the POST. Therefore, in each of these designs, at power on the reset bit of the processor P.sub.1 is generally toggled by the power on circuitry (not shown) of the computer system C, allowing it to begin a POST, while the processor P.sub.Z is kept in a deactivated or held state.

In the first design according to the present invention, as shown in FIG. 2, when the processor P.sub.1 (FIG. 1) has finished a sufficient portion of its POST routine in step 212 to allow start up of the processor P.sub.Z (FIG. 1), the software implementing this design performs an initialization procedure I.sub.1 to bring the processor P.sub.Z into an active state. First, in step 216, the vector at memory location 40:67 in the ROM 50 (FIG. 1), which is the reset vector memory location, is replaced with a new vector pointing to initialization code located in the ROM 50 that will be executed by the processor P.sub.Z when it is enabled. The vector that was previously stored in this location is saved for later restoration.

In step 218, the processor P.sub.1 performs a similar replacement procedure with the CMOS non-volatile memory reset byte, which is preferably located in the CMOS 54. The CMOS reset byte is located at address location OFh in the CMOS memory 54 and is accessed through ports 070h and 071h, as is standard for addressing the CMOS memory in the IBM PC compatible computers. The status of this byte reflects whether a normal boot or vector on reset is necessary when the processor P.sub.Z reads this value in the POST sequence. The processor P.sub.1 will have previously interrogated this location and have found the normal boot value present, enabling it to begin a normal POST. The current value of the CMOS reset byte is saved in step 218 to a temporary location, preferably to a register in the processor P.sub.1. The CMOS reset byte is then changed to value 0Ah, this value signifying that the computer system C is or has been running and that only a vector on reset is necessary instead of the normal POST routine that a processor would normally follow at power on. This change, in effect, fools the processor P.sub.Z into thinking that it has already performed the POST operations. The 0Ah value written to the CMOS reset byte is the reset without EOI value and is utilized to prevent the Processor P.sub.Z from clearing the interrupt controller, as this is unnecessary and might inadvertently cause an error.

Address line A20 of the system address bus 40 (FIG. 1) is enabled in step 220 to allow the processor P.sub.Z to properly access high memory in the ROM 50 where the POST program is located. Address line A20 had previously been disabled in the POST routine of the processor P.sub.1 (step 212) for software compatibility reasons, these stemming from the use by previous programmers of a feature of the 8086 microprocessor whereby the program counter rolled over to 0000h after FFFFFh due to the maximum of twenty address lines available in that microprocessor. This roll over was incorporated into software written for these older 8086 microprocessor-based systems for various purposes, the end result for current purposes being that, in order to maintain compatibility with this older software, address line A20 was disabled during the POST of the processor P.sub.1 (step 212). Consequently, address line A20 must be re-enabled in step 220 to allow the processor P.sub.Z to address the bootstrap program which is preferably located in high memory in the ROM 50.

In step 222, the processor P.sub.1 clears the reset bit in the Processor Option Register of the Processor P.sub.Z, thereby activating the processor P.sub.Z to begin the POST routine in step 226. The processor P.sub.Z comes out of reset and vectors to the reset location in the ROM 50 where the POST program is located. This is the same location where processor P.sub.1 vectored to after reset, this being a general function of the microprocessors used in the present invention. Thus, both the processors P.sub.1 and P.sub.Z operate from the same ROM 50 immediately after reset execution. Very early in the execution of the POST routine, the processor P.sub.Z polls the CMOS reset byte to determine its status. As the CMOS reset byte was previously changed by the processor P.sub.1 in step 218 to value 0Ah, reflecting a vector on reset status, the processor P.sub.Z in step 228 is directed to the reset vector memory location 40:67. This location contains the vector which was placed there earlier by the processor P.sub.1 in step 216, and this vector is used in step 230 to direct the processor P.sub.Z to its alternate initialization code, preferably located in the ROM 50 but alternatively located in RAM 52 after being loaded by the processor P.sub.1. This initialization code generally includes the processor P.sub.Z executing any specific reset code, testing its cache memory and performing other processor P.sub.Z dependent features.

After activating the processor P.sub.Z in step 222, the processor P.sub.1 awaits the successful dispatch of the processor P.sub.Z in step 224 by polling a semaphore bit which is preferably located in the RAM 52. A final step 232 in the initialization sequence performed by the processor P.sub.Z involves the processor P.sub.Z altering the semaphore bit to signal to the processor P.sub.1 that the initialization sequence has been successfully completed. When step 232 is completed, the processor P.sub.Z begins performing a software loop in step 234, waiting until it is directed by the operating system to perform a task.

When the processor P.sub.1 receives notification by way of the changed semaphore bit that the processor P.sub.Z has completed its initialization, the processor P.sub.1 proceeds to step 236 where it restores the original value of the CMOS reset byte from its temporary location. The processor P.sub.1 then proceeds to step 238 where the original vector is returned to the reset vector memory location 40:67 and the initial state of address line A20 is restored. The processor P.sub.1 then continues with its operation.

Referring again to FIG. 1, the second design according to the present invention is similar in many respects to the first, but is tailored for a two processor system C (FIG. 1) incorporating one primary processor, referred to as the processor P.sub.1, and one secondary processor, referred to as the processor P.sub.2. The expansion of this design to incorporate multiple secondary processors, however, is also contemplated.

This second design is also