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Claims  |
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We claim:
1. A process for forming a multilayer wiring in a fabricated wafer, said
multilayer wiring comprising a plurality of wirings stacked via silicon
and oxygen-containing insulating layers each provided between one and
another of said wirings, one of said wirings being electrically connected
to another wiring through via-holes, which comprises the steps of:
(a) introducing into a pretreatment chamber said fabricated wafer having
the wirings, one of which is covered thereon by the insulating layers
except said via-holes, the surfaces of the wiring exposed at the via-holes
being covered by a native oxide of the wiring;
(b) introducing a rare gas into said pretreatment chamber and then forming
a plasma in said chamber by electric discharge to physically remove an
amount of said oxide from the exposed surfaces due to the collision of
plasma particles against the surfaces;
(c) introducing an etching gas into said chamber, then forming a plasma in
said pretreatment chamber by electric discharge and introducing said
fabricated wafer from step (b) into said plasma, thereby increasing the
oxygen content of the surface of said insulating layers as reduced during
the physical removal of the oxide in step (b) to restore the reduced
oxygen/silicon ratio of the surface of the insulating layers, to that
before the pretreatment of step (b);
(d) ceasing the introduction of both the rare gas and etching gas in said
pretreatment chamber and then evacuating said pretreatment chamber;
(e) subjecting the exposed surfaces of the wiring to a treatment for
corrosion prevention and transferring said fabricated wafer to an
evacuated deposition chamber; and,
(f) introducing a deposition material gas into said deposition chamber
containing the corrosion-prevention treated wafer placed therein, and
selectively depositing said material only on said exposed surfaces of the
wiring in said via-holes to fill said via-holes with the deposited
material; and,
(g) preparing another wiring on said insulating layers.
2. The process according to claim 1, wherein said etching gas is a gas at
least containing chlorine or a chlorine compound.
3. The process according to claim 1, wherein said treatment for corrosion
prevention is carried out in said pretreatment chamber.
4. The process according to claim 1, wherein said treatment for corrosion
prevention is carried out in a chamber separately provided, containing
said fabricated wafer transferred thereto from said pretreatment chamber.
5. The process according to claim 1, wherein said treatment for corrosion
prevention is carried out in said deposition chamber.
6. The process according to claim 1, wherein said treatment for corrosion
prevention is carried out by heating said fabricated wafer under vacuum or
in an atmosphere of one or more of nitrogen gas, hydrogen gas, and a rare
gas at a higher wafer temperature than that used in the subsequent
depositing step (f).
7. A process for forming a multilayer wiring in a fabricated wafer, said
multilayer wiring comprising a plurality of wirings stacked via silicon
and oxygen-containing insulating layers each provided between one and
another of said wirings, one of said wirings being electrically connected
to another wiring through via-holes, which comprises the steps of:
(a) introducing into a pretreatment chamber said fabricated wafer having
the wirings, one of which is covered thereon by the insulating layers
except said via-holes, the surfaces of the wiring exposed at the via-holes
being covered by a native oxide of the wiring;
(b) introducing a rare gas into said pretreatment chamber, then forming a
plasma in said chamber by electric discharge to physically remove an
amount of said oxide from the exposed surfaces due to the collision of
plasma particles against the surfaces, and ceasing the introduction of the
rare gas in the pretreatment chamber;
(c) introducing an etching gas into said chamber, then forming a plasma in
said pretreatment chamber by electric discharge and introducing said
fabricated wafer from step (b) into said plasma, thereby increasing the
oxygen content of the surface of said insulating layers as reduced during
the physical removal of the oxide in step (b) to restore the reduced
oxygen/silicon ratio of the surface of the insulating layers, to that
before the pretreatment of step (b);
(d) ceasing the introduction of the etching gas in said pretreatment
chamber and then evacuating said pretreatment chamber;
(e) subjecting the exposed surfaces of the wiring to a treatment for
corrosion prevention and transferring said fabricated wafer to an
evacuated deposition chamber; and,
(f) introducing a deposition material gas into said deposition chamber
containing the corrosion-prevention treated wafer placed therein, and
selectively depositing said material only on said exposed surfaces of the
wiring in said via-holes to fill said via-holes with the deposited
material; and,
(g) preparing another wiring on said insulating layers.
8. The process according to claim 7, wherein said etching gas is a gas at
least containing chlorine or a chlorine compound.
9. The process according to claim 7, wherein said treatment for corrosion
prevention is carried out in said pretreatment chamber.
10. The process according to claim 7, wherein said treatment for corrosion
prevention is carried out in a chamber separately provided, containing
said fabricated wafer transferred thereto from said pretreatment chamber.
11. The process according to claim 7, wherein said treatment for corrosion
prevention is carried out in said deposition chamber.
12. The process according to claim 7, wherein said treatment for corrosion
prevention is carried out by heating said fabricated wafer under vacuum or
in an atmosphere of one or more of nitrogen gas, hydrogen gas, and a rare
gas at a higher wafer temperature than that used in the subsequent
depositing step (f).
13. A process for forming a multilayer wiring in a fabricated wafer, said
multilayer wiring comprising a plurality of wirings stacked via silicon
and oxygen-containing insulating layers each provided between one and
another of said wirings, one of said wirings being electrically connected
to another wiring through via-holes, which comprises the steps of:
(a) introducing into a pretreatment chamber said fabricated wafer having
the wirings, one of which is covered thereon by the insulating layers
except said via-holes, the surfaces of the wiring exposed at the via-holes
being covered by a native oxide of the wiring;
(b) introducing a rare gas and an etching gas or an etching gas alone,
forming a plasma of said gases or gas by electric discharge, and exposing
said fabricated wafer to the plasma, to physically remove an amount of
said oxide from the exposed surfaces due to the collision of plasma
particles against the surfaces and chemically removing an amount of said
oxide with radicals in said plasma, while simultaneously increasing the
oxygen content of the surface of said insulating layer to restore the
oxygen/silicon ratio of the surface of the insulating layer, which was
reduced during the removal of the oxide film, to that before the
pretreatment of step (a);
(c) ceasing the introduction of the rare gas and the etching gas or the
etching gas alone in said pretreatment chamber and then evacuating said
pretreatment chamber;
(d) subjecting the exposed surfaces of the wiring to a treatment for
corrosion prevention and transferring said fabricated wafer to an
evacuated deposition chamber; and,
(e) introducing a deposition material gas into said deposition chamber
containing the corrosion-prevention treated wafer placed therein, and
selectively depositing said material only on said exposed surfaces of the
wiring in said via-holes to fill said via-holes with the deposited
material; and,
(f) preparing another wiring on said insulating layers.
14. The process according to claim 13, wherein said etching gas is a gas at
least containing chlorine or a chlorine compound.
15. The process according to claim 13, wherein said treatment for corrosion
prevention is carried out in said pretreatment chamber.
16. The process according to claim 13, wherein said treatment for corrosion
prevention is carried out in a chamber separately provided, containing
said fabricated wafer transferred thereto from said pretreatment chamber.
17. The process according to claim 13, wherein said treatment for corrosion
prevention is carried out in said deposition chamber.
18. The process according to claim 13, wherein said treatment for corrosion
prevention is carried out by heating said fabricated wafer under vacuum or
in an atmosphere of one or more of nitrogen gas, hydrogen gas, and a rare
gas at a higher wafer temperature than that used in the subsequent
depositing step (f). |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
The present invention relates to a method for filling small via holes
provided to insulating film to expose parts of the underlayer on a wafer
by metal by means of selective CVD (chemical vapor deposition) and an
apparatus therefor. In particular, it relates to a method for via filling
by metal suitable for filling small via holes by metal which is capable of
both securing a satisfactory selectivity and providing a good low contact
resistance, and to an apparatus therefor.
With the recent trend toward more highly integrated LSIs, difficulties in
wiring design for connection between elements and wiring or between
respective wirings are becoming more serious, and multilayer wiring, so
called multilevel metallization, has become an indispensable technique for
overcoming the difficulties. In order to connect a lower layer wiring and
an upper layer wiring provided thereon with an insulating film provided
therebetween, there is used a method which comprises providing minute via
holes to the insulating film and filling the via holes by a metal. Several
methods are known for filling via holes. Among them, one of the most
promising methods for use in practice is selective CVD of a metal
(particularly tungsten) because it shows a good via filling ability even
when the diameter of via hole is very small.
The method of selective CVD of tungsten comprises introducing a mixture of
tungsten fluoride (WF.sub.6) gas and hydrogen (H.sub.2) gas over a sample
heated to above 250.degree. C. and making them contact with each other,
and thereby making a tungsten (W) film grow on the underlayer metal
(exemplified herein by aluminum) based on either of the following
reactions.
WF.sub.6 +2Al.fwdarw.W+2AlF.sub.3 ( 1)
WF.sub.6 +3H.sub.2 .fwdarw.W+6HF (2)
On an insulating film such as SiO.sub.2 film, the reaction (1) does not
take place and also the reaction (2) does not proceed at a temperature not
higher than 700.degree. C., so that tungsten grows selectively on
aluminum, whereby via filling can be achieved.
References which give description of selective CVD of tungsten include J.
Electrochem. Soc. 131, 1427-1433 (1984) and Proc. of VLSI Multilevel
Interconnection Conference (Jun. 15-16, 1987) p 132-137. However, even
when the methods described in above references are used, such insulating
substances as oxide film present on Al underlayer and AlF.sub.3 formed by
the reaction (1) remain at the interface between tungsten and aluminum in
the via hole, making it difficult to obtain a sufficiently low contact
resistance at the via hole part. Methods which have been proposed to solve
the above problem include one comprising forming the tungsten film while
heating the wafer above 380.degree. C. as disclosed in Proc. of VLSI
Multilevel Interconnection Conference (Jun. 15-16, 1987) p. 208-215, and a
method comprising attaching a thin (about 500 .ANG. thick) MoSi.sub.2 film
onto aluminum and thereby inserting MoSi.sub.2 between aluminum and
tungsten, whereby the tungsten film can be formed without leaving aluminum
surface oxide film and AlF.sub.3 behind at the interface, as disclosed in
Toshiba Review, Vol. 41, No. 12, p. 988-991.
Recently, a method has been reported in which SiH.sub.4 or a similar gas is
used in place of H.sub.2 as a reducing gas, as described, for example, in
Technical Digest IEDM (1987), P213-P219. The use of this method enables a
high rate film growth at a wafer heating temperature as low as
250.degree.-320.degree. C. In this method, at a temperature not below
340.degree. C., the selectivity is lost and selective via filling cannot
be achieved.
In the prior techniques mentioned above, however, no sufficient
consideration is given regarding the treatment of underlayer metal surface
on which tungsten is to be grown by selective CVD, resulting in the
following problems. That is, the contact resistance at the via hole is
not-sufficiently low or, even when the contact resistance at the via hole
is low, the resistance of wiring itself increases; or tungsten grows also
on the insulating film as the result of surface cleaning treatment of via
hole underlayers, leading to occurrence of short circuit between adjacent
through holes.
The surface of underlayer metal after formation of small via holes is
contaminated by fouling originated from a photoetching process applied for
providing the small via holes, or the metal surface is formed of a oxide
film (Al.sub.2 O.sub.3 etc. when the underlayer metal is aluminum, for
example) purposely provided as an anti-corrosive treatment against a
halogen-containing gas used as an etching gas. Therefore, the underlayer
has no clean metal surface exposed, and impurities which increase contact
resistance remain at the interface between underlayer metal and tungsten
even after tungsten film has been grown. The oxides etc. which remain at
the interface are, when a wafer temperature of 380.degree. C. or more is
used in growth of tungsten, sometimes decreased in amount through the
etching reaction of WF.sub.6 and diffusion within film during heating,
resulting in a sufficiently low contact resistance. However, when the
underlayer surface conditions of small via holes differ from wafer to
wafer, a sufficiently low contact resistance cannot always be obtained
with good reproducibility. To solve the above problems, namely poor
reproducibility of low contact resistance and increased contact resistance
of the tungsten/aluminum interface formed by the selective CVD of tungsten
mentioned above, there has been proposed a method which uses as an
underlayer an aluminum of a laminate film formed by attaching a MoSi.sub.2
film (about 500 .ANG. thick) onto aluminum. In this method, since the
remaining oxygen at the interface is decreased by making the exposed part
of the small via hole constituted of MoSi.sub.2 more difficultly
oxidizable than aluminum and further since the formation of insulative
AlF.sub.3 with a low vapor pressure according to the above-mentioned
equation (1) does not take place at the interface, the contact resistance
of the W/MoSi.sub.2 /Al is lower than that of the W/Al interface. However,
this method is accompanied by a problem of requiring etching for forming a
wiring of laminated film of MoSi.sub.2 and Al and of increasing wiring
resistance due to the use of MoSi.sub.2 having a high resistivity. The
above-mentioned increase in resistance poses no problem in the case of
MOSLSI such as DRAM and SRAM because the film thickness of MoSi.sub.2 is
very thin as compared with that of aluminum. In the case of such LSIs as
bipolar and biCMOS which capitalize on their high speed, however, even a
slight increase in resistance raises a serious problem.
On the other hand, several methods have been tried in which aluminum is
used as the underlayer and the via hole is filled by tungsten after
cleaning the surface of the underlayer (including removal of Al.sub.2
O.sub.3 on the aluminum surface). Methods used for cleaning the underlayer
surface include a wet etching which uses a solution containing hydrogen
fluoride (HF) or a compound thereof such as ammonium fluoride (NH.sub.4 F)
and a sputter-etching which uses Ar ions. In the former treatment,
however, a slight amount of fluorine remains even after washing and drying
steps and causes the corrosion of aluminum underlayer. The latter
sputter-etching treatment enables exposure of a clean underlayer surface
since it physically removes the outer surface of the underlayer, and is
hence in use as the method of pretreatment of underlayers in multilevel
interconnection of sputtered aluminum. In this method, however, it has
been revealed as described below that selectivity is lowered in the
selective CVD, caused by the fact that the insulating film is
sputter-etched simultaneously. When an insulating film is sputter-etched,
the composition of the surface layer of insulator changes owing to the
difference in sputtering yield between elements. In a SiO.sub.2 film, for
example, since O atom is more susceptible to sputtering than Si atom, the
surface layer comes to have a composition rich in Si. In other words,
active si atoms come to exist at the insulating film surface. This
phenomenon has been studied by means of X-ray photoelectron spectroscopy
(XPS or ESCA) and discussed, for example, in J. Vac. Sci. Technol., A 3(5)
(1985), pp 1921-1928 and J. Phys. D: Applied Phys., 20 (1987), pp
1091-1094.
When the selective CVD of tungsten is carried out under such conditions,
the growth of tungsten proceeds presumably as the result of the following
reaction:
WF.sub.6 3/2Si.fwdarw.W+3/2SiF.sub.4 ( 3)
Accordingly, tungsten grows also on SiO.sub.2, resulting in lowering of
selectivity. This applies also to the selective CVD of other metals than
tungsten. Thus, since selective CVD is based on the difference in chemical
activity between respective surface parts, when a part at which no growth
is desired, namely the surface of insulating film, is sputtered and
activated, selectively is lowered resultantly. When a metal grows on
insulating film, it gives rise to a possibility of short circuit with
adjacent through holes and, further, since the metal film formed on the
insulating film is apt to peel off, it remains as dirt on the wafer and
causes the lowering of yield.
In the foregoing, description was made with reference to a via hole using
an aluminum wiring as an underlayer because the surface oxide film on
aluminum are generally known as the representative of the most difficultly
removable materials. However, in case of via filling of a via hole with Si
contact, which is called a contact hole occasionally, where doped Si,
various barrier metals (e.g., WSi.sub.2, MoSi.sub.2, TiSi.sub.2, PtSi, and
TiW) are used as underlayer, there arise problems different from those in
via holes using an aluminum wiring as an underlayer mentioned above.
Tungsten film is formed relatively easily on the surface of the
above-mentioned materials which may possibly constitute the underlayer of
contact holes, because they do not form an oxide film so strongly as the
aluminum does. However, in case that a number of different materials come
to exist as the underlayer of the bottom part of holes, the growth rate of
tungsten varies depending on the difference of materials of underlayer,
leading to a situation wherein while via filling by tungsten has been
completed in holes of a certain underlayer, the growth of tungsten has
just begun at other holes. This is attributable to the differences in
thickness, and/or quality of the oxide film present on the surface of
underlayers caused by the difference in material of underlayers. It is
generally considered that in W-CVD (tungsten chemical vapor deposition)
the growth of tungsten does not begin simultaneously with the introduction
of raw material gas, but an induction time is present after the
introduction of gas till the substantial initiation of growth of tungsten,
because the surface oxide film of the underlayer delays the initiation of
tungsten film growth. Therefore, the presence of contact holes different
in thickness and quality of the surface oxide film of underlayers on the
same wafer leads to difficulty in obtaining uniform film thickness in via
filling by tungsten. Thus, it is necessary to remove these surface oxide
films of underlayer in order to obtain a uniform film thickness of via
filling by tungsten in contact holes. In doped Si and various silicides
used as the underlayer material of contact holes, wet etching treatment
with a solution containing hydrogen fluoride or a compound thereof such as
ammonium fluoride is carried out as a means for cleaning the underlayer
surface and the surface oxide film is removed thereby because no problem
of corrosion arises unlike in aluminum. However, even in a wafer subjected
to such wet etching treatment, there remains a problem unsolved in that a
surface oxide film is formed during drying wafers or during the time
preceding the transport to a CVD apparatus, resulting in not uniform film
thickness in via filling by tungsten. On the other hand, when the
sputter-etching of a surface oxide film of the underlayers and the growth
of tungsten film are carried out continuously, no oxide film is formed on
the underlayer surface of the contact hole bottom before tungsten film
growth but, as described above with reference to via holes on aluminum
wiring, there arises the problem of decreased selectivity.
SUMMARY OF THE INVENTION
The object of the present invention is to provide, in filling a small via
hole by metal by means of CVD typically represented by tungsten selective
CVD, a method in which selectivity is not lowered even when a treatment
for cleaning small via hole underlayer surfaces is carried out, and an
apparatus therefor.
The above object can be attained, in via filling of via holes or contact
holes by CVD of tungsten, by successively conducting the following three
treatments:
1-(1) a surface cleaning treatment of small via hole bottom underlayer
surface (removing treatment of surface oxide layer etc.),
1-(2) a stabilization treatment of the insulating film surface layer
activated by said surface cleaning treatment, and
1-(3) a treatment of filling small via holes by metal by means of CVD of
tungsten using WF.sub.6 gas and reducing gas (H.sub.2, silane (SiH.sub.4)
and like compounds used alone or as a gas mixture); or by conducting the
above treatments (1) and (2) simultaneously and then conducting the third
treatment, in other words conducting the following two treatments
successively:
2-(1) a surface cleaning treatment of small via hole bottom underlayer
accompanied by no activation of the surface of insulating film on the
wafer (namely, removing treatment of surface oxide layer etc.), and
2-(2) a treatment of filling small via holes by metal by means of CVD of
tungsten using WF.sub.6 gas and reducing gas (H.sub.2, silane (SiH.sub.4)
and like compounds used alone or as a gas mixture); or, since substances
corrosive to underlayer produced by surface cleaning treatment sometimes
remain on wafers depending on the combination of the material of small via
hole underlayer with the kind of halogen gas used for the cleaning
treatment, by carrying out the following three treatments successively:
3-(1) a surface cleaning treatment of small via hole bottom underlayer
surface accompanied by no activation of the surface of insulating film on
the wafer (namely, removing treatment of surface oxide layer etc.),
3-(2) a treatment of removing substances corrosive to small via hole bottom
underlayer produced by the above surface cleaning treatment (namely,
anti-corrosive treatment), and
3-(3) a treatment of filling small via holes by metal by means of CVD of
tungsten using WF.sub.6 gas and reducing gas (H.sub.2, silane, and like
compound used alone or as a gas mixture).
Among the above-mentioned treatments, with respect to the treatment 1-(1),
sputter-etching treatment using inert gases such as Ar may be used.
Respecting the stabilization treatment of 1-(2), the insulating film
surface which has become rich in Si and active can be modified by plasma
treatment using halogen-containing chemical etching gases such as
Cl.sub.2, BCl.sub.3, CCl.sub.4, C.sub.2 Cl.sub.4, SiCl.sub.4, NF.sub.3,
SF.sub.6 and SiF.sub.4 each alone or as a mixture thereof with inert gases
such as Ar.
The stabilization treatment of 1-(2) may also be effected by another method
comprising heating a wafer in N.sub.2 (a pure gas or a mixture containing
a very small amount of O.sub.2) atmosphere.
With respect to the treatment 2-(1) wherein said (1) and 1-(2) are carried
out simultaneously, the surface oxide film of small via hole bottom
underlayer can be removed, with no accompanying activation of the
insulating film surface, by plasma treatment using halogen-containing
chemical etching gases employed in the above stabilization treatment of
1-(2) such as Cl.sub.2, BCl.sub.3, CCl.sub.4, C.sub.2 Cl.sub.4,
SiCl.sub.4, NF.sub.3, CF.sub.4, CHF.sub.3, SF.sub.6 and SiF.sub.4 each
alone or as a mixture thereof with inert gases such as Ar.
The etch amount necessary in said simultaneous treatments is just to
correspond to the amount of sputter-etching applied in 1-(1), whereas only
a slight modification of surface layer is effected in the stabilization
treatment of 1-(2) described before. When sputter-etching by Ar ions is
effected by using plasma of Ar gas alone as in the prior art, the surface
layer of insulating film becomes rich in Si and is activated owing to the
difference in sputtering yield among elements as described before, whereas
in the case where halogen gas plasma is used, even when the surface layer
becomes partly rich in Si, the Si-rich part is immediately removed by
halogen ions or radicals and the insulating film surface is ultimately not
activated; rather, selectivity in tungsten film growth is improved as
compared with a case where no such treatment is applied because active
parts rich in Si originating from defect etc. developed in forming the
insulation film are removed. However, depending on the combination of the
material of small via hole bottom underlayer with the kind of halogen gas
used for the surface cleaning treatment, there sometimes remain on wafers
substances corrosive to underlayer produced by the surface cleaning
treatment. That is, when the underlayer of small via hole bottom part is
aluminum wiring and a halogen gas containing chlorine is used, there will
remain such substances as AlCl.sub.3 which will react with moisture
contained in the air and corrode aluminum wiring when the wafer is taken
out into the air after tungsten film growth. In such a case, therefore, a
treatment of removing residual chlorine is necessary as an anti-corrosive
treatment after the surface cleaning treatment.
The removal of substances corrosive to small via hole bottom underlayers as
an anti-corrosive treatment can be effected by oxygen plasma treatment or
fluorine plasma treatment, to knock out the corrosive substances remaining
on the wafer with ions or radicals or to form a thin protective film on
the underlayer surface. A heat treatment is also effective as an
anti-corrosive treatment which comprises heating the wafer thereby to
evaporate off remaining corrosive substances.
The selective tungsten CVD treatment of 1-(2), 2-(2) or 3-(3) can be
accomplished by using one-stage CVD which comprises passing a gas mixture
of WF.sub.6 and a reducing gas such as H.sub.2, SiH.sub.4 etc. over a
heated wafer in a CVD reaction chamber set up for conducting selective
CVD, by using a two-stage CVD which comprises passing WF.sub.6, alone or
diluted with inert gases such as Ar, and then passing WF.sub.6 and the
above-mentioned reducing gas over a heated wafer, or by using a CVD of two
or more stages which comprises passing WF.sub.6 and H.sub.2 and then
passing WF.sub.6 and another reducing gas. Reducing gases which can be
used are, for example, H.sub.2, SiH.sub.4, Si.sub.2 H.sub.6, BH.sub.3,
PH.sub.3 etc. used alone or in a combination thereof.
In the plasma treatment apparatus using chemical etching gas used in the
present invention, plasma is generated by high frequency wave (of
preferably 10 kHz or more) as in conventional methods. However, if the
wall etc. of the treatment chamber is sputtered by generated plasma and
metallic contaminants adhere onto the wafer, tungsten will grow from the
contaminants serving as nuclei in the subsequent W-CVD, which may result
in lowering of selectivity. Therefore, it is important for exhibiting the
effect of the present invention that a cathode coupled type apparatus
wherein the wafer is negatively charged when high frequency wave is
applied to the electrode through a blocking capacitance be used as the
plasma treatment apparatus and the apparatus be constructed such that
parts which are close to the wafer surface and may possibly become the
source of metallic contaminants are covered by quartz plates.
The above-mentioned surface cleaning treatment of small via hole bottom
underlayers has an effect of removing by a physical treatment of
sputter-etching oxide films present on the unde | | |
