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Reduced CMOS-swing clamping circuit for bus lines    
United States Patent5498990   
Link to this pagehttp://www.wikipatents.com/5498990.html
Inventor(s)Leung; Wingyu (Cupertino, CA); Lee; Winston (San Francisco, CA); Hsu; Fu-Chieh (Saratoga, CA)
AbstractA memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.
   














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Drawing from US Patent 5498990
Reduced CMOS-swing clamping circuit for bus lines - US Patent 5498990 Drawing
Reduced CMOS-swing clamping circuit for bus lines
Inventor     Leung; Wingyu (Cupertino, CA); Lee; Winston (San Francisco, CA); Hsu; Fu-Chieh (Saratoga, CA)
Owner/Assignee     Monolithic System Technology, Inc. (San Jose, CA)
Patent assignment
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Publication Date     March 12, 1996
Application Number     08/417,511
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     April 5, 1995
US Classification     327/323 257/E21.526 327/309 327/319 365/189.06
Int'l Classification     H03K 005/08
Examiner     Tran; Toan
Assistant Examiner    
Attorney/Law Firm     Friel, Klivans; Norman R. Skjerven, Morrill, MacPherson Franklin & Hoffman; E. Eric ,
Address
Parent Case     CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 08/156,186, filed Nov. 22, 1993, now abandoned, which in turn is a continuation-in-part of U.S. patent application Ser. No. 07/927,564 filed Aug. 10, 1992, entitled "Fault-tolerant, High Speed Bus System and Bus Interface for Wafer Scale Integration", now abandoned, which, in turn is a continuation-in-part of U.S. patent application Ser. No. 07/865,410 filed Apr. 8, 1992 entitled "Circuit Module Redundancy Architecture", now abandoned, which, in turn is a continuation-in-part of U.S. patent application Ser. No. 07/787,984 filed Nov. 5, 1991 entitled "Wafer-scale Integration Architecture, Circuit, Testing and Configuration", now abandoned.
Priority Data    
USPTO Field of Search     327/202 327/203 327/309 327/312 327/313 327/314 327/315 327/316 327/317 327/318 327/319 327/320 327/321 327/322 327/323 327/324 327/327 327/328 327/332 327/363 365/189.06 365/189.05 365/230.05
Patent Tags     reduced cmos-swing clamping circuit bus lines
   
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