 |
Claims  |
|
|
We claim:
1. An electronic semiconductor structure comprising:
a plurality of semiconductor chips electrically coupled together in a system, at least one semiconductor chip of the plurality of semiconductor chips having a memory with m memory cells, wherein m is an integer;
a control circuit for coupling said plurality of semiconductor chips to external circuitry, said control circuit including selection means for facilitating access to a selected semiconductor chip, said selected semiconductor chip comprising one
semiconductor chip of the at least one semiconductor chip having a memory, said selected semiconductor chip corresponding to an address received from the external circuitry, said control circuit including a plurality of circuit paths;
a spare memory circuit functionally integrated with said plurality of circuit paths of said control circuit, and having n memory cells, wherein n is an integer and n.ltoreq.m, said spare memory circuit being electrically connected to said at
least one semiconductor chip having said memory and being programmable such that a single memory cell of the n memory cells of the spare memory circuit can functionally replace a single failed memory cell of said m memory cells of the at least one
semiconductor chip having said memory.
2. The electronic semiconductor structure of claim 1, wherein each semiconductor chip of said plurality of semiconductor chips comprises a semiconductor memory chip having said memory with m memory cells.
3. The electronic semiconductor structure of claim 2, wherein said semiconductor memory chips are mechanically coupled together as a multichip stack.
4. The electronic semiconductor structure of claim 3, wherein said spare memory circuit is programmable to account for multiple memory cell failures in the multichip stack by functionally replacing each failed memory cell with a memory cell of
the n memory cells of the spare memory circuit.
5. The electronic semiconductor structure of claim 1, wherein said plurality of semiconductor chips comprises a plurality of DRAM chips.
6. The electronic semiconductor structure of claim 5, wherein said spare memory circuit comprises a SRAM circuit, said plurality of DRAM chips and said SRAM circuit being mechanically coupled together in said system.
7. The electronic semiconductor structure of claim 1, wherein said spare memory circuit is programmable such that a plurality of memory cells of the n memory cells can functionally replace a corresponding plurality of failed memory cells of the
at least one semiconductor chip having said memory with m memory cells.
8. The electronic semiconductor structure of claim 1, wherein said spare memory circuit is integrated with said control circuit as an integrated circuit.
9. The electronic semiconductor structure of claim 8, wherein said plurality of semiconductor chips comprises a plurality of semiconductor memory chips, each semiconductor memory chip having said memory with m memory cells, said plurality of
semiconductor memory chips being mechanically coupled together as a multichip stack, and wherein said integrated circuit resides on a separate logic/memory chip mechanically and electrically coupled to said multichip stack.
10. The electronic semiconductor structure of claim 1, wherein said plurality of semiconductor chips comprises a plurality of semiconductor memory chips, each semiconductor memory chip having said memory with m memory cells, said semiconductor
memory chips being mechanically coupled together as a multichip stack, and wherein said spare memory circuit and said control circuit reside on a separate semiconductor chip mechanically and electrically coupled to said multichip stack.
11. The electronic semiconductor structure of claim 10, wherein said multichip stack includes an end surface and at least one side surface, and wherein said separate semiconductor chip is mechanically affixed to said multichip stack at either
said end surface or said at least one side surface.
12. The electronic semiconductor structure of claim 1, wherein each semiconductor chip of said plurality of semiconductor chips comprises a semiconductor memory chip having said memory with m memory cells, said plurality of semiconductor memory
chips being mechanically coupled together as a multichip stack, and wherein said electronic semiconductor structure further comprises an endcap mechanically coupled to said plurality of semiconductor memory chips as part of said multichip stack, said
spare memory circuit and said control circuit residing on said endcap.
13. The electronic semiconductor structure of claim 1, wherein said plurality of semiconductor chips, said control circuit and said spare memory circuit are mechanically coupled together in a multichip package, and wherein said electronic
semiconductor structure further comprises means for electrically programming said spare memory circuit within said multichip package.
14. The electronic semiconductor structure of claim 13, wherein said means for electrically programming includes a programmable control means for retaining an address of the single failed memory cell of said m memory cells of the at least one
semiconductor chip having said memory.
15. The electronic semiconductor structure of claim 1, wherein said plurality of semiconductor chips comprise a plurality of DRAM chips, and wherein said control circuit further comprises means for interfacing with said external circuitry using
signals of a type for a single DRAM chip.
16. The electronic semiconductor structure of claim 15, wherein said spare memory circuit includes an address input, a RAS input, a CAS input, a RAS comparator coupled to said RAS input and said address input, and a CAS comparator coupled to
said CAS input and said address input, and wherein an address presented on said address input is examined in said RAS comparator when said RAS input is engaged and said address is examined in said CAS comparator when said CAS input is engaged such that
attempted access to said single failed memory cell is detected.
17. The electronic semiconductor structure of claim 16, wherein said spare memory circuit comprises a RAS failed address store separate from a CAS failed address store, said RAS failed address store being coupled to said RAS comparator and said
CAS failed address store being coupled to said CAS comparator.
18. The electronic semiconductor structure of claim 16, wherein said spare memory circuit further comprises a redundant word generator coupled to said RAS comparator and a redundant bit generator coupled to said CAS comparator such that faulty
bit replacement and faulty word replacement are both facilitated by said spare memory circuit.
19. The electronic semiconductor structure of claim 15, wherein said control circuit comprises data input buffers for reducing the electrical load presented by the control circuit to said external circuitry to substantially that of a single DRAM
chip.
20. The electronic semiconductor structure of claim 15, wherein said control circuit includes means for interfacing using JEDEC DRAM compatible signals to said external circuitry.
21. An electronic semiconductor structure comprising:
a plurality of semiconductor chips electrically and mechanically coupled together in a packaged system;
a sparing circuit electrically coupled to the plurality of semiconductor chips and comprising part of the packaged system;
electrically programmable, non-volatile means for activating the sparing circuit to permanently function in combination with at least one semiconductor chip of the plurality of semiconductor chips in the packaged system;
a control circuit for coupling said plurality of semiconductor chips to external circuitry, said control circuit including selection means for facilitating access to a selected semiconductor chip of the at least one semiconductor chip, said
selected semiconductor chip corresponding to an address received from the said external circuitry, said control circuit including a plurality of circuit paths common to, and functionally integrated with, said sparing circuit.
22. The electronic semiconductor structure of claim 21, wherein said sparing circuit comprises a logic circuit, and wherein said electrically programmable, non-volatile electrical means comprises means for activating said logic circuit to
permanently operate in combination with the at least one semiconductor chip without physical rewiring of an electrical connection within the packaged system.
23. The electronic semiconductor structure of claim 21, wherein said spare circuit comprises a memory circuit, and wherein said electrically programmable, non-volatile means comprises means for activating said memory circuit to permanently
operate in combination with the at least one semiconductor chip without physical rewiring of an electrical connection within the packaged system.
24. The electronic semiconductor structure of claim 23, wherein said memory circuit comprises a volatile memory circuit and wherein said electrically programmable, non-volatile means for activating comprises one of an electrical fuse array, a
non-volatile memory, and an electrically programmable logic array.
25. The electronic semiconductor structure of claim 21, wherein said electrically programmable non-volatile means comprises part of the packaged system, and wherein said electronic semiconductor structure further comprises a structure
surrounding said plurality of semiconductor chips, said sparing circuit and said electrically programmable non-volatile means. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
TECHNICAL FIELD
The present invention relates in general to high density electronic circuit packaging, and more particularly, to techniques for providing programmable sparing capability to a multichip package, either with or without the inclusion of a spare
chip(s) in the multichip package.
BACKGROUND ART
The market for high density electronic circuit packages of multiple semiconductor chips continues to increase. Two common types of semiconductor chip stacks are the vertically-extending (or "pancake") stack and the horizontally-extending (or
"breadloaf") stack.
U.S. Pat. Nos. 4,525,921 and 4,646,128 by Carson et al. disclose structure and fabrication techniques for producing one type of high density, multichip electronic package. These documents describe a semiconductor chip stack consisting of
multiple integrated circuit chips adhesively secured together. A metallized pattern is provided on at least one side surface of the stack for electrical connection of the stack to external circuitry. This metal pattern typically includes both
individual contacts and bussed contacts. The stack is positioned on an upper surface of a substrate so that electrical contact can be made between the stack metallization pattern and a substrate surface metallization pattern.
Various alternate stack structures and electrical interconnection possibilities have also been described. For example, reference U.S. patent application Ser. No. 08/000,826 entitled, "Multichip Integrated Circuit Packages and Systems," U.S.
patent application Ser. No. 08/120,876, entitled "Integrated Multichip Memory Module, Structure and Fabrication," and U.S. patent application Ser. No. 08/120,993, entitled, "Integrated Memory Cube, Structure and Fabrication," which are all commonly
assigned to the same assignee as the present invention, and which are all hereby incorporated herein by reference.
At least one redundant chip(s) is often provided in a semiconductor chip stack so that if one or more of the primary chips in the stack should fail following stack fabrication and/or stressing (i.e., burn-in), the redundant chip(s) may be
"invoked" to provide the electronic circuit package with the desired performance level. This activity is referred to in the art as "sparing." Invoking of a redundant or spare semiconductor chip is typically physically accomplished at the package level
of assembly, which normally entails wirebonding the chip to a lead frame and then encapsulating the entire assembly in a polymer material. Thus, burn-in and invoking of the redundant semiconductor chip ("sparing") in a multichip package must be
performed prior to encapsulation and final testing of the semiconductor chip stack. Unfortunately, chip failure can occur during final stack packaging, in which case the resultant electronic circuit package must be discarded.
Conventional stack "breadloaf" sparing technology is based on provision of a programmable via in combination with a thin film metallization layer on a side-surface of an unpackaged semiconductor chip stack. Such technology enables access to the
spare chip(s) in the stack while still maintaining a fixed pattern and fixed function solder bump array. Alternatively, additional stack side-face wiring channels may be employed to independently access a spare chip(s) in the semiconductor chip stack.
An important application of today's chip stacking technology is in the fabrication of computer memory systems. Traditionally, computer memory systems are assembled from many types of memory chips, such as DRAMs, SRAMs, EPROMs and EEPROMs. The
number of storage devices per memory chip technology generation varies but increases over time with more devices per chip being delivered with each succeeding generation, thereby providing greater memory capacity. When a next generation memory chip
becomes available, the number of chips needed to make a given memory system is correspondingly reduced. With fewer memory chips needed, the resultant memory system becomes physically smaller.
The next generation DRAM memory chips have traditionally increased by 4.times. the number of bits compared with current generation technology. For example, assume that the current generation of memory chips comprises 16 megabit (Mb) chips, then
by industry standards the next generation comprises 64 Mb memory chips. This 4.times. advancement from one generation of memory chips to the next generation is typically accomplished with corresponding advancement in semiconductor tool and process
technologies, for example, sufficient to attain a 2.times. reduction in surface geometries. Due to this interrelationship, a significant interval of time can pass between generations of memory chips. Therefore, a genuine improvement in memory system
design and fabrication would be attained if current generation memory chips could be assembled to have the same functions and physical dimensions of an anticipated, next generation memory chip. The multichip memory packages and fabrication techniques
presented in the above-incorporated patent applications provide such an improvement.
Experience has shown that burn-in stressing of semiconductor chips in a multichip package predominately results in only a few single bit (i.e., "memory cell") fails per failing semiconductor chip. For example, in a typical failed memory chip,
there might be 10-15 memory cells in the chip which fail testing following burn-in stressing. Currently, there is no cost-effective technology to spare only these failed bits, particularly after the chip has been encapsulated; that is, at least not
without providing a redundant semiconductor chip. Therefore, an entire semiconductor chip stack might have to be discarded because of only a few failed memory cells. Since single memory cell failures are the predominant mode of failure of a
semiconductor chip's memory, an alternative stack sparing approach based on replacement of only the failed memory cell(s), rather than replacement of the entire semiconductor chip, would clearly have commercial advantages.
As another problem, most semiconductor random access memories (RAMs) utilize power-on latches which assume a state based on non-volatile data. Fuses, for instance, can be opened to influence latch state during power-up. Such circuit
technologies are commonly used for memory array redundancy allocation. Unfortunately, in a high radiation flux environment, an ion impact episode may cause these redundancy latches to flip; thereby activating or deactivating random redundancy.
Obviously, this could have catosphropic consequences to a memory dependent machine.
In general, various novel techniques for providing programmable sparing capability to a multichip package, either with or without the inclusion of a spare chip(s) in the multichip package, are presented herein. These techniques address each of
the above-noted drawbacks of the existing multichip stack fabrication art.
DISCLOSURE OF INVENTION
Briefly described, the present invention comprises in one aspect an electronic semiconductor structure wherein a plurality of semiconductor chips are electrically coupled together to form a system. At least one semiconductor chip in the system
has a memory with m memory cells, wherein m is an integer. A spare memory circuit having n memory cells is also provided, wherein n is an integer and n.ltoreq.m. The spare memory circuit is electrically connected to the plurality of semiconductor chips
and is programmable such that single memory cells of the n memory cells of the spare memory circuit can functionally replace a single failed memory cell of the m memory cells of the at least one semiconductor chip in the system. If desired, the spare
memory circuit could be provided physically separate from the plurality of semiconductor chips, or on a semiconductor chip comprising one of the plurality of semiconductor chips, or on each semiconductor chip of the plurality of semiconductor chips.
In another aspect, an electronic semiconductor structure is provided wherein a plurality of semiconductor chips are electrically coupled together to form a system. A controller circuit is electrically coupled to the system and contains
non-volatile means for sparing the system by permanently selecting after encapsulation at least one semiconductor chip of the plurality of semiconductor chips to be active within the system.
In yet another aspect, a packaged electronic semiconductor structure is described wherein, again, a plurality of semiconductor chips are electrically coupled together in a packaged system. A spare circuit is mechanically and electrically coupled
to the plurality of semiconductor chips so as to comprise part of the packaged system and electrical means are provided for activating the spare circuit to function in combination with the plurality of semiconductor chips in the packaged system.
In a further aspect, the invention comprises a method for sparing a packaged semiconductor device having multiple semiconductor chips each with a memory of m memory cells, wherein m is an integer. The device also includes a spare memory circuit
having n memory cells, wherein n is an integer and n.ltoreq.m. The multiple semiconductor chips and the spare memory circuit are electrically coupled together. The sparing method includes the steps of: for each semiconductor chip of the multiple
semiconductor chips, testing operability of and monitoring for failure at a memory cell of the m memory cells of the memory; and after detecting a failed memory cell, programming a memory cell of the n memory cells of the spare memory circuit to
functionally replace the failed memory cell.
In still another aspect, the invention comprises a method for fabricating a multichip semiconductor package including: providing a plurality of semiconductor chips, each having two substantially parallel planar main surfaces; mechanically and
electrically coupling together the plurality of semiconductor chips such that at least one planar main surface of each semiconductor chip is coupled to a planar main surface of an adjacent semiconductor chip; and providing and electrically coupling a
controller circuit to the multichip semiconductor stack, the controller circuit including programmable, non-volatile means for sparing the multichip semiconductor stack.
To summarize, various techniques are discussed for sparing a stack subsequent to sealing a stack within a microelectronic package. Personalization of the package is thus attainable at final testing, along with permanent sparing thereof, for
example, by using an electrical fuse array, non-volatile memory or an electrical programmable logic array. The programmable methodologies presented can also be used to invoke various logic functions such as I/O reconfiguration, error correction code
(ECC), self-timed refresh, address reconfiguration, or any desired application specific function. When the logic function and selecting function are combined, the resultant circuitry can be incorporated almost anywhere within the stack.
In addition, techniques are presented for sparing a multichip package by replacing only failed memory bits, i.e., without the use of a redundant semiconductor chip in the stack. Thus, greater density is achieved, and fixed segmentation points in
a large stack fabrication process are possible and cost-effective, while still maintaining high stack yield. Significant stack fabrication/test cost reductions are achieved by eliminating the need for functional, but not accessed, spare chips. Sparing
of memory chip fails caused by ion bombardment after packaging is also possible.
Further, the invention enables the "up-grading" of non-conforming chips when incorporated into a multichip stack. Specifically, the invention can result in the replacement of failed memory cells from a DRAM stack with functional memory cells
contained in a SRAM cache. Thus, the invention is not necessarily limited to simply replacing failed memory cells that occur during stressing. Rather, cell replacement can also occur for memory cells that fail due to other reasons, even to the extent
of taking semiconductor chips that as single chips would be considered non-conforming, incorporating them into the stack, and replacing the failed memory cells in those chips with the SRAM macro cells. Further, the cell replacement technique presented
is not restricted to DRAM chips. The invention can be applied to any number of technologies, including SRAM, flash, etc., for which sparing is needed for cost effective fabrication of a multichip package.
BRIEF DESCRIPTION OF DRAWINGS
These and other objects, advantages and features of the present invention will be more readily understood from the following detailed description of certain preferred embodiments of the invention, when considered in conjunction with the
accompanying drawings in which:
FIG. 1 is a partially exposed top view of a multichip package in accordance with one embodiment of the invention wherein a logic circuit and a non-volatile sparing controller are electrically coupled;
FIG. 1a is an exposed side elevational view of the multichip package of FIG. 1;
FIG. 2 is an exposed end elevational view of the multichip package of FIG. 1;
FIG. 3 is a schematic of one embodiment of a non-volatile spare circuit controller for the multichip package of FIG. 1;
FIG. 4 is a partially exposed top view of another embodiment of a multichip package in accordance with the present invention wherein a logic/SRAM chip is affixed to an endcap chip of a semiconductor chip stack;
FIG. 4a is an exposed side elevational view of the multichip package of FIG. 4;
FIG. 5 is an exposed end elevational view of the multichip package of FIG. 4;
FIG. 6 is a block diagram representation of one embodiment of a logic/SRAM circuit in accordance with the invention for the multichip package of FIG. 4;
FIG. 7 is a block diagram representation of one embodiment of a sparing circuit in accordance with the invention for the logic/SRAM circuit of FIG. 6;
FIG. 8 is a block diagram representation of one embodiment of a SRAM decoder and SRAM circuit for the sparing circuit of FIG. 7;
FIG. 9 is an elevational view of one stacking/packaging arrangement in accordance with the invention showing connection of a logic/SRAM chip to a multichip stack;
FIG. 10 is an elevational view of another stacking/packaging arrangement in accordance with the invention showing connection of a logic/SRAM circuit embedded within an endcap chip of a multichip stack; and
FIG. 11 is an elevational view of still another stacking/packaging arrangement in accordance with the invention showing connection of a logic/SRAM chip to a side-surface of a multichip stack.
BEST MODE FOR CARRYING OUT THE INVENTION
Broadly stated, the present invention comprises various electronic semiconductor structures and fabrication/sparing methods for improving multichip package yield, principally subsequent to encapsulation and burn-in of the package. More
particularly, various multichip stack structures and packaging techniques are described for enhancing package yield by providing the capability to spare memory ranging in size from one or more memory cells to an entire chip or chips.
Reference is now made to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
FIGS. 1, 1a & 2 depict one embodiment of a multichip package, generally denoted 10, in accordance with the invention. Package 10 includes by way of example five identical-type integrated circuit chips 12, only four of which need to be active
with the fifth chip comprising a redundant semiconductor chip. In one embodiment, each chip 12 may comprise a memory chip such as a 4 Mb dynamic random access memory (DRAM) chip. Semiconductor chips 12 are coupled together in a vertically-extending
stack referred to in the art as a "pancake" configuration. An endcap 14, for example, fabricated of a ceramic or organic material, is disposed above an uppermost semiconductor chip 12 in the vertically-oriented stack. The multichip package depicted in
FIGS. 1, 1a & 2 comprises an SOJ package wherein encapsulant 36 surrounds the multichip stack and pins/lead frame 38 provide electrical connection to the semiconductor chips of the stack. FIGS. 9-11 depict various alternate mechanical arrangements for
interconnecting semiconductor chips to form a stack.
Disposed above endcap 14 is a logic circuit chip 16 and a non-volatile programming means, labelled "sparing control" 24, along with a multitude of pads 20 which electrically connect through endcap 14 by metallized via holes, such as metallized
via 32, and appropriate transfer metallization 26 to side surface bussings 34. Bussings 34 electrically connect to the multiple chips 12 in the package. Pads 18 and 30 are also disposed above circuit chip 16 and sparing control chip 24, respectively.
Traditional wire bond 22 can be used to interconnect chips 16 and 24 and to connect the chips to selected metallized via holes (32) through endcap 14, for coupling to side surface metallization 34 via an appropriate transfer metallization 26 above the
uppermost semiconductor chip 12 in the stack.
Wiring 26 extends outwardly to the stack's side surface bussings 34 and electrically connects thereto via, e.g., conventional T-connections (FIG. 2). Note that transfer metallization 26 may be employed to electrically contact to an active
surface of an adjacent semiconductor chip or to electrically connect a metallized via 32 to side surface metallization 34 of the multichip package. One preferred approach to electrically connecting a semiconductor chip disposed on an end surface of a
multichip stack is described in the above-incorporated application entitled "Multichip Integrated Circuit Packages and Systems," Ser. No. 08/000,826.
Various implementations of the non-volatile programmable means, i.e., sparing control 24, are possible. Again, in this embodiment the goal of programmable means 24 is to provide a mechanism for selecting those semiconductor chips 12 to be active
in the stack. More particularly, package 10 may be configured such that by default the four lowermost semiconductor chips in the stack are active, i.e., unless testing subsequent to encapsulation and burn-in establishes that one of these semiconductor
chips is defective. In such a case, programming means 24 is activated to deselect the failed semiconductor chip and substitute therefore the uppermost semiconductor chip 12 in the stack. Obviously, this assumes that there is only one failed
semiconductor chip in the multichip package. If desired, multiple redundant semiconductor chips could be incorporated into the stack prior to encapsulation. The decision whether to incorporate one or more redundant semiconductor chips into the stack
can be based upon empirical yield data for the particular type semiconductor chips at issue. Alternatively, a "spare chip" not redundant of the particular type semiconductor chips at issue could be incorporated into the stack as described below.
Programming of non-volatile program means 24 is electrically controlled after encapsulation through a programmable control bus 28.
Sparing of a multichip package after encapsulation and final testing can be accomplished using a number of different non-volatile programming means. For example, a first option might be to employ an electrical fuse array, either on a second
silicon chip (e.g., chip 24) or by invoking a fuse array integrated with the logic circuit chip 16. Such fuses can be open circuited via programmable control lines connected to a spare package pin or multiplexed with functional package pins. For
instance, package address pins can be used to "point" to specific fuses. Then by driving current through the pin(s), the fuse in question can be open circuited. With such a capability, the spare control 24 can be "permanently" (non-volatilely) directed
to access only semiconductor chips of the stack which have tested functional subsequent to encapsulation and burn-in. Alternatively, non-volatile memory may be accessed via a spare package pin(s) to electrically program a data output configuration
similar to that of a fuse network.
The control circuit of FIG. 3, which presents still another non-volatile programming option, employs electrically programmable logic arrays (EPLAs) to program a sparing algorithm at final testing of the multichip package. This circuit includes
complementary metal oxide semiconductor (CMOS) circuits with P-channel field-effect transistors (PFETs) indicated in the drawing by a rectangle with a diagonal line formed therein and a control element or gate electrode arranged adjacent thereto and with
N-channel field-effect transistors (NFETs) indicated by a rectangle without a diagonal line and with a control element or gate electrode arranged adjacent thereto.
Data is scanned into a data register 50 at a rate dictated by a common clock 51. Coupled to data register 50 are a plurality of non-volatile logic circuits 54, only one of which is shown. Each bit location in data register 50, e.g., location
53, has a corresponding logic circuit 54 associated therewith. A zero `0` at the corresponding bit 53 of data register 50 forward biases a PFET 58, which permits a floating gate NFET 56 to receive an elevated voltage at its gate `G` and drain `D`. As a
result, floating gate structure 56 absorbs hot electrons which increases the threshold voltage of the device, driving it to a permanently "off" state. A PFET 62 configured as a bleeder is connected to the drain `D` of NFET 56 to ensure that the drain
`D` never floats. A buffer 64 is employed to amplify the floating gate network to CMOS levels for input to an appropriate bit of a compare register 52, which has `n` bits that correspond to `n` bits of data register 50. Programming of a `0` in the data
register thus produces a `1` in the compare register. After programming, compare register 52 holds the logic vector for the sparing algorithm. Scan out can be used to verify programming accuracy.
The same non-volatile programming methodologies for substituting chips can be used to invoke various logic functions, collectively referred to herein as "feature circuits." Such logic functions, which can reside on logic chip 16 (FIG. 1), might
include logic for I/O reconfiguration, ECC, self-timed refresh, address reconfiguration, or almost any application specific function desired. Thus, multichip package personalization may be completed on a customer-specific basis. The physical wiring of
FIGS. 1, 1a & 2 supports test, burn-in and application, while FIG. 3 depicts an embodiment for programming final logic functions and selecting good chips without rewiring any electrical connection. When the logic function and the non-volatile selecting
function are combined, the total system can be placed anywhere within the multichip stack, for example, reference FIGS. 10 and 11 (discussed below).
As noted initially, for certain applications it may be desirable to avoid the inclusion of one or more redundant semiconductor chip(s) in a multichip package, yet to still provide a sparing capability, particularly after encapsulation and burn-in
of the package. This is because inclusion of a redundant semiconductor chip in a multichip stack necessarily results in a greater stack height (or length), more complex package side-surface wiring, additional test time and, ultimately, additional
product cost.
The majority of today's multichip packages comprise memory modules wherein multiple memory chips are electrically and mechanically integrated within the package. Failure analysis has shown that testing subsequent to burn-in (i.e., after
encapsulation) may result in failure of a memory chip at, for example, 5-15 memory cells of the memory array. Thus, another aspect of the present invention comprises the sparing of a multichip package after encapsulation, without the use of a redundant
semiconductor chip within the stack, by substitution of individual functional memory cells for identified failed memory cells in one or more semiconductor chips of the multichip package.
FIGS. 4, 4a & 5 depict one embodiment of a multichip stack, generally denoted 110, in accordance with this aspect of the invention. In this stack, four semiconductor chips 112 are mechanically connected such that at least one planar main surface
of each memory chip is coupled to a planar main surface of an adjacent memory chip, resulting in the chips residing one above the other as shown in FIGS. 4a & 5. By way of example, package 110 could comprise four DRAM chips. However, the concepts
described herein are equally applicable to other semiconductor chips, such as logic chips, wherein memory is included on at least one of the chips and a failed memory cell location is identified during post-burn-in testing.
In the embodiment shown, an endcap 114, positioned above the four semiconductor chips 112, has a logic/SRAM chip 116 affixed thereto. Analogous to endcap 14 of FIG. 1, endcap 114 facilitates electrical connection of chip 116 to semiconductor
chips 112 via metallized vias 132 and transfer metallization 126. Chip 116 contains contact pads 118 on an upper surface thereof which can be wire bonded 122 to surrounding pads 120 disposed above endcap 114, such as shown. Pads 120 might be
electrically connected to side surface metallizations 134 through connection to appropriate metallized vias 132 and transfer metallization 126. In this embodiment, the multichip package is encapsulated 136 to form an SOJ package having connection pins
138 extending therefrom.
Central to this aspect of the invention is the provision of programmable, spare memory cells (e.g., in the form of a SRAM macro) that are electrically connected to the multichip stack to provide substitute memory cells for failed memory cells in
the stack. In the embodiment shown, the SRAM macro is integrated with a logic macro, which coordinates communication with the package via appropriate addressing and I/O buffering logic. One embodiment of such a logic chip is described in the
above-incorporated U.S. patent application entitled "Integrated Multichip Memory Module, Structure and Fabrication," Ser. No. 08/120,876 However, it is important to note that the spare memory cells could be disposed anywhere within the multichip stack,
including on each semiconductor chip of the stack or on a dedicated semiconductor chip integrated with the multichip stack.
By way of overview, the SRAM macro provides access to spare memory cells at retrieval rates equal to or greater than access rates to the semiconductor chips of the stack, e.g., dynamic random access memory (DRAM) chips. This is accomplished by
storing the address of a failed memory cell location in the logic/SRAM chip by some means of non-volatile data recordation, such as, but not limited to, an electrically programmable fuse bank. The fuse bank stores the complete fail pattern for the
multichip stack as address information. Then during normal stack access, incoming address information is compared with the stored failed cell patterns, and in the event of a valid compare, the SRAM is activated for a read or write of data through the
I/O buffering logic. Simultaneously, the DRAM stack data is disabled.
An integrated multichip memory package in accordance with the invention can be implemented using any of a variety of available memory chip architectures. For example, four 16 Mb DRAMs can be assembled into a memory stack which can emulate
exactly a next generation memory chip, i.e., a 64 Mb DRAM (in this regard, reference the above-incorporated application entitled "Integrated Multichip Memory Module, Structure and Fabrication," Ser. No. 08/120,876). The integrated function is
accomplished by associating control logic chip 116 with the stack of four memory chips (FIG. 4a). Preferably the resultant module of four 16 Mb DRAMs plus logic chip can be sized to fit into an industry standard 64 Mb package, or if desired, a smaller
package. Sparing capabilities in accordance with this aspect of the present invention facilitates achieving the goal.
An overview of one embodiment of a control logic circuit/SRAM 116 in accordance with this aspect of the invention is depicted in FIG. 6. Logic circuit 116 receives address and control inputs 117 from a memory controller (not shown) or other
external processing unit. In this example, logic/SRAM circuit 116 is designed to industry standards for a next generation, single memory chip's input timings. For example, if the semiconductor memory chips in the stack 113 comprise 64 Mb memory chips,
then logic 116 would have the same I/O characteristics as a 256 Mb single memory chip.
As a further example, 4 Mb.times.4 12/10 addressable memory chips might be used to define multichip package 110 (FIG. 4a). In such a case, each chip provides 1/4 of a 64 Mb memory array. Assume further that a desired product is a 13/11
addressable, 16 Mb.times.4 array. Wit | | |
