Maximum likelihood sequence detector

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This invention relates to a maximum likelihood (ML) detector for estimating a data symbol in a sequence of transmitted data symbols received over a communication channel, and further relates to an equaliser and/or decoder incorporating such a detector.

In the present specification digitised signals are referred to as data.

BACKGROUND OF THE INVENTION

Intersymbol interference is a recognised problem resulting from transmission of data on a dispersive communication channel and an equalisation process is effected on the received signal in order to estimate the individual data symbols which were originally transmitted. Various types of equaliser are known but of particular interest in the present context are so-called maximum likelihood (ML) detectors.

Furthermore, for the purpose of forward error correction, data may be convolutionally encoded before it is transmitted. (Forward error correction means that the data is corrected at the receiver without the need for retransmission.) A ML detector may also be used for decoding convolutionally encoded data.

In the context of ML detection, a trellis diagram is commonly used to represent the progression of states with the passage of time. It is noted here that the number of states S is given by the equation S=N.sup.c where N is the number of symbols in the data alphabet used and C is the constraint length (ie. extent of intersymbol interference). Thus for a 2-symbol alphabet and a constraint length of 4 there are 16 possible states.

The term `node` is usually used to designate a particular state at a particular time on a trellis diagram.

The arc or path representing the transition between two states (nodes) adjacent in time is known as a `branch` and the associated `branch metric` is an indication of the likelihood of the particular transition occurring. The `partial path metric` is the overall probability that a particular partial path to the left of the node at the current stage n of the trellis represents the correct sequence of state transitions, taking into account the observed sample of the received data at the current trellis transition and the branch metric. The term `partial path` is construed accordingly. This is the meaning of the terms partial path and partial path metric as they are used in the present specification, but the terms `path` and `path metric` are also used to convey the same meaning. The `previous partial path metric` thus refers to the path metric at the previous stage n-1 of the trellis. The overall path i.e. the path between the beginning and the end of the trellis which has the maximum path metric is the maximum likelihood path which essentially represents the best estimate of the data symbols actually transmitted.

In theory a maximum likelihood (ML) or maximum a-posteriori (MAP) detector may be used wherein the branch metrics are calculated for every branch in the trellis diagram. The path metric for every path in the trellis diagram is then determined, and finally the path for which the overall path metric is a maximum is chosen. The sequence of symbols corresponding to this path is the estimate of the symbols actually transmitted. The difficulty with this approach is that the number of paths increases exponentially as the trellis diagram is traversed from left to right.

The so-called Viterbi detector is a computationally more efficient version of a ML detector which exploits the special structure of the detector to achieve a complexity that grows linearly rather than exponentially along the trellis. Hence, a Viterbi detector has the advantage that it requires a constant computation rate per unit time. For each node, the Viterbi detector selects the path having the largest partial path metric, called the `survivor path` for that node. All partial paths other than the survivor path are discarded because any other partial path has by definition a smaller partial path metric, and hence if it replaced the survivor path in any overall path, the path metric would be smaller.

At each stage of the trellis it is not known which node the optimal path must pass through and so it is necessary to retain one survivor path for each and every node. The survivor path and associated path metric have to be stored in memory for each node at a stage n in the trellis in order for the algorithm to proceed to the next stage n+1.

When the terminal node of the trellis has been reached it is possible to determine the unique path of maximum likelihood representing the estimation of the symbols actually transmitted. It is only at this stage that the estimated data symbols can be read off by effecting a "trace-back" along the identified maximum likelihood path.

Despite its improved efficiency mentioned above, it has to be noted the Viterbi algorithm remains intrinsically computationally elaborate and therefore the processing circuitry for implementing the algorithm tends to be complex, costly and power consuming. Furthermore, the level of complexity means that a substantial area of semiconductor material is required for realization of a conventional Viterbi detector in integrated circuit (IC) form.

European Patent Application No. 0,398,690, which was published after the priority date of the subject application, relates to circuitry for implementing the Viterbi algorithm, wherein the states of the bits of a defined time interval are processed utilizing the circuitry in serial form for indicating the data symbol.

SUMMARY OF THE INVENTION

According to the present invention there is provided a maximum likelihood (ML) detector for estimating a data symbol in a sequence of transmitted data symbols received over a communication channel, wherein a plurality of different states is associated with the transmission of said data symbols, the detector comprising a plurality of data sources relating respectively to state transition probabilities and observed values of the received data symbols, and means for calculating the partial path metrics for each state using values from said data sources, characterised in that the calculating means comprise common add/accumulate means for performing repeated additive arithmetic operations and for storing the cumulative result thereof, and in that multiplexing means are provided for selectively coupling said data sources in a predetermined order to said add/accumulate means to implement the partial path metric calculation.

A ML detector in accordance with the invention has the advantage that, by time multiplexing, the same processing circuitry, viz. the add/accumulate means, can be used repeatedly to perform all of the arithmetic steps required to calculate the partial path metrics. Since no further arithmetic processing means are required, the hardware complexity is dramatically reduced and consequently the detector can be implemented in integrated circuit form using significantly less semiconductor (e.g. silicon) area.

The ML detector may include a further data source relating to terms characteristic of the communication channel, and means for calculating the branch metrics using values from said further data source and from the data source relating to the observed values of the received data symbols, wherein the branch metric calculating means comprise said common add/accumulate means, the multiplexing means being adapted for selectively coupling said data sources in a predetermined order to said common add/accumulate means to implement the branch metric calculations. Hence, the same add/accumulate means are used, again by time multiplexing, also to calculate the branch metrics. Clearly, this arrangement further helps to reduce hardware complexity by maximising re-use of the same add/accumulate means.

In one embodiment the predetermined order in which the multiplexing means couples the data sources to the add/accumulate means is such that for each state at a given time a first partial path metric is calculated in respect of a state transition corresponding to the transmission of a first symbol type (e.g. a binary "1"), and subsequently a second partial path metric is calculated in respect of a state transition corresponding to the transmission of a second symbol type (e.g. a binary "0"), means being provided for storing said first partial path metric, the detector further including means for comparing the first partial path metric in the storage means and the second partial path metric in the add/accumulate means and for selecting the larger of said first and second partial path metrics for each state in turn. In this case only a single adder/accumulator is required to implement the arithmetic processing in a complete Viterbi processor.

In an alternative embodiment the calculating means comprises a first add/accumulate means for calculating for each state in turn a first partial path metric in respect of a state transition corresponding to the transmission of a first symbol type (e.g. a binary "1"), and a second add/accumulate means for calculating for each state in turn a second partial path metric in respect of a state transition corresponding to the transmission of a second symbol type (e.g. a binary "0"). Suitably the first and second add/accumulate means are arranged to operate in parallel. This arrangement has the advantage of reducing processing time (because the two partial path metrics associated with a given state can be calculated simultaneously), but at the expense of an including an additional add/accumulate means. On the other hand, this arrangement does dispense with the additional storage means for storing the first partial path metric required in the previous embodiment. Means may also be included for comparing the first and second partial path metrics in said first and second add/accumulate means respectively and for selecting the larger of said first and second partial path metrics for each state.

In order to implement the Viterbi algorithm in either of the aforementioned embodiments, means are preferably included for storing the larger of the first and second partial path metrics for each state. In addition, means may be provided for storing for each state either a first or a second symbol (e.g. a "1" or a "0", viz. a so-called survivor bit) depending on which of the first and second partial path metrics is the larger. Means may be provided for reading from the data symbol storage means an estimate of the most likely sequence of transmitted data symbols. This reading step is commonly known in the art as "trace-back".

It is noted here that a maximum likelihood detector in accordance with the invention may be utilised in an equaliser and/or a decoder.

It is particularly advantageous not only that the same adder/accumulator can be used repeatedly within the equalisation and decoding functions, but also that the same adder/accumulator can be re-used by multiplexing in such manner that the same detector functions sequentially both as the equaliser and as the decoder. This has important implications in practice because both the equaliser and the decoder can be realised on a unitary IC (i.e. on a single "chip"). In this case the same Viterbi processor can effectively be time-shared by the respective equalisation and decoding functions.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 is part of a 16-state trellis diagram illustrating the possible state transitions,

FIG. 2 is a schematic block diagram of a Viterbi processor in accordance with the present invention,

FIG. 3 is a block diagram showing the internal configuration of the add/accumulate block in FIG. 2,

FIG. 4 is a block diagram showing the internal configuration of one of the blocks for performing multiplication by .+-.2 in FIG. 2,

FIG. 5 is a diagram showing the memory locations of the branch metric store in FIG. 2,

FIG. 6 is a block diagram showing the internal configuration of the comparator/accumulator block in FIG. 2,

FIG. 7 is a schematic block diagram of a further embodiment of a Viterbi processor in accordance with the invention,

FIG. 8 is a block diagram showing in more detail the soft decision processor in FIG. 7,

FIG. 9 is a block diagram showing the processing of soft and hard decisions,

FIG. 10 is a block diagram of an encoder for generating convolutionally encoded data,

FIG. 11 is part of a 16-state trellis diagram for use at the decoder stage, and

FIG. 12 is a schematic block diagram of the Viterbi processor in FIG. 7 modified for operation as a decoder.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is part of a trellis diagram for the 16 states associated with a 2-symbol alphabet in the case where the constraint length is 4. The two symbols may, for example, be +1 and -1 mapped from the single bits 1 and 0 respectively. The partial trellis diagram shows the state transitions for all 16 states at a stage n and a subsequent stage n+1.

The states (0000, 0001 . . . 1110, 1111) are indicated in columns to the left and right of the respective nodes of the actual trellis diagram and the number of the state is shown in the column adjacent the state.

A transition between states occurs by shifting the current state at stage n one bit to the left, inserting the so-called transition bit in the position of the least significant bit and discarding the most significant bit (known as the survivor bit). The survivor bit is shown separately in the left hand (first) column in FIG. 1 and the transition bit is shown in the right hand (last) column.

As will be discussed in more detail below, the partial path metric for any particular state 0 to 15 at stage n+1 is given by combining the previous partial path metric at stage n and the branch metric between stages n and n+1. It can be seen that for each node at stage n+1 two possible state transitions may have occurred, that is to say there are two branch metrics. Hence there are two partial path metrics associated with each node, the larger of which is retained as the survivor path in accordance with the Viterbi algorithm. The survivor path is a unique path through the trellis which indicates the most likely sequence of state transitions terminating at any particular node. A 1 or a 0 is retained as a survivor bit depending on the most significant bit of the previous state in the survivor path. Hence consider the state number 1, i.e. 0001, at stage n+1. There are two possible states at the preceding stage n which could lead to state 0001 at stage n+1, namely state number 0 (0000) and state number 8 (1000). It can be seen from FIG. 1 that if the survivor path shows the last transition was from state 0 then the survivor bit is 0, whereas if the survivor path shows the last transition was from state 8 then the survivor bit is 1.

In general there are 2.sup.c+1 possible paths at each trellis transition, where C is the constraint length. In the present case where C=4 there are 2.sup.5 =32 paths through the trellis. That is to say that at any stage in the trellis there are 32 possible paths associated with the 16 states, i.e. 2 paths per state as can be seen from FIG. 1. Hence there are 32 path metrics to be calculated at each stage in the trellis. However, only 2.sup.c (in this case 16) paths are retained (survived) at each trellis stage.

The partial path metric is dependant not only on the previous partial path metric and the branch metric (as mentioned above), but also on the current observation or sample value of the received data symbol. The closer the observation is to the expected data symbol the more likely it is that the associated state transition actually occurred. Conversely the more the observed value departs from the expected data symbol the less certain it is that the associated state transition actually occurred. Using the equation derived by Gottfried Ungerboeck in his paper entitled "Adaptive Maximum-Likelihood Receiver for Carrier-Modulated Data-Transmission Systems" published in IEEE Transactions on Communications, Vol. COM-22, No. 5, May 1974, pages 624-636, and using the same nomenclature adopted therein, the partial path metric J.sub.n at stage n is defined by

where a.sub.n is the least significant bit of the current state (i.e. the transition bit, hence for the state transition 0000 to 0001 a.sub.n =1), obs is the external observation of the received data for the current trellis transition, J.sub.n-1 is the value of the previous partial path metric and F(.sigma..sub.n, .sigma..sub.n-1) is the branch metric where a refers to the state; .sigma..sub.n being the current state, and .sigma..sub.n-1 being the previous state.

The 2.sup.c+1 branch metrics are determined by the following formula: ##EQU1## where the s values are provided from estimates of the channel characteristics (i.e. the channel impulse response), and the ai values relate to the previous and current states. Hence a.sub.n is the new bit in the sequence (the transition bit) and a.sub.n-i (i=1 . . . C) are the bits of the previous state. Hence for the transition 0110 to 1101 a.sub.n =1, a.sub.n-1 =0, a.sub.n-2 =1, a.sub.n-3 =1, a.sub.n-4 =0.

The `a` values can be mapped from (0,1) to (-1,1). (If zero was used, all the `s` values multiplied by zero in equation (2) above would have the same weight, namely zero).

Hence the equation for the branch metrics, in the case of a 16 state trellis (i.e. C=4) becomes:

The branch metrics, according to this equation, remain constant throughout the trellis. They can therefore be calculated at the outset and stored, e.g. in a random access memory (RAM) for use throughout the calculations involved in the Viterbi algorithm.

Referring back to equation (1) it will be evident that there are 2.sup.c pairs of calculations involved in making each transition along the trellis. Also, there will be 2.sup.c new path metrics stored as the survivor paths after each trellis state calculation.

After completing each trellis transition there will be 2.sup.c new survivor bits, one for each state. The survivor bits are normally stored in memory for each transition, usually until completion of the sequence.

The survivor bit store will therefore be 2.sup.c bits wide and of length equal to the number of samples N.

The final stage of the Viterbi algorithm procedure is so-called "trace back". Trace back starts from the survivor bit which corresponds to the maximum final path metric. If the survivor bit is `a` and the state number is b then the next state number in the trace back is

This corresponds to shifting the current state one bit to the right, putting the survivor bit in the most significant bit position and discarding the least significant bit, which gives the maximum likelihood state at the previous stage in the trellis.

Thus, for example if the last state was 0110 (state number 6) and the survivor bit is 1, then the next state is 1011 (state number 11). If the survivor bit for state number 11 from the previous stage in the trellis was 0 then the next state will be 0101 (state number 5), and so on. Hence, it can be seen that a unique path representing the maximum likelihood bit sequence can be identified by the trace back. The maximum likelihood sequence are the bit values occurring at the trace back state positions in the survivor bit store, i.e. 10 . . . in the above example.

To summarize, the Viterbi algorithm comprises three main stages.

1. Calculate branch metrics.

2. Calculate path metrics through the trellis for all observation samples.

3. Perform trace back to establish maximum likelihood sequence.

An architectural arrangement for implementing the Viterbi algorithm will now be described with reference to FIG. 2. In this embodiment the Viterbi processor (detector) is employed for equalisation of a signal received over a dispersive communication channel.

In accordance with the present invention the Viterbi detector comprises a common adder/accumulator 1 into which, by time multiplexing, values from various sources can be applied on inputs 2, 3 for implementing the various equations of the Viterbi algorithm.

The internal configuration of the adder/accumulator 1 is shown in more detail in FIG. 3. The external input 2 is coupled directly to the input 6a of an arithmetic adder 5 and external input 3 is coupled to the input 6b of the adder via a multiplexer 7. The output of the adder is coupled directly to the external output 4 of the adder/accumulator 1 and is also fed back to the input 6b of the adder 5 via a latch 8 and the multiplexer 7. A control signal applied to the multiplexer 7 on control line 9 determines which input to the multiplexer is fed forward to the adder. In practice, the input from latch 8 will normally take precedence over the external input 3 unless or until an initialization signal is applied on the control line in which case the adder/accumulator 1 is effectively reset.

To illustrate the operation of the adder/accumulator 1 consider the summation of four terms A+B+C+D. At the outset an initialization signal is applied to multiplexer 7 on control line 9. The values A and B are applied respectively on inputs 2 and 3. The value A is applied directly to adder 5. By virtue of the initialization signal on control line 9 the multiplexer applies value B at input 6b of the adder 5. Hence the adder 5 sums A and B and the result is held in latch 8. The initialization signal on control line 9 is now removed so that the output of latch 8 can now be applied to the input 6b of the adder 5. At the next stage of the operation value C is applied at external input 2 and hence to the adder 5. By virtue of a clock signal applied to the latch 8 the value A+B stored therein is applied (via multiplexer 7) to the input 6b of the adder 5 in synchronization with the input value C. Hence adder 5 calculates (A+B)+C and stores the result in the latch 8 in place of the previous value (A+B). The value D is then applied at input 2 and this value is combined with the value (A+B+C) from the latch via the multiplexer 7 in the same manner as before. Hence the total summation (A+B+C)+D is calculated by the adder 5 and the result is available at the output 4. At this stage, the signal on the multiplexer control line is returned to the initialization value whereby the input 3 is coupled to the adder instead of the latch output so that the adder/accumulator is ready to perform the next calculation. (Note that it is immaterial what value is stored in the latch from the previous calculation since this will in effect be overwritten after the first add operation of the current calculation).

It is noted here that the switching of the various inputs to the adder/accumulator 1 is achieved by a plurality of respective CMOS transmission gates 10 to 15 each of which has a respective control line (depicted in the Figure by an incoming arrow). The impedance of the gates 10 to 15 is high when they are turned off. The control signals to the gates are applied, for example under the control of a finite state machine so that the various arithmetic operations inherent in the Viterbi algorithm calculations are performed in the appropriate sequence. Finite state machines are themselves well known in the art and so no further details need be given here except to note that when the finite state machine is in each state, a counter sequences each of the calculations. The counter also ensures that the relevant memory locations are addressed at the appropriate time. When the counter reaches a predetermined value the state machine moves to the next state and clears the counter. The state sequencing and associated number of clock cycles is discussed in more detail below.

The Viterbi detector in FIG. 1 will now be described in relation to tho three main stages of the Viterbi algorithm mentioned above,

1. Branch Metric Calculation

This section implements equation (3) above viz.

when F(.sigma..sub.n, .sigma..sub.n-1) is the branch metric.

The values s.sub.o, s.sub.1 . . . s.sub.4 are determined from estimates of the channel characteristics in known manner. The value s.sub.o is stored in a latch 16 (or other memory device) and the values s.sub.1, to s.sub.4 are stored in a random access memory (RAM) 17 labelled S RAM in FIG. 2. Addressing of S RAM 17 is effected under the control of the finite state machine counter. Latch 16 is coupled directly to the initialization input 3 of the adder/accumulator 1 via gate 13, and S RAM 17 is coupled to the input 2 through gate 10 via a multiplication stage 18 labelled S MULT in FIG. 2. S MULT 18 is shown in more detail in FIG. 4. The multiplication of the s.sub.1 to s.sub.4 values by two is effected simply by shifting the s value left by one position and adding a 0 at the least significant bit position. This is effected at stage 19. S MULT 18 also includes a multiplexer 20 under the control of a signal applied from the finite state machine to select the positive or negative value of s.sub.1 . . . s.sub.4 depending on the particular calculation being performed.

It is noted here that two's complement arithmetic is used at this stage and throughout the present embodiment. As is very well known, two's complement is a method of forming the binary equivalent of a negative number. The (positive) number value is written in binary, each digit is then inverted (i.e. 0 becomes 1 and vice versa) and a 1 is added in the least significant position. Two's complement arithmetic enables a subtraction operation to be achieved by adding the two's complement of the number to be subtracted. Hence in the present embodiment two's complement arithmetic enables the adder 5 to be used for effecting all the branch metric calculations including those where terms have to be subtracted. To this end S MULT 18 includes an inverter 21 for inverting the s values. The additional binary 1 is simply added by the adder 5 as a "carry in" to the least significant bit.

If the add/accumulate circuit is initialized to s.sub.o as described here (i.e. s.sub.o is applied to the initialization input 3) then there are four distinct add/accumulate operations (and hence four clock cycles) needed to perform each branch metric calculation. Hence a 6-bit counter can be used to sequence the branch metric operation, the four most significant bits determine which of the sixteen metrics is being calculated and the two least significant bits sequence the four additions required for each metric.

It is noted, however, that in an alternative embodiment all of the s values including s.sub.o may be stored in S RAM 17 and applied to the input 2 of adder 5. In this case a standard initialization value of 0 may be applied on initialization input 3. In this case, however, there will be five distinct add/accumulate operations (and hence five clock cycles) needed to perform each branch metric calculation.

In theory there are 32 branch metrics in the case of a 16 state trellis as explained above, but only sixteen need to be calculated because in equation (2) the term a.sub.n.sup.2 is positive whether a.sub.n is +1 or -1. The full set of thirty-two branch metrics is therefore reflected about its mid point. The branch metrics calculated by the adder/accumulator 1 are stored in a RAM 23 labelled BRANCH METRIC STORE in FIG. 2. The structure of the BRANCH METRIC STORE in 23 is shown in more detail in FIG. 5, with branch metric F.sub.o stored in locations 0 and 31, and the branch metric F.sub.1, stored in locations 1 and 30 and so on, the branch metric F.sub.15 being stored in locations 15 and 16. It will be evident to a person skilled in the art that due to the symmetrical distribution of branch metrics about the mid-point a RAM having only sixteen memory locations may be used instead to store the branch metrics with appropriate addressing i.e. with F.sub.o stored in location 0 only, F.sub.1 stored in location 1, and so on. Addressing of the BRANCH METRIC STORE is determined by the finite state machine.

2. Path Metric calculation

This section implements equations (1) above, viz

where, as before, a.sub.n .+-.1, obs is the external observation of the received data for the current trellis transition, J.sub.n-1 is previous path metric, and F(.sigma..sub.n, .sigma..sub.n-1) is the branch metric.

The observed values obs are stored in a RAM 24 labelled OBSN RAM in FIG. 2. Addressing of OBSN RAM 24 is effected under the control of the finite state machine. OBSN RAM 24 is coupled to the input 2 of the common adder/accumulator 1 through gate 12 via a multiplication stage 25 labelled OBS MULT in FIG. 2. The internal configuration of OBS MULT 25 is equivalent to S MULT 18 shown in FIG. 4. OBS MULT 25 thus effects the operation .+-.2.obs.

The BRANCH METRIC STORE 23 is also coupled to the input 2 of the adder/accumulator 1 but through a different gate 11.

The previous partial path metrics are stored in a RAM 28 labelled VA STATE STORE in FIG. 1. Sixteen partial path metrics are stored in the VA STATE STORE 28, one for each node of the trellis at the previous stage n-1, at locations representative of the state number. Hence the partial path metric for state 0 is stored at location 0, the partial path metric for state 1 at location 1 and so on. Addressing of the VA STATE STORE is effected under the control of the finite state machine.

VA STATE STORE 28 is coupled to the input 3 of the adder/accumulator 1 through gate 15. Thus, the adder/accumulate circuit is initialized to J.sub.n-1. Hence, there are two add/accumulate operations (and hence two clock cycles) for each possible state transition involving respectively the terms F(.sigma..sub.n,.sigma..sub.n-1) and 2.a.sub.n.obs.

As explained in detail above there are two partial path metrics for each node of the trellis, associated respectively with a 1 or 0 survivor bit. For example, consider the partial path metrics for the state 0010. The partial path metric J.sub.n.sup.0 in respect of a 0 survivor bit is given by

and the, partial path metric J.sub.n.sup.1 in respect of a 1 survivor bit is given by

The first partial path metric J.sub.n.sup.0 is calculated in the adder/accumulator 1 and the result stored in latch 26. Subsequently the second partial path metric J.sub.n.sup.1 is calculated in the same adder/accumulator 1. The two partial path metrics are compared by a subtractor 27 and the result of the subtraction operation controls a multiplexer 29 whereby the larger of the two partial path metrics is selected for input to the VA STATE STORE 28. Since it is only the sign of the subtraction operation that is required, i.e. to indicate which of the two partial path metrics is the larger, the subtractor may output a single bit. Specifically, a 1 output may indicate that the larger partial path metric is that corresponding to a 1 survivor bit (J.sub.n.sup.1) whereas a 0 output would indicate that the larger partial path metric is that corresponding to a 0 survivor bit (J.sub.n.sup.0). It will be noted that in this case the output of subtractor 27 directly constitutes the survivor bit and will be used in this capacity as discussed further below. The larger partial path metric is written into the VA STATE STORE 28 at the appropriate location overwriting the previous partial path metric already written at that location, using a cyclic addressing pattern e.g. as proposed in the paper entitled "In-place Updating in Viterbi Decoders" by M. Biver, H. Kaeslin and C. Tommansini published in IEEE Journal of Solid Stage Circuits Volume 24, No. 4, August 1989, pages 1158-60.

An alternative implementation of the VA STATE STORE 28 may involve a ping-pong arrangement of two RAMs, one of which is written with J.sub.n values, the other being the source of J.sub.n-1 values. When a full trellis transition has been completed at stage n, the function of the two RAMS is interchanged for the trellis calculations at stage n+1 so that the existing J.sub.n values become the new J.sub.n-1 values and a new set of J.sub.n values is calculated and stored in the RAM previously containing the J.sub.n-1 values.

In summary, therefore, it will be seen that two adder/accumulator operations (two clock cycles) are needed to calculate each partial path metric, hence four operations (clock cycles) for each state. Sixty four cycles are therefore required to calculate all sixteen partial path metrics.

Control of the partial path calculations is achieved using the finite stage machine counter. The two least significant bits sequence the four additions required for the calculation of each new partial path metric. The next four bits determine which of the sixteen path metrics is being calculated. The remaining (most significant) bits determine which trellis transition is being calculated, and hence which observation value to use. The number of bits in this counter will therefore depend on the number of observations.

For the very first trellis transition, instead of a true previous partial path metric, a trellis initialization signal I is driven onto the input 3 of adder/accumulator 1. This value may be forced to zero for all metric calculations. Alternatively, if the preceding bit sequence is known, I can be initialized to some arbitrary positive value for the known state.

As each partial path metric is calculated a corresponding survivor bit has to be stored for use during the subsequent trace backsphase. As explained above in the theory of the Viterbi algorithm, the survivor bit is the most significant bit of the state at stage n (and represents the transition bit four transitions earlier, i.e. at stage n-4). As has been explained above the output of the subtractor 7 constitutes the survivor bit. Thus, as each of the partial path metrics is calculated in turn, the survivor bit output from subtractor 27 is input into a 16 bit shift register 30, i.e. one survivor bit for each state. Thus when the first partial path metric is calculated for the state 0 the first survivor bit is fed into the most significant bit position in the shift register 30. When the second partial path metric is calculated for state 1 the first survivor bit is shifted to the right and the second survivor bit is input into the most significant bit position, and so on. When the sixteenth partial path metric is calculated the sixteenth survivor bit is input into the most significant bit position at which point the first survivor bit is shifted into the least significant bit position. Hence the position of the survivor bit corresponds directly to the state number. After all sixteen survivor inputs have been input to the shift register 30 the data is transferred as a 16-bit word into a random access memory 81 designated as SURVIVOR STORE in FIG. 1. This process is repeated at each of the N stages of the trellis (where N is the number of external observations of the received data signal) so that at the end of the trellis calculations there will be N 16-bit words stored in the SURVIVOR STORE 81 their respective locations corresponding to the chronological occurrence in the sampling sequence.

3. Trace Back

The theory of the trace back operation has already been described above. In the present embodiment a comparator/accumulator 31 is included to select the largest partial path metric at the final stage of the trellis. The internal arrangement of the comparator/accumulator 31 is shown in FIG. 6. The comparator/accumulator 31 thus compares each of the sixteen partial path metrics on input 34 and stores the metric in latch 36 only if it is larger than the previously held value. The comparison is performed by a subtractor 37 the output of which controls a multiplexer 38. This circuit also stores in latch 39 the actual state corresponding to the currently stored partial path metric. The state values are applied on input 35 of a multiplexer 40 which, also under the control of the output signal from subtractor 37 selects whether to retain the current state stored in the latch or to update it with the new state depending respectively on whether the new partial path metric is smaller than or exceeds the current value in latch 36. At the end of all the partial path metric comparisons the comparator/accumulator 31 has stored in latch 36 the maximum partial path metric and in latch 39 the associated state. The maximum state (comprising four bits) is then transferred from latch 39 into a shift register 32 labelled as STATE REG in FIG. 2. The state thus stored in STATE REG 32 is the initial state for the trace back. STATE REG 32 controls the operation of multiplexer 33 coupled to the output of SURVIVOR STORE 81, and determines the location of the initial survivor bit which is output from the multiplexer 33. The survivor bit is also fed back to the most significant bit position of STATE REG 32 and shifted one position to the right each time a new survivor bit is added, the bit in the least significant position being discarded each time. Thus the new value in STATE REG 32 indicates the location (=state number) of the survivor bit to be recovered from the next 16-bit word stored in the SURVIVOR STORE 81. Again this survivor bit is output from multiplexer 33 and also fed back to the most significant bit position in STATE REG 32 to determine the position of the survivor bit to be recovered from the next 16-bit word in the SURVIVOR STORE 81.

The process is repeated until the survivor bits have been recovered from all N 16-bit words stored in SURVIVOR STORE 81. The resulting bit stream output from the SURVIVOR STORE 81 is the maximum likelihood sequence of transmitted bits (in reverse order).

The operation of the trace back stage will be more clearly understood in the light of an example. Assume therefore that at the final transition, i.e. stage N, the comparator/accumulator 31 calculates that state number 4 (0100) has the maximum partial path metric. The state 0100 will be stored in STATE REG 32. This will cause the fourth bit (from the least significant bit position) of the last word in the SURVIVOR STORE 81 to be output from the multiplexer 33 as the first survivor bit. Assume this bit is a 1. This survivor bit is also fed back to the most significant bit of the STATE REG 32. Hence the new state stored in the STATE REG will become 1010 (i.e. state number 10). This will cause the tenth bit (from the least significant bit position) of the penultimate word in the STATE STORE 81 to be output from the multiplexer 33. Assume this bit is a 0. The new STATE REG value will become 0101 (state number 5) causing the fifth bit of the third from last word to be output from the multiplexer 33 and so on. Hence the resulting bitstream (the maximum likelihood bit sequence) in this case will be 10 . . .

To conclude this description of a first embodiment of the invention, it is useful to recap on the state sequence of the finite state machine, and to consider the timing aspect. When the finite state machine is in each state a counter sequences the calculations. When the counter reaches a predetermined value the state machine moves to the next state and clears the counter. The following table shows the various states and the associated clock cycles.

______________________________________ FSM STATE Counter Explanation ______________________________________ 1. Reset 0 2. Branch Metric 0 .fwdarw. 63 (16 branch metrics; Calculation each take 4 cycles to compute). 3. Path Metric 0 .fwdarw. (64 .times. N) (Number of observations Calculation .times. 64 cycles per observation). 4. Trace Back 0 .fwdarw. N (Trace back through N trellis transitions). ______________________________________

It can be seen, therefore, that the total number of clock cycles for a complete Viterbi algorithm calculation is

for example if there are 116 observations, the total number of clock cycles will be 7604. Thus, at 10 MHz the present detector would be able to complete all the computations involved in 0.76 ms.

As presented thus far the partial path metrics will grow without bound as transitions proceed across the trellis. This arrangement will be adequate if sufficient precision exists. However, if the metrics become too large a nomalization circuit may readily be included. The comparator/accumulator 31 may be adapted to determine the maximum of the sixteen partial path metrics at each stage of the trellis. This value may be subtracted as a constant offset fro