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We claim:
1. A method of manufacturing a semiconductor integrated circuit device having (1) memory cells each comprising a first MISFET and a capacitor element connected in series and (2) a
peripheral circuit comprising second MISFETs, comprising the steps of:
providing a semiconductor substrate having a main surface of first conductivity type, said main surface including a first area for forming one of said memory cells and a second area for forming one of said second MISFETs;
forming a first conductive strip, having two sides, both said two sides overlying said first area, as a gate electrode for said first MISFET, and forming a second conductive strip, having two sides, both said two sides overlying said second area
as a gate electrode for a second MISFET;
introducing first impurities of second conductivity type, which is opposite to said first conductivity type, into said semiconductor substrate in said first and second areas, in a self-aligned manner with said first and second conductive strips,
thereby to form first semiconductor regions as source and drain regions for said first MISFET in said first area and second semiconductor regions in said second area as source and drain regions for said second MISFET;
selectively forming sidewall spacers on both sides of each of said first and second conductive strips;
forming a first insulating film over said first and second conductive strips in said first and second areas, said first insulating film having a via exposing said sidewall spacers on sides of said first conductive strips and exposing a surface
portion of said semiconductor substrate into which said first impurities have been introduced in said first area;
forming a first polycrystalline silicon strip in said via so that said first polycrystalline silicon strip contacts said surface portion in said first area;
forming a dielectric film over said first polycrystalline silicon strip and forming a third conductive strip over said dielectric film; and
introducing second impurities of second conductivity type into said semiconductor substrate in said second area in a self-aligned manner with said sidewall spacers, on both sides of said second conductive strip, without introducing said second
impurities in said first area, thereby to form third semiconductor regions as source and drain regions of said second MISFET, wherein said step of introducing second impurities is performed using second impurities having higher impurity concentration
than said first impurities so as to form said third semiconductor regions having a higher impurity concentration than that of said first semiconductor regions.
2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of forming a mask layer covering said first area and exposing said second area, prior to said introducing second impurities,
said mask layer acting as a mask when introducing the second impurities.
3. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said step of forming sidewall spacers comprises the substeps of:
forming an insulating film over said first and second conductive strips; and
etching said insulating film by using reactive ion etching.
4. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of forming a fourth conductive strip in said first area, said fourth conductive strip being connected to another of said
source and drain regions of said first MISFET.
5. A method of manufacturing a semiconductor integrated circuit device according to claim 4, further comprising a step of forming fifth conductive strips in said second area, said fifth conductive strips being connected to said source and drain
regions of said second MISFET.
6. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first polycrystalline silicon film is formed in a self-aligned manner in contact with said surface portion exposed in said via.
7. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the step of introducing third impurities of the second conductivity type in said surface portion so as to form a fourth semiconductor
region in one of said first semiconductor regions, the fourth semiconductor region having a higher impurity concentration than said one of the first semiconductor regions.
8. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said third impurities are introduced in said surface portion by diffusion from the first polycrystalline silicon strip, the third impurities
having been included in the first polycrystalline silicon strip.
9. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the impurity concentration of the fourth semiconductor region is less than an impurity concentration of the third semiconductor regions.
10. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein a depth of the fourth semiconductor region from the main surface of the semiconductor substrate is less than that of the first semiconductor
regions.
11. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first polycrystalline silicon strip is a conductive strip having said third impurities therein.
12. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first polycrystalline silicon strip contacts with one of the first semiconductor regions, and wherein the method includes the further step
of forming a conductive line connected with another of the first semiconductor regions, the further step of forming the conductive line including substeps of:
forming a fifth semiconductor region in said another of the first semiconductor regions, the fifth semiconductor region being of a same conductivity type as that of the first semiconductor regions and of a higher impurity concentration than that
of the first semiconductor regions; and
forming the conductive line so as to contact the fifth semiconductor region.
13. A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the fifth semiconductor region is formed by introducing impurities into said another of the first semiconductor regions via a contact hole
exposing said another of the first semiconductor regions, and wherein the conductive line is formed so as to extend into said contact hole.
14. A method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the impurities are introduced into said another of the first semiconductor regions, to form the fifth semiconductor region, by ion
implantation.
15. A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein, prior to forming the conductive line, an inter-layer insulating film is selectively removed so as to expose the semiconductor substrate at
the fifth semiconductor region, the inter-layer insulating film being selectively removed using the third conductive strip as a mask.
16. A process for forming a first MISFET and second MISFETs of a semiconductor integrated circuit device having (1) memory cells each comprising the first MISFET and a capacitor element connected in series and (2) a peripheral circuit comprising
the second MISFETs, comprising the steps of:
providing a semiconductor substrate having a main surface of a first conductivity type, said main surface including a first area for forming one of said memory cells and a second area for forming a second MISFET of said second MISFETs;
forming a first conductive strip, having two sides, both said two sides overlying said first area, as a gate electrode for said first MISFET, and forming a second conductive strip, having two sides, both said two sides of said second conductive
strip overlying said second area, as a gate electrode for said second MISFET;
introducing first impurities of a second conductivity type, which is opposite to said first conductivity type, into said semiconductor substrate in said first and second areas, in a self-aligned manner with said first and second conductive
strips, thereby to form first semiconductor regions as source and drain regions for said first MISFET in said first area, and second semiconductor regions in said second area;
selectively forming sidewall spacers on both sides of each of said first and second conductive strips;
forming a first insulating film over said first and second conductive strips in said first and second areas, said first insulating film having a via exposing said sidewall spacers formed on said first conductive strip and exposing a surface
portion of said semiconductor substrate into which said first impurities have been introduced in said first area;
forming a first polycrystalline silicon strip in said via so that said first polycrystalline silicon strip contacts with said surface portion in said first area;
forming a mask layer which covers said first area and exposes said second area; and
introducing second impurities of the second conductivity type into said semiconductor substrate in said second area in self-aligned manner with said sidewall spacers, on both sides of said second conductive strip, by using said mask layer as a
mask, thereby to form third semiconductor regions as source and drain regions of said second MISFET,
wherein said step of introducing second impurities is performed using second impurities having higher impurity concentration than said first impurities, such that the third semiconductor regions have a higher impurity concentration than that of
said first semiconductor regions.
17. A process according to claim 16, further comprising the step of introducing third impurities of the second conductivity type in said surface portion so as to form a fourth semiconductor region in one of said first semiconductor regions, the
fourth semiconductor region having a higher impurity concentration than said one of the first semiconductor regions.
18. A process according to claim 17, wherein said third impurities are introduced in said surface portion by diffusion from the first polycrystalline silicon strip, the third impurities having been included in the first polycrystalline silicon
strip.
19. A process according to claim 18, wherein said first polycrystalline silicon strip is connected to said capacitor element.
20. A process according to claim 17, wherein the impurity concentration of the fourth semiconductor region is less than an impurity concentration of the third semiconductor regions.
21. A process according to claim 17, wherein a depth of the fourth semiconductor region from the main surface of the semiconductor substrate is less than that of the first semiconductor regions.
22. A process according to claim 16, wherein the first polycrystalline silicon strip contacts with one of the first semiconductor regions, and wherein the method includes the further step of forming a conductive line connected with another of
the first semiconductor regions, the further step of forming the conductive line including substeps of:
forming a fifth semiconductor region in said another of the first semiconductor regions, the fifth semiconductor region being of a same conductivity type as that of the first semiconductor regions and of a higher impurity concentration than that
of the first semiconductor regions; and
forming the conductive line so as to contact the fifth semiconductor region.
23. A process according to claim 22, wherein the fifth semiconductor region is formed by introducing impurities into said another of the first semiconductor regions via a contact hole exposing said another of the first semiconductor regions, and
wherein the conductive line is formed so as to extend into said contact hole. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, particularly a semiconductor integrated circuit memory device, and more particularly to structure which is effective when applied to a semiconductor integrated circuit
device having dynamic random access memories (DRAMs), and methods for the production thereof. The present invention is further directed to a semiconductor integrated circuit device having a capacitor element, particularly a semiconductor integrated
circuit memory device, such as a DRAM, having a stacked capacitor element, and methods of production thereof.
The present invention is further directed to wiring techniques having applicability in connection with various devices, including in connection with semiconductor integrated circuit devices, particularly semiconductor integrated circuit memory
devices such as DRAMs.
Each of the memory cells constituting a DRAM includes a memory cell selecting MISFET and a capacitor element for storing information, such capacitor element being connected in series to one semiconductor region of the MISFET. The gate electrode
of the memory cell selecting MISFET is connected to a word line which extends in the row direction so that the MISFET is controlled through this word line. The other semiconductor region of the memory cell selecting MISFET is connected to a data line
which extends in the column direction.
Attempts are continuously being made, with respect to this type of DRAM, to increase its integration density, for the purpose of increasing the memory capacity, and therefore there is a tendency for the memory cell sizes to shrink. When the
memory cell sizes are reduced, the size (area) of the capacitor elements, for storing the information, is also reduced which results in a decrease in the capacity of such capacitor elements for storing charges which constitute information. As the charge
storing capacity decreases, the effect of minority carriers generated due to .alpha.-particles increases, so that so-called soft errors are likely to occur. This occurrence of soft errors is particularly a problem in DRAMs having high integration
density, such as 1 Mbit or more.
In view of this problem of soft errors generated due to .alpha.-particles, stacked capacitor elements (STCs) have been adopted as information storage capacitor elements of the memory cells of DRAMs. A stacked capacitor element includes a first
electrode layer, a dielectric film and a second electrode layer, which are successively stacked on a semiconductor substrate. The first electrode layer is formed in such a manner that, after memory cell selecting MISFETs of the memory cells have been
formed, when part of the first electrode layer of the stacked capacitor elements is connected to one semiconductor region of the corresponding MISFET, another part thereof is extended above the gate electrode of the corresponding memory cell selecting
MISFET. The first electrode layer is formed from a polycrystalline silicon film having an impurity (such as P or As, for example) introduced therein, for the purpose of lowering the resistance value of the polycrystalline silicon. The dielectric film
is defined by a silicon oxide film formed by oxidizing the surface of the polycrystalline silicon film constituting the first electrode layer, The second electrode layer is formed integrally with the second electrode layers of other adjacent memory
cells, thus providing a common plate electrode (as the second electrode layer). The second electrode layer is formed from a polycrystalline silicon film like that of the first electrode layer.
The aforementioned memory cell selecting MISFET of the memory cell is constructed into an n-channel type. This MISFET has its shape specified by the element insulating isolating film and a p-type channel stopper region, and is electrically
isolated from the elements of other regions.
There is connected a data line with the other semiconductor region of the memory cell selecting MISFET of each memory cell in the array, such data line being connected to such other semiconductor region through an intermediate conducting layer
which is formed in the same fabrication step as the first electrode layer of the storage capacitor element. Since this intermediate conducting layer is connected in self-alignment with the other semiconductor region, the data line is connected in
self-alignment with the other semiconductor region even if a masking-displacement is caused at the fabrication steps of the intermediate conducting layer and the data line.
Information stored in each memory cell of the DRAM is input through the above-described data line to a sense amplifier of a peripheral circuit, where it is amplified, and the amplified information is then output to a common data line through a
Y-switch. The Y-switch is controlled by a column decoder circuit (Y-decoder circuit) through a Y-select signal line. The Y-select signal line is formed from the same conductive layer as that for the above-described data line and extends in the same
column direction as the data line.
The memory cell comprising the above-described stacked capacitor elements has the advantage that incidence of soft errors can be reduced because such capacitor elements do not use the semiconductor substrate in which minority carriers are
generated due to .alpha.-particles incident thereon. In addition, the stacked capacitor element enables areas of the first and second electrode layers to be increased in the heightwise direction (direction extending perpendicular to the semiconductor
substrate) by making use of the stepped configuration of the memory cell selecting MISFET. Due to such increased size, an increase in the capacity of storing charge which constitutes information is achieved, so that it is further possible to reduce soft
errors.
The data lines of the DRAMs, mentioned previously, consist of an aluminum wiring having a small specific resistivity. An element for reducing electromigration and stress migration is added to the aluminum wiring forming the data line. For
example, copper (Cu) is generally used as such element for reducing electromigration and stress migration; however, palladium (Pd) or titanium (Ti) can also be used as such element. In addition, silicon or the like has also been added to the aluminum
wiring, in addition to the element(s) discussed above, in order to prevent an aluminum spike. Thus, a common wiring for the data line is an aluminum-copper-silicon wiring.
The aluminum wiring technique of a DRAM is described, for example, in "Nikkei Micro-Devices", May Issue, 1987, pgs. 16-31, Special Issue No. 1, published by Nikkei-McGraw-Hill Co.
It should also be noted that a DRAM in which each memory cell includes a stacked capacitor element is described, for example, in Japanese Patent Laid-Open No. 183952/1986. The contents of this Japanese patent laid-open application are
incorporated in their entirety herein.
SUMMARY OF THE INVENTION
Problems Found and Addressed by the Inventors
In attempting to develop a DRAM having increased capacity, the present inventors have found various problems in the above-described prior art structure, and in the methods of forming such structure.
A. In connection with a first aspect of the present invention, the inventors have found that when the information storage capacitor of the stacked structure is formed after the memory cell selecting MISFET has been formed, the source and drain
region of the MISFET being formed by ion implantation at a relative high implantation flux of or above 10.sup.15 atoms/cm.sup.2 (providing a high impurity concentration region of or above 10.sup.20 atoms/cm.sup.3), crystal defects are often caused in the
principal surface portion of the semiconductor substrate (for example, a well region formed in the substrate) due to such ion implantation. Such crystal defects cannot be satisfactorily removed by annealing at a later step in the manufacturing process.
Due to such defects, charges stored in the stacked capacitor element leak to the substrate, so that the information retention characteristics of the DRAM degrade. Such degradation of the information retention characteristics results in the requirement
that the frequency of refreshing the information increases, so that the operating speed of the DRAM decreases.
B. In connection with a second aspect of the present invention, the present inventors have found that, where each of the memory cells is disposed under the above-described data line, and if the aforementioned Y-select signal line is provided
using the same conductive layer as that for the data line, the region where this Y-select signal line is provided becomes a useless space. This useless space hinders a decrease in the memory cell area, and results in a failure to further increase the
integration density of the DRAM.
C. In connection with a third aspect of the present invention, as the integration density increases, and in order to protect against minority carriers below the memory cell forming region, it becomes desirable to form a potential barrier layer
below the memory cell forming region. This potential barrier layer can be formed, for example, by introducing a P-type impurity at a high dosage into the memory cell forming region by ion implantation. This P-type impurity can be introduced at various
stages during the manufacturing process. Thus, this P-type impurity can be introduced into the entire surface of the memory cell array, including locations for the memory cell, before the element isolating insulating film and the channel stopper region
are formed. In addition, this introduction of the P-type impurity can be accomplished by using the element isolating insulating film as an impurity introducing mask, after the element isolating insulating film and the channel stopper region are formed.
The introduction of the P-type impurity for forming the potential barrier layer increases the impurity concentration of the aforementioned channel stopper region in the peripheral region of the memory cell. This increase in turn drops the PN
junction breakdown strength between one semiconductor region (forming part of the information storing capacitor element, that is, a storage node) of the MISFET of a memory cell and the channel stopper region. This drop in the junction breakdown strength
causes the electric charges stored in the stacked capacitor element to leak, thereby degrading its information holding characteristics, so that the frequency of refreshing such information is increased. As a result, the reading and writing rates of the
DRAM increases, thus decreasing the speed of the DRAM. Moreover, such DRAM, having such potential barrier layer, requires an increased number of fabrication steps, due to the addition of the step of forming the aforementioned potential barrier layer.
As a technique for solving the problems specified above, in connection with this third aspect of the present invention, it is possible to form both the channel stopper region and the potential barrier layer in the same processing step, with the
channel stopper region being formed by introducing a P-type impurity through the element isolating insulating film by ion implantation using a high energy. If, however, the impurity is introduced with a high energy, a number of crystal defects is caused
in the substrate surface at the memory cell forming region, thereby degrading the information holding characteristics of the DRAM.
D. In connection with a fourth aspect of the present invention, the inventors have found the following problems arising upon increasing the integration density of the DRAM. Thus, the memory cell is required to have an isolating space between the
first electrode layer of the stacked capacitor element and an intermediate conducting layer which connects a data line to a semiconductor region of the memory cell selecting MISFET. Such isolating space causes a decrease in the area of the first
electrode layer of the stacked capacitor element, and accordingly decreases the amount of storage of electrical charges which can be achieved in the stacked capacitor element. Moreover, when the second electrode layer of the stacked capacitor element is
to be patterned, the intermediate conducting layer uses a dielectric film formed thereover as an etching stopper; however, since this dielectric film is very thin, the intermediate conducting layer can be damaged or broken as a result of over-etching in
patterning the second electrode layer. This causes a poor connection between the data line and the other semiconductor region of the MISFET.
In order to prevent this, it is conceivable not to sandwich an intermediate conducting layer between the other semiconductor region and the data line. The omission of the intermediate conducting layer can extend the first electrode layer to the
data line, so as to increase the area of the same, so that the amount of storage of the electric charges of the stacked capacitor element can be increased. However, since the other semiconductor region has its principal surface substantially exposed to
the outside, when the intermediate conducting layer is omitted, its principal surface is damaged by the etching upon patterning the first and second electrode layers of the stacked capacitor element.
In order to solve this problem, an inter-layer insulating film can be formed as an etching stopper layer all over the surface of the substrate after the MISFET is formed and before forming the first electrode layer; such inter-layer insulating
film can be made of a silicon oxide film which is prepared by a deposition technique, such as chemical vapor deposition (CVD). The first electrode layer is then formed over the inter-layer insulating film, and the connection between the one
semiconductor region of the memory cell selecting MISFET and the first electrode layer of stacked capacitor element can be accomplished through a connection hole which is formed in the aforementioned inter-layer insulating film. However, the inter-layer
insulating film over the other semiconductor region of the memory cell selecting MISFET has to be removed before the data line is connected, so that there arises the problem that the number of manufacturing steps for forming the semiconductor device
disadvantageously increases. Furthermore, since the removal of the inter-layer insulating film requires a mask alignment margin, there arises a further problem, in connection with use of the inter-layer insulating film, that the memory cell area is
disadvantageously increased, so as to decrease the degree of integration of the device.
On the other hand, where the dielectric film of the stacked capacitor element is used as an etching stopper when the second electrode layer is patterned, and when patterning of the second electrode layer is accomplished by plasma etching, for
example, the further problem arises that the dielectric film left uncovered by the second electrode layer is charged up with electric charges during patterning of the second electrode layer, so that its dielectric breakdown strength decreases; this
deteriorates the reliability of the DRAM. Accordingly, according to this fourth aspect of the present invention, it is desired to provide a technique wherein the integration density of the DRAM can be increased without deteriorating the reliability of
the DRAM, while still satisfactorily providing the stacked capacitor element and data line connection to the other semiconductor region of the memory cell selecting MISFET.
E. In connection with a fifth aspect of the present invention, the present inventors have found that the dielectric film of the stacked capacitor element of each of the memory cells, defined by a silicon oxide film formed by oxidizing the surface
of a polycrystalline silicon film which defines the first electrode layer, has a lower dielectric strength and a larger number of defects per unit area than those of a silicon oxide film formed by oxidizing the surface of a single crystal silicon
substrate. Due to such lower dielectric strength and larger number of defects, the stacked capacitor element has a relatively large leakage current, and therefore suffers from deterioration of information holding characteristics. While it has been
considered to adopt a single-layer silicon nitride film, deposited by CVD, as the dielectric film of the stacked capacitor element, such single-layer silicon nitride film has a relatively large leakage current, and therefore the information holding
characteristics of the capacitor element having such nitride film as the dielectric layer is deteriorated. Accordingly, there is still a need, according to this fifth aspect of the present invention, to provide a dielectric film of the stacked capacitor
element whereby the stacked capacitor element has a relatively small leakage current.
F. In connection with a sixth aspect of the present invention, the inventors have discovered that, in connection with aluminum wiring (such as the data line) used in, e.g., a DRAM, shape defect and disconnection occur frequently due to
electrolytic corrosion. As a result of analysis of the aluminum wiring, the inventors believe that such electrolytic corrosion occurs during a wet treatment after forming such wiring. Specifically, the aluminum wiring to which the element for reducing
migration is added is formed by anisotropic etching, such as reactive ion etching (RIE) using a photoresist film as an etching mask. After this anisotropic etching step, the aluminum wiring is subjected to water washing and a cleaning treatment, and to
a wet treatment, using a liquid, to remove the photoresist film utilized as an etching mask during the anisotropic etching. During this wet treatment, a battery (galvanic) reaction occurs with the base (aluminum) of the aluminum wiring serving as an
anode and an intermetallic compound formed by aluminum and the element for reducing electromigration added to the wiring, as described above, serving as a cathode. This galvanic reaction corrodes the base of the wiring around the intermetallic compound
as a nucleus, with shape defects or disconnection of the aluminum wiring resulting from this galvanic reaction; such result lowers the electrical reliability of the wiring used in the DRAM.
In order to improve electrical reliability of the aluminum wiring resulting from the galvanic reaction described above, the inventors of the present invention dispose a protective film on the aluminum wiring to protect it from the liquid used in
the wet treatment. A refractory metal film or a refractory metal silicide film having resistance to wet treatment, and high reliability in a semiconductor fabrication process, is used as the protective film. This protective film is formed by first
depositing an aluminum film by sputtering, by use of a sputtering apparatus, and then depositing the protective film by use of another sputtering apparatus, or a CVD apparatus. However, the inventors have found that an aluminum oxide film is
instantaneously formed on the aluminum film, while the formed structure is transferred between, for example, the sputtering apparatus for depositing the aluminum film and another sputtering apparatus, or a CVD apparatus, for forming the protective film.
This aluminum oxide functions as an etching stopper when the aluminum film is patterned and results in the problem that the aluminum film cannot be etched. Thus, according to this sixth aspect of the present invention, there is a desire to provide a
structure of aluminum film and protective film, without such aluminum oxide film.
G. In connection with a seventh aspect of the present invention, and in order to provide DRAMs having large integration density, applicants have found that when MoSi.sub.2 is utilized as the protective film for protecting the aluminum wiring from
a liquid used for wet treatment to remove the photoresist mask utilized for anisotropic etching to form the wiring, with an upper layer aluminum wiring being provided on the MoSi.sub.2 (for example, such MoSi.sub.2 being provided in a through-hole in an
inter-layer insulating film to provide electrical conductivity between upper and lower aluminum wiring layers), the contact resistance value increases abnormally at the interface portion between the MoSi.sub.2 and the upper aluminum wiring. As a result
of analysis, the inventors have found that aluminum particles of the lower layer aluminum wiring precipitate at the interface through MoSi.sub.2 and an aluminum oxide is formed at the interface. The increase in contact resistance value between the lower
and upper layer aluminum wirings reduce the yield of the through-holes.
Solutions to the Foregoing Problems
A. Accordingly, it is an object of the first aspect of the present invention to provide, in a semiconductor integrated circuit device (e.g., a DRAM), wherein a memory cell is constructed utilizing a capacitor element (e.g., a stacked capacitor
element) formed on a substrate, a technique capable of enhancing information retention characteristics of the device.
It is a further object of this first aspect of the present invention to provide a technique of capable of accomplishing the aforementioned object, thereby to raise the operating speed of the DRAM.
It is a still further object of this first aspect of the present invention to provide a technique capable of reducing the area of the memory cell, thereby to increase the integration density of the DRAM.
It is a further object of this first aspect of the present invention to provide a technique capable of lowering the resistance of the connection portion between one of the semiconductor regions of the memory cell selecting MISFET of the memory
cell and, e.g., the stacked capacitor element of such memory cell.
It is a still further object of this first aspect of the present invention to provide a technique capable of preventing short-circuiting between a substrate and a data line which is connected to the memory cell selecting MISFET of the memory
cell.
The foregoing objects, and other objects, of the first aspect of the present invention are achieved by the presently described structure, which will be briefly summarized in the following. Such summary of this aspect of the present invention,
achieving the objects in connection with the first aspect of the present invention, as well as the following summaries in connection with the other aspects of the present invention, are illustrative, and not limiting. Moreover, while these summaries set
forth the various aspects of the present invention in terms of DRAMs having stacked capacitor elements, the present invention in all of its aspects is not to be limited thereto.
Thus, in each memory cell of a DRAM, the semiconductor region of the memory cell selecting MISFET to which the stacked capacitor element is connected is formed by ion implantation at an impurity concentration lower than that of the semiconductor
regions of the MISFETs of peripheral circuits of such DRAM.
In addition, the semiconductor region of the memory cell selecting MISFET to which the stacked capacitor element is connected is made up of a first semiconductor region of low impurity concentration which is formed by ion implantation, which has
formed therein a further semiconductor region of high impurity concentration which is formed by diffusion of an impurity introduced in the electrode layer of the stacked capacitor element, connected to the semiconductor region.
In addition, the other semiconductor region of the memory cell selecting MISFET of the memory cell, electrically connected to a data line, is formed of a semiconductor region of low impurity concentration which is formed by ion implantation, and
a still further semiconductor region, of high impurity concentration, which is formed by ion implantation carried out through a contact hole for connecting such other semiconductor region and the data line, is provided in such other semiconductor region.
According to such structure as discussed above, the occurrence of crystal defects in the semiconductor substrate, attributed to ion implantation when forming the semiconductor regions of the memory cell selecting MISFET, can be decreased, and
leakage of charges that store information in the stacked capacitor element can be reduced, so that the information retention characteristics of the DRAM can be enhanced. As a result, the frequency of refresh of the DRAM can be reduced, whereby the
operating speed of the DRAM can be increased.
Furthermore, since the semiconductor region of the memory cell selecting MISFET has a relatively-low impurity concentration, as compared to that of MISFETs of the peripheral circuit, the short channel effect can be suppressed, so that the area of
the memory cell can be reduced. As a result, a higher integration density of the DRAM can be achieved. Furthermore, through use of diffusing the impurity from the electrode layer of the stacked capacitor element into the semiconductor region of the
memory cell selecting MISFET, the contact resistance therebetween can be reduced.
Furthermore, since the semiconductor region of the memory cell selecting MISFET in contact with the data line is formed in part by ion implantation through a contact hole for the data line to be connected therewith, short-circuiting of the data
line and the substrate attributed to mask misregistration between the other semiconductor region of the memory cell selecting MISFET and the data line can be avoided.
B. In connection with the second aspect of the present invention, it is an object to provide a technique which enables an increase in the integration density of, e.g., a DRAM in which each memory cell includes an information storing capacitor
element over a substrate (e.g., a stacked capacitor element).
It is a further object of this second aspect of the present invention to provide a technique which enables effective utilization of space where select signal lines extend, in a DRAM utilizing a select signal line formed of the same conductive
layer as the data line.
It is a still further object of this second aspect of the present invention to provide a technique which enables an increase in the charge storage capacity of each stacked capacitor element in such a DRAM utilizing the select signal lines.
It is a still further object of this second aspect of the present invention to provide a technique which achieves reduction in the incidence of soft errors in, e.g., a DRAM utilizing such select signal lines.
The foregoing objects are achieved by the second aspect of the present invention, providing structure wherein each memory cell includes a stacked information storage capacitor element, a pair of complementary data lines and a select signal line
for selecting the data line, with the data lines and select signal line being formed from the same conductive layer and extending in the same column direction, and wherein the lower electrode layer of the stacked capacitor element is extended to a
position where it is overlapped by the select signal line.
By utilizing such structure wherein the lower electrode layer of the, e.g., stacked capacitor element is overlapped by the select signal line, it is possible to increase the area of the lower electrode layer by making use of the space below the
select signal line, whereby it is possible to increase the charge storing capacity of, e.g., the stacked capacitor element. Such increase in the charge storage capacity enables a decrease in the incidence of soft errors in the DRAM to be achieved.
Furthermore, since the incidence of soft errors can be reduced, it is possible to increase the integration density of the DRAM.
C. In connection with the third aspect of the present invention, it is an object to provide a technique capable of improving the information holding characteristics of the memory device (e.g., DRAM).
It is a further object of this third aspect of the present invention to provide a technique capable of increasing the operating speed of the DRAM.
It is a still further object of this third aspect of the present invention to provide a technique capable of increasing the integration density of the DRAM.
It is a still further object of this third aspect of the present invention to provide a technique capable of reducing the number of steps of fabricating the DRAM.
The foregoing objects of the third aspect of the present invention are achieved by the following technique.
Thus, in a DRAM, there is disposed below the semiconductor region of the memory cell selecting MISFET, to be connected with the stacked capacitor element, a potential barrier layer, which is formed by diffusing an impurity for forming a channel
stopper region. In such DRAM, it is particularly advantageous that such potential barrier layer, formed by diffusing an impurity for forming a channel stopper region, is provided below both semiconductor regions of the memory cell selecting MISFET.
Furthermore, the objectives of this third aspect of the present invention are further achieved by forming the channel stopper region and potential barrier layer in the same manufacturing step.
By forming such potential barrier layer as in this third aspect of the present invention, the minority carriers trapped by the capacitor element of the memory cell can be reduced, so that it is possible to prevent soft error of the memory cell
mode. Moreover, by such third aspect of the present invention, the impurity concentrations of the channel stopper region and the potential barrier layer can be made substantially equal, to improve the PN junction breakdown voltage between the potential
barrier layer and the semiconductor region to which the electrode of the stacked capacitor cell is connected, so that leakage of electrical charges of the stacked capacitor element (whereby information of the stacked capacitor element is lost) can be
reduced, to improve the information holding characteristics. As a result, the frequency required to refresh information in the DRAM can be reduced, thereby to increase the operating speed of the DRAM.
In addition, by providing the potential barrier layer beneath the semiconductor region of the memory cell selecting MISFET to which the data line is connected, it is possible to prevent soft error of the data line mode.
Furthermore, since the step of forming the potential barrier layer is performed simultaneously with the step of forming the channel stopper region, it becomes possible to reduce the number of steps for fabricating the DRAM. Moreover, since the
potential barrier layer is formed in self-alignment with the channel stopper region, the mask alignment margin of the fabrication process can be eliminated, which can improve the degree of integration of the DRAM.
Furthermore, since diffusion of the impurity introduced for forming the channel stopper region is utilized for forming the potential barrier layer, damage to the substrate caused by ion implantation to introduce the impurity for forming the
channel stopper region can be reduced, so as to reduce the crystal defects caused by the impurity introduction. As a result, it is possible to improve the refreshing characteristics of the DRAM.
D. In accordance with the fourth aspect of the present invention, it is an object to provide a technique of improving the breakdown strength of the dielectric film of the memory device (e.g., DRAM) which utilizes, e.g., a stacked capacitor
element for storage of information.
It is a further object of this fourth aspect of the present invention to provide a technique capable of improving the electrical reliability of the DRAM.
It is a further object of this fourth aspect of the present invention to provide a technique capable of highly integrating the DRAM by reducing the area of the memory cell.
It is still another object of this fourth aspect of the present invention to provide a technique capable of reducing the number of steps of fabricating the DRAM.
Each of the foregoing objects are achieved by the structure of this fourth aspect of the present invention, which will be summarized below. Generally, the stacked capacitor element of this fourth aspect of the present invention has a dielectric
film thereof constructed to have the same shape as that of the second electrode layer, which lies thereover.
In addition, an inter-layer insulating film is removed from the semiconductor region of the memory cell selecting MISFET which is to be connected with the data line, by using the second electrode layer or its patterning mask as a mask in such
removal.
By the technique specified in the foregoing, in connection with this fourth aspect of the present invention, the dielectric film of the stacked capacitor element can be coated (laminated) with the second electrode layer to reduce electrical
charges stored in the dielectric film (for example, at the time of plasma etching to form the second electrode layer), so that the insulating breakdown voltage of the dielectric film can be improved. As a result, it is possible to improve the electrical
reliability of the DRAM.
Furthermore, by this fourth aspect of the invention, the inter-layer insulating film over the semiconductor region of the memory cell selecting MISFET to be connected to the data line can be removed by using the second electrode layer, or its
patterning mask, as a mask, so that the number of steps of fabricating the DRAM can be reduced. Furthermore, such removal of the inter-layer insulating film can be accomplished in self-alignment with respect to the second electrode layer or its
patterning mask, so that the area of the memory cell can be reduced so as to improve the integration density of the DRAM.
E. In accordance with the fifth aspect of the present invention, it is an object to provide a technique which enables an improvement in the information holding characteristics of a memory device (e.g., a DRAM) having a capacitor element over the
substrate (e.g., a stacked capacitor element).
It is a further object of this fifth aspect of the present invention to provide a technique which permits enhancement in the dielectric strength of the dielectric film of the stacked capacitor element of the DRAM, and also permits a reduction in
the number of defects per unit area thereof.
It is still another object of th | | |
