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Description  |
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TECHNICAL FIELD
OF THE INVENTION
The invention relates to semiconductor "flip-chip" manufacturing techniques and, more particularly, to the fluxing and soldering steps employed in flip-chip manufacture.
BACKGROUND OF THE INVENTION
"Flip-chip" manufacturing techniques involve soldering one or more semiconductor (silicon) chips (one is discussed), in face-to-face relationship, to another semiconductor chip termed a "substrate". Typically, solder balls (otherwise known as
pads or bumps) are formed (raised above the planar surface of the chip and substrate) on facing surfaces of both the chip and the substrate at intended points of contact between the two, liquid flux (rosin) is often applied to the face of the chip and/or
substrate, the chip is mechanically held in register with the substrate, and the chip and the substrate are subjected to elevated temperature to effect soldering, or fusion of the solder balls on the chip and the corresponding solder balls on the
substrate.
The "solder balls" on either the chip or substrate, typically those on the substrate, may be solderable metallized surfaces. The soldering process may be carried out in a reducing atmosphere. A typical flip-chip structure is shown in FIG. 1,
and is discussed in greater detail hereinafter.
Previous systems of rigid attachment of chips to chucks have been used for chip alignment, but they must allow some degree of compliance because the chips tend to change relative alignment during soldering by surface tension between the solder
balls. The addition of liquid flux to the chip/substrate (flip-chip) assembly creates capillary attraction between the chip and the substrate, which serves to misalign the chip with respect to the substrate. This is illustrated in FIG. 2, and is
discussed in greater detail hereinafter. Further, much of the flux that is applied to the flip-chip assembly is wasted. Still further, the dimension of the remaining gap between the chip and the substrate and the mechanical properties of the solder
joints formed by the solder balls and corresponding solder balls tends to be indeterminate.
The present invention is more broadly (i.e., than chip-to-chip) directed to connecting one or more semiconductor "chips" (dies) to one or more "substrates" such as other semiconductor dies, printed circuit (or wiring) boards, and the like. The
resulting assembly is termed a "flip-chip structure".
DISCLOSURE OF THE INVENTION
It is therefore an object of the invention to provide a flip-chip manufacturing technique which reduces capillary action, and hence misalignment, between a chip and a substrate.
It is a further object of the invention to provide a flip-chip manufacturing technique which requires the use of less flux, and which controls the position of the flux between the chip and the substrate.
It is a further object of the invention to provide a flip-chip manufacturing technique which provides a controlled spacing between chips and the substrate.
It is a further object of the invention to provide a flip-chip manufacturing technique which provides solder joints having predictable and tailorable mechanical characteristics.
It is a further object of the invention to provide a flip-chip manufacturing technique that simplifies the face-to-face joining of the chip and substrate.
According to the invention, a preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure. The preformed planar structure establishes a minimum gap between the chip(s) and the substrate.
According to a feature of the invention, liquid flux is applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate.
In an embodiment of the invention, the preformed planar structure is provided with through holes in registration with the solder balls (pads) on the chip(s) and the substrate. In this embodiment, liquid flux selectively fills the through holes
for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate.
According to an aspect of the invention, the through holes are sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together.
According to an aspect of the invention, the preformed planar structure has a planar core and opposing planar faces. The core is formed of thermosetting organic resin, such as polyimide, or non-organic material such as alumina, polished
sapphire, beryllium oxide, anodized aluminum or aluminum nitride. The planar faces of the preformed planar structure are formed of thermoplastic resin or thermosetting material, such as polyacetal, epoxy (epoxy resins) or polystyrene. The preformed
planar structure tends to draw the chip(s) together to the substrate, establishing a flip-chip structure or mechanical integrity.
According to an aspect of the invention, the preformed planar structure has a thickness of 5-50 microns, preferably on the order of 20-30 microns.
Additional and further embodiments and variations of a preformed planar structure are set forth below, with respect to the descriptions of FIGS. 6-15.
Other objects, features and advantages of the invention will become apparent in light of the following description thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of a typical, prior art flip-chip structure.
FIG. 2 is a cross-sectional view of a prior art flip-chip assembly illustrating capillary action caused by liquid flux, resulting in the misalignment of a chip with respect to a substrate.
FIG. 3 is an exploded cross-sectional view of a flip-chip assembly, prior to soldering, according to a technique of the invention.
FIG. 4 is a perspective view of a plastic standoff element (preformed planar structure) employed in the technique of FIG. 3.
FIG. 5 is a perspective view of an alternate embodiment of a standoff element suitable to be employed in the technique of FIG. 3.
In the description of further embodiments of a preformed planar structure that follows, the preformed planar structure may alternately be referred to as an "interposer".
FIG. 6 is an exploded cross-sectional view of a flip-chip assembly incorporating a preformed planar structure (interposer), according to the invention.
FIG. 6a is a cross-sectional view of another embodiment of a preformed planar structure, similar to that shown in FIG. 6, according to the invention.
FIG. 6b is a cross-sectional view of another embodiment of a preformed planar structure, similar to that shown in FIG. 6a, according to the invention.
FIG. 6c is a cross-sectional view of an encapsulated semiconductor die assembled to a preformed planar structure, according to the invention.
FIG. 7 is a cutaway view of a preformed planar structure including a ring-shaped array of angled through holes, according to the invention.
FIG. 7a is a top view of the preformed planar structure of FIG. 7.
FIG. 7b is a top view of a preformed planar structure with a rectangular array of angled through holes, according to the invention.
FIG. 8 is a cross-sectional view of a semiconductor device assembly employing a preformed planar structure as a connection "pitch adapter", according to the invention.
FIG. 8a is a cross-sectional view of a semiconductor device assembly employing a multi-layer preformed planar structure as a connection pitch adapter, according to the invention.
FIG. 9a is a view of a semiconductor device assembly employing dissolvable preformed planar structures, according to the invention.
FIG. 9b is a view of a the semiconductor device assembly of FIG. 9a, after dissolving the preformed planar structures.
FIG. 10a is a view of a ring-shaped preformed planar structure, according to the invention.
FIG. 10b is a view of a gapped ring-shaped preformed planar structure, according to the invention.
FIG. 10c is a close-up top view of a portion of a leg of a kerfed ring-shaped preformed planar structure (interposer), according to the invention.
FIG. 10d is a side view of the kerfed interposer of FIG. 10c.
FIG. 10e is a close-up top view of a portion of a leg of another embodiment of a kerfed ring-shaped preformed planar structure (interposer), according to the invention.
FIG. 10f is a side view of the kerfed interposer of FIG. 10e.
FIG. 11a is a cross-sectional view of a semiconductor device assembly employing a preformed planar structure (interposer) with an embedded conductive trace and probe finger, according to the invention.
FIG. 11b is a cross-sectional view of a semiconductor device assembly employing a preformed planar structure with an embedded conductive trace electrically connecting two different solder bump connections, according to the invention.
FIG. 11c is a side view of a semiconductor device assembly employing a preformed planar structure (interposer) wherein embedded conductive traces exit the interposer and form conductive leads of the assembly, according to the invention.
FIG. 11d is a top view of a preformed planar structure (interposer) similar to that of FIG. 11c, wherein conductive leads embedded in the interposer are connected to an external "ribbon-cable", according to the invention
FIG. 12 is a cross-sectional view of a semiconductor device assembly employing noble metal conductors embedded in a preformed planar structure to prevent electro-galvanic corrosion of dissimilar solder bump contacts, according to the invention.
FIG. 13a is a cutaway side view of one embodiment of a stepped preformed planar structure, according to the invention.
FIG. 13b is a cutaway side view of another embodiment of a stepped preformed planar structure, according to the invention.
FIGS. 14a-d are side views of various embodiments of transparent, colored, clear, and translucent preformed planar structures (interposers) according to the invention.
FIG. 15a is a side view of a flip-chip semiconductor device assembly, according to the invention.
FIG. 15b is a side view of a multi-tier flip-chip semiconductor device assembly, according to the invention.
FIG. 15c is a cutaway side view of a flip-chip semiconductor device assembly, according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1 and 2 illustrate a prior art technique of assembling flip-chips 10. The completed flip-chip structure 10 includes one or more silicon chips 12 (two of such chips are illustrated) mounted in face-to-face relationship to a larger silicon
chip or substrate 14 in the following manner. Solder balls (or pads) 16 are formed on the face 12A of the chip 12, and solder balls (or pads) 18 are formed on the face 14A of the substrate in corresponding positions (i.e., to align with the solder balls
16 of the chips).
It should be understood that the solder balls on either the chip 12 or on the substrate, typically, the corresponding solder balls 18 on the substrate, may simply be solderable metallized surfaces.
It should also be understood that balls (of dollops) of conductive epoxy or polymer could be used in lieu of solder balls. In the main hereinbelow, solder balls are discussed.
Liquid flux 20 (shown in FIG. 2 only) is applied to the face 14A of the substrate, prior to bringing the chips 12 in face-to-face relationship with the substrate 14. The chips 12 are placed in face-to-face relationship by mechanical means, such
as with a chuck (not illustrated), and the temperature of the chips and substrate is elevated sufficiently to cause the solder balls 16 on the face 12A of the chips 12 to "fuse", forming solder joints, with the corresponding solder balls 18 on the face
14A of the substrate 14.
As illustrated in FIG. 2, the liquid flux 20 fills a gap 22 between the faces 12A of the chips 12 and the face 14A of the substrate 14, and also fills an area on the face 14A of the substrate 14 between the chips 12. Capillary action and/or
surface tension created by the presence of the liquid flux 20 causes the chips 12 to migrate to the center 24 of the substrate 14 during the soldering process, resulting in a lack of registration between the chips 12 and the substrate 14, and hence
between the solder balls 16 and the corresponding solder balls 18, respectively. This tendency of the chips to become misaligned during soldering is augmented by any initial lack of planarity between the chips 12 and the substrate 14, and is extremely
disadvantageous in the assembly of flip-chips. For instance, it becomes extremely difficult to characterize the mechanical configuration of the solder joints not only because of the difficulty in maintaining accurate registration, but also because of
the somewhat unpredictable dimension of the gap 22 between the chips and the substrate. This can adversely affect flip-chip throughput in the manufacturing process. Further, as is evident from FIG. 2, much more flux is used than is required to effect
clean solder joints between the solder balls 16 and corresponding solder balls 18, respectively.
FIG. 3 illustrates a technique of assembling flip-chips 30. In a manner similar to that previously discussed, the flip-chip assembly 30 includes one or more silicon chips 32 (two of such chips are illustrated) ultimately mounted in face-to-face
relationship to a larger silicon chip or substrate 34 in the following manner. Solder balls 36 are formed on the face 32A of the chip 32, and solder balls 38 are formed on the face 34A of the substrate 34 in corresponding positions. Notably, liquid
flux is not applied to the face 34A of the substrate 34, prior to soldering the chips 32 thereto. Nor is liquid flux required to be applied to the faces 32A of the chips 32.
Prior to soldering the chips 32 to the substrate 34, a preformed planar structure 40 (otherwise termed a "stamp" or "plastic standoff element", and discussed in greater detail hereinafter), of similar planar dimension as the chip 32, is
interposed between the chips 32 and the substrate 34. The planar structure 40 is provided with through holes 42 in positions corresponding to the positions of the solder balls 26 and 38, respectively. Inasmuch as the solder balls 36 are typically
located just within the perimeter of the chips 32, the through holes 42 would be located just within the perimeter of the planar structure 40.
Prior to soldering, the planar structure 40 is dipped (not illustrated) into a solution (bath) of liquid flux, such as rosin material, and is allowed to dry, as shown at 44. In this manner, the planar structure 40 receives selectively deposited
rosin preferentially within the holes 42, in registration with the corresponding solder balls 36 and 38, and there will be very little, if any, flux on the planar surface of the preformed planar structure. The capillary action of liquid solutions in
small holes draws the bulk of the liquid flux material into the through holes 42, which are disposed in register with the solder balls, to effect successful solder bonding.
This selective application of flux to the solder balls has numerous advantages: there will be very little flux on the surfaces of the planar structure; a minimum amount of rosin is used to flux the solder balls; extra (waste) flux is kept out of
the flip-chip assembly; and relative motion of the chips otherwise caused by the capillary action and/or surface tension of such excess molten flux will be minimized.
By successive dilution of the flux bath into which the planar structure is dipped, an optimal amount of flux can be empirically determined for particular applications that will both successfully flux the solder balls and minimize flux usage, and
the aforementioned problems inherent therein.
Thus, the chips 32 are more easily and accurately held in place by mechanical means, such as with a chuck (not illustrated) during soldering, resulting in increased throughput (yield) of flip-chips in the manufacturing process. Further, the
holes 42 in the planar structure 40 assist in maintaining registration of the solder balls 36 and corresponding solder balls 38, respectively, and hence alignment of the chips 32 with respect to the substrate 34.
FIG. 4 shows, in further detail, the preformed planar structure 40 used in the technique of FIG. 3. References to FIG. 3 are made in the following paragraphs.
The preformed planar structure 40 includes a planar core 46 formed of a material such as thermosetting organic resin or non-organic material (e.g. aluminum sheet, alumina sheet, beryllium oxide sheet). Laminated to both opposing faces of the
core 46 are planar layers (faces) 48 formed of thermoplastic (resin) or thermosetting "skin" which can be expected to soften significantly at the elevated temperatures employed for solder reflow in the flip-chip bonding process. This softening and
consequent shrinking of the thermoplastic resin skin (and hence shrinkage of the overall planar structure) will allow and encourage the chips to draw or grow closer to the substrate in response to surface tension caused by the molten solder balls and
surface tension of the skin itself. This "growing together" of the chips and substrate, in other words diminution of the gap therebetween, is desirable to ensure that each and every solder ball has an opportunity to grow together and successfully fuse.
Again, this enhances flip-chip throughput (yield) in the manufacturing process. It is also important to regulate the amount of growing together in that the requirements for solder ball shape may require a planar structure which does not generate a
structure of minimum surface area.
The thermoplastic faces 48 will re-solidify after soldering (upon reduction in temperature) and create a cushion for the faces 32A and 34A of the chips 32 and substrate 34, respectively. Simultaneously, the shrinkage of the planar structure 40,
especially the thermoplastic faces 48 thereof, will have the effect of drawing the chips together as they cool off to room temperature after soldering. In this manner, the solder balls are mechanically kept in contact with the chips and substrate,
respectively, as well as with each other.
The core 46 of the preformed planar structure exhibits good thermal conductivity, and is formed of a rigid thermosetting organic resin or non-organic material, such as polyimide, polished alumina, polished sapphire, beryllium oxide, anodized
aluminum/or aluminum nitride. A suitable polyimide is available from CIBA-GEIGY Corporation, Santa Clara, Calif., in their "PROBIMIDE" (a trademark of CIBA-GEIGY Corporation); 300 or 400 Series, or "SELECTILUX" (a trademark of CIBA-GEIGY Corporation);
HTR 3, microelectronic polyimide materials. The faces 48 of the preformed planar structure 40 are formed of a thermoplastic material such as polyacetal, epoxides or polystyrene. It is advantageous that the preformed planar structure exhibit hermeticity
and that it does not wick the liquid flux. The overall thickness of the preformed planar structure 40 is on the order of 5-50 microns, preferably 30--30 microns, and the preformed planar structure acts as a physical barrier standoff between the chips
and the substrate.
A synergistic effect results from the use of the preformed planar structure which effectively eliminates flux from the faces of the chips and substrate by selectively causing the flux to be deposited on the solder balls and corresponding solder
balls, respectively. Inasmuch as the faces of the chips and substrates are relatively clean, any adhesion of the planar structure (notably the "skin") thereto effects a mechanical connection of the solder balls and corresponding solder balls
irrespective of soldering. (Albeit; the adhesion and shrinkage become effective at the elevated temperature experienced during soldering). This satisfies the adage that, "good mechanical joints lead to good solder joints".
The preformed planar structure 40 serves as a plastic standoff element to determine the size of the gap between the chips and the substrate. Evidently, the relatively solid core 46 of the planar structure 40 sets a relatively rigid lower limit
on the amount that the chips can grow (draw) together to the substrate as the solder balls and corresponding solder balls melt and fuse together.
As mentioned hereinbefore, in prior art flip-chip manufacturing techniques the mechanical properties of the solder joints remain somewhat indeterminate. By use of the planar structure 40 in the manufacturing process, flip-chip structures can be
formed without the usual concerns about solder ball bond rigidity. Evidently, the through holes 42 form a generally cylindrical "mold" of predetermined dimension wherein the solder joints are formed. One may view the resulting solder joint formed
therein by the solder balls and corresponding solder balls as a mechanical structure (not illustrated) of predetermined dimension, and calculate the resulting mechanical properties thereof, such as rigidity (or elasticity), shear strength, tensile
strength, bending moment, etc.
FIG. 5 is a perspective view of an alternate embodiment of a preformed planar structure, or standoff element 50, suitable to be employed in the technique of FIG. 3. References to FIG. 3 are made in the following paragraphs.
With respect to the materials used to form the core 56 and faces 58, and the thickness thereof, the standoff element 50 is similar to the standoff element 40 shown in FIG. 4. However, rather than having through holes 42 in alignment with the
solder balls 36 and corresponding solder balls 38, the standoff element 50 may be provided with corner cutouts 52 in alignment with the solder balls 36 and corresponding solder balls 38, and is sufficiently sized so that the solder joints are formed just
outside its perimeter. The surfaces of the corner cutouts 52 can be left relatively rough (as compared with the faces 58) in order that liquid flux 54 tends to adhere thereto (as opposed to draining off the faces 58). As discussed with respect to the
planar structure 40, the liquid flux is applied to the planar structure 50 by dipping the planar structure in a bath of liquid flux which is allowed to dry thereon. Under the elevated temperatures employed for solder bonding, the flux will be delivered
to the solder balls 36 and to the corresponding solder balls 38.
The advantages of the standoff element (preformed planar structure) 50 are similar to those of the standoff element 40 with respect to forming a gap of predetermined dimension between the chip and the substrate, aiding in drawing together the
chip and the substrate, mechanically drawing together the solder balls and the corresponding solder balls, requiring less flux to effect soldering and, to a lesser extent aiding in maintaining alignment of the chip and the substrate and alleviating the
usual concerns about solder ball bond rigidity.
The preformed planar (layered) structure cushions and draws and holds (upon re-solidifying) the chip and the substrate together in the flip-chip manufacturing process. This improves the mechanical integrity of the flip-chip assembly and
increases the resistance thereof to loss of electrical contact between the solder balls. This is important in that the older balls themselves serve as the mechanical point of attachment between the chip and the substrate. Chip (to substrate) draw
together is controlled, and a permanent tension is created between the chip and substrate.
The invention solves the problem of using too much flux and having the position of the chips change during bonding (soldering). The invention allows the use of an absolute minimum of flux so subsequent cleaning of the flip-chip assembly is
simplified.
SUMMARY OF PARENT CASES
The aforementioned commonly-owned parent U.S. patent application Ser. Nos. 07/981,096 (U.S. Pat. No. 5,299,730), 07/775,009, (U.S. Pat. No. 5,168,346), 07/576,182 (U.S. Pat. No. 5,111,279) and 07/400,572 (abandoned), describe a preformed
planar structure which is suitable to be interposed between a semiconductor die and a substrate. In one embodiment, the preformed planar structure is provided with through holes, that are ultimately filled with a conductive material. Furthermore, the
preformed planar structure may be formed as a multi-layer structure having a planar core and opposing planar faces. The core may be formed of thermosetting organic resin, such as polyimide, or of non-organic material such as alumina, polished sapphire,
beryllium oxide, aluminum nitride or anodized aluminum. The planar faces of the preformed planar structure may be formed of thermoplastic resin or thermosetting material, such as polyacetal, epoxide resin or polystyrene. Methods of mounting a chip
(e.g., semiconductor die) to a substrate (e.g., another semiconductor die), using the preformed planar structure are discussed.
Generally, as described in parent, commonly-owned U.S. Pat. Nos. 5,111,279 and 5,168,346, the preformed planar structures serve at least two purposes: (1) the through holes or cutouts allow for selective fluxing and ensure predictable
mechanical characteristics of joints formed by solder balls, and (2) the preformed planar structure provides a prescribed standoff (separation) between the chip and the substrate, and also helps draw them together in intimate contact with the preformed
planar structure.
In the discussion that follows, the preformed planar structure is often referred to as an "interposer", especially in those cases where it is literally interposed between a chip and a substrate. Further, in the discussion that follows, it should
be understood that the substrate could be a printed circuit board, another chip or chips, or the like. It should further be understood that the chip could be a complete packaged semiconductor device.
Use of the preformed planar structure as a pitch-spreader
The preformed planar structures of commonly-owned parent U.S. Pat. Nos. 5,111,279 and 5,168,346 generally disclose an interposer (preformed planar structure) for forming solder joints between a chip and a substrate having the same pitch, or
spacing, of solder bumps. Generally, the through holes or cut outs extended perpendicularly through the preformed planar structure.
It is an object of the present invention to provide a preformed planar structure suitable for interposing between, and aiding in joining together, a chip having an array (pattern) of solder bumps at one pitch (spacing from one another) and a
substrate having an array of solder bumps disposed at another, dissimilar pitch.
It is an object of the invention to provide an improved technique for packaging semiconductor dies, and for interconnecting the packaged dies to external systems.
According to the invention, one face of a preformed planar structure (interposer) is provided with an array of holes disposed at one pitch (spacing) for aligning with the solder bumps of a chip, and the other face of the preformed planar
structure is provided with an array of holes at another pitch for aligning with solder bumps on a substrate. Angled or bent through holes through the preformed planar structure extend from the one holes to the other holes, and may be partially or fully
filled with a conductive material prior to assembling the chip to the substrate.
According to the invention, a preformed planar structure is interposed between at least one die and an underlying substrate. (The underlying substrate being part of an external system, such as a printed circuit board). The preformed planar
structure is provided with at least one through hole. At least one electrical connection is made from the at least one die, through the at least one through hole to connection points on the underlying substrate.
In one embodiment of the invention, the die is flipped face-down onto a face of the preformed planar structure, and solder balls on the face of the die align with the through holes on the face of the preformed planar structure. Circuit elements
may be formed on the face (obverse) or back (reverse) side of the die. Typically, the circuit elements would be formed on the face of the die.
According to an aspect of the invention, the (at least one) through holes in the preformed planar structure are pre-filled, or partially pre-filled, with conductive material, such as metal, solder, or conductive polymer or epoxy, such as
silver-filled epoxy.
According to a feature of the invention, the reverse (opposite the die) side of the preformed planar structure is provided with ball bumps, or the like, for making connections from external systems (via the underlying substrate) to the die. In
this case, the preformed planar structure forms a significant part of the package body surrounding and/or supporting the die.
According to a feature of the invention, the through holes are partially pre-filled with conductive material, and are then pre-fluxed for subsequent attachment of the die and formation of the ball bumps.
According to an aspect of the invention, the through holes are disposed at various angles through the preformed planar structure so that they have a first, relatively close spacing on the face of the preformed planar structure receiving the die
(for making connections to an array of closely-spaced solder bumps on the face of the die), and have a second, relatively far-apart spacing on the face of the preformed planar structure making connection to external systems. The connection to external
systems would typically be achieved by means of a printed circuit board (PCB) which would have connection points disposed at a greater pitch than the solder bumps on the die.
According to another embodiment of the invention, at least one die is mounted to a preformed planar structure having at least one through hole. At least one connection to the die is made through the at least one through hole. Additional
connections to the die are made on the side of the die facing away from the preformed planar structure, such as by wire bonding.
According to an aspect of either embodiment of the invention, the preformed planar structure has a planar core and opposing planar faces. The core is formed of thermosetting organic resin, such as polyimide, or non-organic material such as
alumina, polished sapphire, beryllium oxide, anodized aluminum or aluminum nitride. The planar faces of the preformed planar structure are formed of thermoplastic resin or thermosetting material, such as polyacetal, epoxy (epoxide resins) or
polystyrene.
Other objects, features and advantages of the invention will become apparent in light of the following description thereof.
FIG. 6 shows (exploded) a die 602 flipped onto a face 604 of a preformed planar structure 606. The preformed planar structure 606 is similar to the previously described structures (see, e.g., the structure described as 40, FIG. 3), but the
through holes 608 (compare with through holes 42, FIG. 3) are at least partially filled with a conductive material 610. For example, the conductive material 610 is recessed below the die-side 604 of the preformed planar structure. In this manner,
conductive balls (raised conductive bumps) 612 disposed on the face 614 of the die will partially enter the recesses 608 formed in the top surface 604 of the preformed planar structure 606. Additionally, because the conductive material is recessed, flux
can be selectively applied to the preformed planar structure, depositing itself exclusively in the recesses, in a manner similar to that set forth with respect to the preformed planar structure 40 (FIG. 3).
The conductive material 610 may be metal, which will fuse with the balls 612, which may be formed of solder. In this manner, a solder joint of predetermined mechanical structure is formed in the recess, similar to what has been described above
with respect to FIGS. 3-5.
Alternatively, the conductive material may be a conductive polymer, and the balls 612 may also be formed of a conductive polymer, in which case there will be an adhesion between the balls 612 and the conductive material 610.
It is within the scope of this invention that the conductive material 610 is not recessed below the surface 604 of the preformed planar structure, but is flush with same, as shown in FIG. 6a, or extends slightly above the surface of same, as
shown in FIG. 6b.
In a similar manner, the conductive material 610 may extend only partially to the opposite surface 618 of the preformed planar structure 606, as shown in FIG. 6, and the resulting recesses can be pre-fluxed in a manner similar to that described
with respect to the preformed planar structure 40 (FIG. 3). The recesses formed by the partially-filled through holes will allow self-registration of conductive balls (raised conductive bumps) 620 on the surface of an underlying substrate 622 to
self-self align with the preformed planar structure (with die mounted thereto). The underlying substrate is, for example, a printed circuit board with wire traces (not shown), and electrically connects the die to external components or systems (not
shown).
As shown in FIG. 6, solder balls 621 may be formed on the bottom surface of the preformed planar structure.
As shown in FIG. 6c, the preformed planar structure 606 is preferably larger than the die 602, and the die, once joined to the preformed planar structure, can be encapsulated with epoxy 624, or the like. In this manner, the preformed planar
structure 606 forms part of a package body enclosing the die. The epoxy 624 forms the remainder of the package body. The preformed planar structure of FIG. 6c would preferably be provided with solder balls such as those shown in FIG. 6 at 621.
The preformed planar structure 606 is preferably thicker than the previously described preformed planar structures (e.g., 40, 50, FIG. 3), and preferably will provide adequate structural support for the die, especially when used in the manner set
forth with respect to FIG. 6c. Additionally, a thicker (e.g., than that of FIG. 3) preformed planar structure may be used as a "pitch adapter" for connecting conductive bumps (612) of the die, at a relatively fine pitch, to conductive bumps (620) of an
underlying substrate at a relatively coarse pitch.
FIG. 7 shows a cutaway portion of a relatively thick preformed planar structure (interposer) 700 having one surface 702 upon which a die (not shown) will be mounted, and an opposite surface 704 which will be mounted to an underlying substrate
(not shown). (The remaining outline of the preformed planar structure 700 is shown in dashed lines 700a.) The preformed planar structure 700 is similar to that described with respect to FIGS. 6, 6a-6c, with the exception that the through holes 710 are
arranged at a range of angles with respect to the surfaces 702, 704, such that at least some of the openings (e.g., 716) of the through holes 710 in the bottom surface 704 are not directly under (i.e., are offset from) corresponding openings (e.g., 706)
in the top surface 702 of the interposer 700. In the preformed planar structures described hereinabove (40, 606), the through holes were generally all disposed at ninety degrees ("normal") to the surfaces of the preformed planar structure, such that the
bottom openings of the through holes were located generally directly beneath the corresponding top openings.
By angling the through holes 710, at a range of angles, the through holes can be made to exit the one surface 702 of the preformed planar structure 700 at one spacing ("pitch"), for example in a linear array matching a pattern of closely spaced
conductive bumps arranged around the periphery of a die, and can be made to exit the other surface 704 of the preformed planar structure 700 at a different, larger pitch, for matching a pattern of conductive bumps (or pads) on an underlying substrate
(e.g., PWB), which may be arranged in a rectangular array of rows and columns.
FIG. 7a shows a top view of the preformed planar structure 700, and is illustrative of relatively close spacing of the top openings 706 of the through holes 710 as they exit the die-mounting face 702 of the preformed planar structure. Dashed
lines indicate the angled trajectory of the through holes 710 through the preformed planar structure 700, ending in bottom openings 716 which are relatively more widely spaced than the top openings 706.
FIG. 7b shows a top view of a similar preformed planar structure 700'. Whereas the preformed planar structure 700 of FIG. 7 showed through holes 710 the top openings of which were arranged in rows, the preformed planar structure 700' has through
holes 710' with top openings 706' arranged in a rectangular array on a top (die mounting) surface 702 thereof. As indicated by dashed lines, the through holes 710' generally "fan outward" as they pass through the preformed planar structure 700', ending
in bottom (substrate-side) openings 716' which are generally wider spaced than the top side openings 706'.
The through holes 710 or 710' are filled with conductive material (not shown) in one of three ways at each surface: (1) the conductive material is recessed below the surface (compare FIG. 6); (2) the conductive material is flush with the surface
(compare FIG. 6a); (3) the conductive material extends out of the surface (compare FIG. 6b). Ball bumps may suitably be applied to the non-die side of the pitch-spreading interposer, and a die mounted thereto can be encapsulated as in FIG. 6c.
The preformed planar structure of this invention can be advantageously applied to situations where it is desirable to package semiconductor dies and attach the packaged dies to underlying substrates having a rectangular array (rows and columns)
or ring-shaped array (e.g., as in FIG. 7a) of connection points.
The preformed planar structure (interposer) of this invention can also be advantageously applied to situation where it is necessary to accommodate less regular arrangements of connection points. For example, a substrate might have connection
points disposed in a zig-zag (or seemingly random) pattern to mate with corresponding solder bump contacts on a semiconductor die arranged in a linear configuration. By providing a preformed planar structure similar to that described with respect to
FIG. 7a, but having bottom side (substrate side) through hole openings matching the zig-zag pattern and top side (die-side) through hole openings in a linear arrangement, the die can be readily adapted, i.e., connected, to the substrate. In other words,
the interposer of this invention can serve not only as a pitch spreader, but can also be advantageously employed as an adapter to join connection points (e.g., of a die and a substrate) having completely dissimilar patterns. It will be readily
appreciated by one of ordinary skill in the art that many different types of connection point adaptations can be accommodated by the present invention.
It is possible to mount a die to one face of a printed circuit board, for example using wire bonding techniques, and to provide the other face of the printed circuit board with solder bumps (e.g., a two-dimensional rectangular array of raised
contacts). Generally, the printed circuit board is provided with plated vias holes connecting wiring traces on the one (die) side of the board to the other (ball bump) side of the board. Additionally, there are traces on the bottom side of the board
connecting the plated vias to the ball bumps. An inherent problem with the traces and ball bumps on the other (ball bump) side of the board is that the plated vias are generally arranged around the periphery of the board, and must navigate through
adjacent ball bumps, especially to connect to ball bumps located in central areas of the array. Consequently, the ball bumps must be arranged with rather wide spacing, to accommodate one or more (typically more) traces passing therebetween.
By using the preformed planar structure (e.g., 700) of the present invention, there is no need for traces on the bottom (away from the die) side of the package body. As mentioned hereinbefore, the bottom side of the preformed planar structure
may be provided with conductive ball bumps, for surface-mounting the packaged die to a printed circuit board (compare FIG. 6).
Preferably, the face of the preformed planar structure to which the die is attached is provided with a thermoplastic layer, or the like (compare 40), which will have the effect of drawing the semiconductor die into intimate contact with the
preformed planar structure.
FIG. 8 shows an alternate embodiment of the invention, wherein a die 800 is mounted to a face of the preformed planar structure 802, and is connected with bond wires 804 thereto. In other respects, the preformed planar structure may be similar
to any of the preformed planar structures (606, 700) set forth hereinabove. For example, the through holes 806 can be formed at angles with respect to the faces of the preformed planar structure.
It will be readily appreciated by one of ordinary skill in the art that any of the above-mentioned preformed planar structures can be fabricated as a multi-layer structure. FIG. 8a shows an example of such a multi-layer structure, similar to
that shown in FIG. 8, except that three laminated layers 802a, 802b, and 802c form the preformed planar structure. In this case, through holes can be "stepped" (they can follow non-linear paths). A through hole consisting of three parts, 806a, 806b,
and 806c, is shown extending through the three layers 802a, 802b, and 802c. The top-most portion 806a (nearest the die 800) of the through hole extends vertically (as depicted) through the top-most layer 802a of the preformed planar structure. A second
portion 806b of the through hole extends horizontally through the second layer 802b. A bottom-most portion 806c of the through hole extends vertically through the bottom-most layer 802c of the preformed planar structure. Techniques similar to those
used for multi-layer printed circuit boards can be used to form the individual portions of the through holes in the individual layers, and to fill them with conductive material. The end result is similar to that shown in FIGS. 7a-7c and 8, where the
bottom opening (substrate side) of the through hole need not be directly under the top opening (die side).
Dissolvable Preformed Planar Structure
The preformed planar structures (interposers) of commonly-owned parent U.S. Pat. Nos. 5,111,279 and 5,168,346 generally disclose a "spacer" or "interposer" between a semiconductor die and another die or substrate. Evidently, when a chip (or
chips) is assembled to a substrate, as indicated by FIG. 3, the preformed planar structure (40, 50) remains interposed between the chip(s) and the substrate, and may provide for entrapment of contaminants. Contaminants in a flip-chip structure
(assembly) are generally undesirable, and may lead to device failure.
It is therefore an object of this embodiment of the invention to provide means for alleviating (avoiding) entrapment of contaminants in flip-chip assemblies incorporating an interposed preformed planar structure.
According to the invention, a dissolvable preformed planar structure can be formed similarly to other preformed planar structures described herein (especially those of FIGS. 3-5), and used to assemble a semiconductor die to a substrate in much
the same manner as described hereinabove (e.g., with respect to FIG. 3). After assembly, the preformed planar structure is dissolved with a suitable solvent, permitting more effective removal of contaminants trapped during the assembly process.
FIG. 9a is a cross-sectional view of a flip-chip assembly, prior to soldering, similar to that of FIG. 3, but employing a dissolvable preformed planar structure 40'. As in FIG. 3, the flip-chip assembly 30 includes one or more silicon chips 32
(two shown) ultimately mounted in face-to-face relationship to a larger silicon chip or substrate 34. Solder balls 36 are formed on the face 32A of each chip 32, and solder balls 38 are formed on the face 34A of the substrate 34 in corresponding
positions. Also as in the assembly of FIG. 3, liquid flux is not applied to the face 34A of the substrate 34, prior to soldering the chips 32 thereto. Nor is liquid flux required to be applied to the faces 32A of the chips 32. Prior to soldering the
chips 32 to the substrate 34, the preformed planar structure 40', is interposed between the chips 32 and the substrate 34.
As in the assembly of FIG. 3, the preformed planar structure 40' is dipped (not shown) in liquid flux, so that it adheres within the bore of the through holes (or to the surface of the cutouts). This selective application of flux to the solder
balls has the same advantages as described hereinabove with respect to FIG. 3 and can be controlled in the same manner as described hereinabove.
After soldering (application of heat to reflow the solder balls), solder joints form within the through holes (or cutouts), and the preformed planar structure is removed by exposing it to a suitable solvent. The result is shown in FIG. 9b,
wherein electrical connections 36A formed by reflow soldering remain after removal of the preformed planar structure 40'. After dissolution of the preformed planar structure 40', the assembly 30 can be cleaned with a suitable solvent to remove any
remaining contaminants. Alternatively, the preformed planar structure 40' can be made of a material which is soluble in the solvent used to remove the contaminants, permitting dissolution of the preformed planar structure 40' and removal of the
contaminants in a single step. One skilled in the art to which this invention most nearly pertains will understand that the solvent must be chosen in accordance to the particular material of which the interposer (preformed planar structure) is formed.
It will be readily appreciated by one of ordinary skill in the art that the use of a dissolvable preformed planar structure provides all of the assembly advantages of the other preformed planar structures described hereinabove, and has the
additional advantage that by removal (dissolution) of the preformed planar structure, any contaminants trapped during assembly can be very effectively eliminated. For example, the interposers of FIGS. 6, 6a, 6b, 7, 7a or 7b could readily be dissolved
after the chip is connected to a substrate. Moreover, it is within the scope of this invention that a chip is mounted to an interposer such as that of FIGS. 6, 6a or 6b, then the interposer would be dissolved, leaving a chip with exaggerated raised
contacts (e.g., 610) on the surface thereof, to later be mounted to a substrate.
Flexible Preformed Planar Structure
The preformed planar structures (interposers) of commonly-owned parent U.S. Pat. Nos. 5,111,279 and 5,168,346 are generally solid and unyielding, and therefore generally unable to conform to poorly planarized substrates such as printed circuit
board substrates. (It is assumed that, typically, the die itself is relatively highly planar.) In such a case of mounting a die to a non-planar substrate surface, the interposer structure could actually "lever" the die away from the substrate, which
would lead to less reliable solder bump attachment.
According to the invention, the interposer is formed as a ring like str | | |
