Thin-film transistor array and liquid crystal display device using the thin-film transistor array

What is claimed is:

1. A thin film transistor array comprising:

an insulative substrate;

a plurality of pixel electrodes arranged in a matrix above the insulative substrate, said pixel electrodes being arranged in a display region of the array;

a plurality of thin film transistors connected to the pixel electrodes, respectively;

a plurality of address lines formed on or above said insulative substrate and having connection terminals for connection with a driver circuit at a region outside the display region in which said pixel electrodes are arranged, each address line being connected to a plurality of control electrodes of said thin film transistors;

a plurality of data lines arranged on or above the insulative substrate in such a manner as to intersect with the address lines and having connection terminals for connection with a driving circuit at a region outside the display region in which said pixel electrodes are arranged, each data line being connected to a plurality of data input electrodes of said thin film transistors;

each of said thin film transistors comprising a gate electrode formed on said insulative substrate, said gate electrode serving as the control electrode, a gate insulating film covering the gate electrode, a first semiconductor film, a drain electrode formed on one side of the first semiconductor film via an ohmic contact layer and connected to a corresponding one of said data lines, said drain electrode serving as the data input electrode, and a source electrode formed on another side of the first semiconductor film via another ohmic contact layer and connected to a corresponding one of said pixel electrodes;

the gate insulating films of the thin film transistors comprising one common insulating film formed in substantially an entire display region of said insulative substrate;

at least one address line short-circuiting conductor in a region of the insulative substrate outside the display region in which said pixel electrodes are arranged, and connected to said address lines by respective thin film two-terminal elements, said two-terminal elements each having non-linear resistance characteristics; and

at least one data line short-circuiting conductor, insulated from said at least one address line short-circuiting conductor, formed on a region of the insulative substrate outside the display region in which said pixel electrodes are arranged, and connected to said data lines by respective thin film two-terminal elements, said two-terminal elements each having non-linear resistance characteristics;

said at least one address line short-circuiting conductor and said at least one data line short-circuiting conductor being formed inside of a terminal arrangement section in which the connection terminals of the address lines and the data lines are arranged; and

each of said two-terminal elements comprising:

a second semiconductor film which is formed on the common insulating film;

a first electrode formed on one side of the second semiconductor film and connected to one of said data and address lines;

a second electrode formed on another side of the second semiconductor film and connected to one of said short-circuiting conductors;

an ohmic contact layer between said first electrode and said second semiconductor film; and

another ohmic contact layer between said second electrode and said second semiconductor film.

2. A liquid crystal display device comprising:

a first insulative substrate;

a plurality of pixel electrodes arranged in a matrix above the first insulative substrate;

a plurality of thin film transistors connected to the pixel electrodes, respectively;

a plurality of address lines formed on or above the first insulative substrate, each address line being connected to a plurality of control electrodes of said thin film transistors, said address lines being supplied with address signals for successively selecting the address lines;

a plurality of data lines arranged on or above the first insulative substrate so as to intersect the address lines, each data line being connected to a plurality of data input electrodes of said thin film transistors, said data lines being supplied with data signals corresponding to display data to be displayed and having a potential waveform inverted at predetermined cycles;

at least one short-circuiting wire formed on or above the first insulative substrate and outside of a display region in which the pixel electrodes are arranged, wherein at least two lines of said plurality of address lines and at least two lines of said plurality of data lines are connected to said at least one short-circuiting wire by respective two-terminal elements, said two-terminal elements each having non-linear resistance characteristics;

a short-wiring driver, connected to said at least one short-circuiting wire, for applying a predetermined potential to said at least one short-circuiting wire;

a second insulative substrate opposed to a surface of said first insulative substrate, said second insulative substrate having a surface provided with at least one opposed electrode opposed to said pixel electrodes; and

a liquid crystal layer of a predetermined thickness interposed between said first and second insulative substrates;

wherein said short-wiring driver supplies to said at least one short-circuiting wire a potential which is synchronized with an inverted cycle of said data signals supplied to the data lines and is inverted with the same potential and same phase as the data signals with reference to a potential applied to the at least one opposed electrode formed on the second substrate.

3. A liquid crystal display device comprising:

a first insulative substrate;

a plurality of pixel electrodes arranged in a matrix above the first insulative substrate;

a plurality of thin film transistors connected to the pixel electrodes, respectively;

a plurality of address lines formed on or above the first insulative substrate, each address line being connected to a plurality of control electrodes of said thin film transistors, said address lines being supplied with address signals for successively selecting the address lines;

a plurality of data lines arranged on or above the first insulative substrate so as to intersect the address lines, each data line being connected to a plurality of data input electrodes of said thin film transistors, said data lines being supplied with data signals corresponding to display data to be displayed and having a potential waveform inverted at predetermined cycles;

at least one short-circuiting wire formed on or above the first insulative substrate and outside of a display region in which the pixel electrodes are arranged, wherein at least two address lines of said plurality of address lines and at least two data lines of said plurality of data lines are connected to said at least one short-circuiting wire by respective two-terminal elements, said two-terminal elements each having non-linear resistance characteristics;

a short-wiring driver, connected to said at least one short-circuiting wire, for applying a predetermined potential to said at least one short-circuiting wire;

a second insulative substrate opposed to a surface of said first insulative substrate, said second insulative substrate having a surface provided with at least one opposed electrode opposed to said pixel electrodes; and

a liquid crystal layer of a predetermined thickness interposed between said first and second insulative substrates;

wherein said short-wiring driver supplies to said at least one short-circuiting wire a potential which is synchronized with said data signals supplied to the data lines and is inverted with the same potential and opposite phase as the data signals, with reference to a potential applied to the at least one opposed electrode formed on the second substrate.

4. A thin film transistor array comprising:

an insulative substrate;

a plurality of pixel electrodes arranged in a matrix above the insulative substrate, said pixel electrodes being arranged in a display region of the array;

a plurality of thin film transistors connected to the pixel electrodes, respectively;

a plurality of address lines formed on or above said insulative substrate and having connection terminals for connection with a driver circuit at a region outside the display region in which said pixel electrodes are arranged, each address line being connected to a plurality of control electrodes of said thin film transistors;

a plurality of data lines arranged on or above the insulative substrate in such a manner as to intersect with the address lines and having connection terminals for connection with a driving circuit at a region outside the display region in which said pixel electrodes are arranged, each data line being connected to a plurality of data input electrodes of said thin film transistors;

at least one address line short-circuiting conductor in a region of the insulative substrate outside the display region in which said pixel electrodes are arranged, and connected to only said address lines; and

at least one data line short-circuiting conductor, insulated from said address line short-circuiting conductor, formed on a region of the insulative substrate outside the display region in which said pixel electrodes are arranged, and connected to only said data lines; and wherein:

said at least one address line short-circuiting conductor and said at least one data line short-circuiting conductor are formed inside of a terminal arrangement section in which the connection terminals of the address lines and the data lines are arranged; and

said address lines and said data lines are connected to said at least one address line short-circuiting conductor and to said at least one data line short-circuiting conductor by respective thin film two-terminal elements having non-linear resistance characteristics.

5. A thin film transistor array according to claim 4, wherein:

said at least one address line short-circuiting conductor comprises two first short-circuiting wirings formed along opposed edges of said display region;

at least two of said address lines are connected to each of the first short-circuiting wirings;

said at least one data line short-circuiting conductor comprises two second short-circuiting wirings formed along opposed edges of said display region; and

at least two of said data lines are connected to each of the second short-circuiting wirings.

6. A thin film transistor array comprising:

a plurality of pixel electrodes arranged in a matrix above the insulative substrate, said pixel electrodes being arranged in a display region of the array;

a plurality of thin film transistors connected to the pixel electrodes, respectively;

a plurality of address lines formed on or above said insulative substrate and having connection terminals for connection with a driver circuit at a region outside the display region in which said pixel electrodes are arranged, each address line being connected to a plurality of control electrodes of said thin film transistors;

a plurality of data lines arranged on or above the insulative substrate in such a manner as to intersect with the address lines and having connection terminals for connection with a driving circuit at a region outside the display region in which said pixel electrodes are arranged, each data line being connected to a plurality of data input electrodes of said thin film transistors;

at least one address line short-circuiting conductor in a region of the insulative substrate outside the display region in which said pixel electrodes are arranged, and connected to only said address lines; and

at least one data line short-circuiting conductor, insulated from said address line short-circuiting conductor, formed on a region of the insulative substrate outside the display region in which said pixel electrodes are arranged, and connected to only said data lines; and wherein:

said at least one address line short-circuiting conductor and said at least one data line short-circuiting conductor comprise:

first short-circuiting wirings formed inside of a terminal arrangement section in which the connection terminals of the address lines and the data lines are arranged, wherein said address lines and said data lines are connected to said first short-circuiting wirings by respective thin film two-terminal elements having non-linear resistance characteristics; and

second short-circuiting wirings formed outside of the terminal arrangement section, wherein said address lines and said data lines are connected to said second short-circuiting wirings.

7. A thin film transistor array according to claim 4, wherein said thin film two-terminal elements each include:

a double-injection type thin film non-linear resistor element in which holes and electrons are injected as carriers, said double-injection type thin film non-linear resistor element comprising a semiconductor film of a non-doped hydrogenated amorphous silicon film formed on or above the insulative substrate, said semiconductor film having two ends;

a first electrode formed on one end of said semiconductor film and connected to one of said data and address lines; and

a second electrode formed on another end of said semiconductor film and connected to one of said short-circuiting conductors.

8. A thin film transistor array according to claim 4, wherein said thin film two-terminal elements each include:

a thin film non-linear resistor element in which electrons are injected as a carrier, said thin film non-linear resistor element comprising a semiconductor film of a non-doped hydrogenated amorphous silicon film formed on or above the insulative substrate, said semiconductor film having two ends;

two n-type amorphous silicon films doped with n-type impurities and respectively formed at both ends of said semiconductor film;

a first electrode formed on one of said n-type amorphous silicon films and connected to one of said data and address lines; and

a second electrode formed on the other of said n-type amorphous silicon films and connected to one of said short-circuiting conductors.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin-film transistor array used in a liquid crystal display (LCD) device, in which display electrodes connected to thin-film transistors are arranged in a matrix, and an LCD apparatus using the thin-film transistor array.

2. Description of the Related Art

There has conventionally been known an active matrix type liquid crystal display device using a thin film transistor array (hereinafter referred to as "TFT-LCD") in which thin film transistors ("TFT") and pixel electrodes are arranged in a matrix.

An example of such a conventional TFT-LCD is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 59-166984. FIG. 32 shows an equivalent circuit of the TFT array used in this TFT-LCD.

As is shown in FIG. 32, in the TFT array, address lines 2 and data lines 3 are arranged in rows and columns on a transparent insulating substrate 1 such that the address lines 2 intersect the data lines 3 at right angles. TFTs 4 having their gates connected to the address lines 2 and their drains connected to the data lines 3 are arranged in a matrix at the intersections of the address lines 2 and data lines 3. Pixel electrodes 5 connected to the sources of the TFTs 4 are arranged in a matrix. A short-wiring or short-ring 6 is formed on an outer peripheral portion of the transparent insulating substrate 1 along the outer periphery of the substrate 1. The data lines and address lines 3 electrically are connected to the short-wiring 6 via their terminal portions 2a and 3a.

After the processing of the TFT array is completed, the substrate 1 is cut along broken lines 7 shown in FIG. 32. Then, the substrate 1 is bonded to an opposed substrate having opposed electrodes with a predetermined gap therebetween, and a liquid crystal material is sealed between these substrates. Thus, an LCD device is formed.

In the manufacturing process of this TFT array, a DC static electricity occurs while the substrate is exposed to a plasma or subjected to a rubbing process. However, since all address lines 2 and data lines 3 are connected to the short-wiring 6, the potential of all address lines 2 and data lines 3 is equalized and it is possible to prevent a problem of dielectric breakdown or short-circuit due to a discharge of static electricity between electrodes.

However, in the manufacturing process of the conventional LCD device using the TFT array, the TFT array is bonded to an opposed substrate via a sealing member and then the short-wiring 6 is cut along broken lines 7 and removed. Thus, owing to static electricity occurring in the subsequent manufacturing steps of adhering a polarizing plate, connecting a driving circuit, etc., there may occur dielectric breakdown, line breakage, a characteristic variation of the TFTs, etc., resulting in a display defect in the LCD device. Consequently, a manufacturing yield may deteriorate.

FIG. 33 shows a structure for preventing dielectric breakdown, etc. due to static electricity in the LCD device after the TFT array is completed. A short-wiring 8 is formed between a display region, in which the pixel electrodes 5 connected to the TFTs 4 are arranged in a matrix, and a terminal array section in which the terminal portions 3a of data lines 3 and the terminal portions 2a of address lines 2 are arranged, such that the short-wiring 8 surrounds the display region. The short-wiring 8 is connected to the data lines 3 and address lines 2 by protection elements 9 each comprising a plurality of diodes designed to have non-linear current-voltage characteristics, as shown in FIG. 34.

In the TFT array having the protection elements 9, the protection elements 9 are turned on if static electricity occurs after the short-wiring 6 shown in FIG. 32 is cut and a high voltage is applied between the short-wiring 6 and the data lines 3 and address lines 2. As a result, a voltage difference between the data lines 3 and address lines 2 is eliminated, and dielectric breakdown between the data lines 3 and address lines 2 can be prevented.

The structure of the above-described protection elements, however, is complex, and steps other than those for forming TFTs are required. Thus, the number of steps for manufacturing the TFT panel increases and the manufacturing yield of TFTs considerably deteriorates owing to the increased steps.

The conventional TFT panels shown in FIGS. 32 and 33 have a problem in that the TFT panel has a low electrostatic destruction preventing effect against pulsatile static electricity, which is applied when the TFT panel is handled by operators, when the TFT panel is put in contact with an electrified manufacturing apparatus, when the rubbing roller approaches the substrate, or when the substrate is cut, at which time most of electrostatic destruction occurs.

Furthermore, in the TFT panel having the protection elements shown in FIG. 32, a leak current flows between the address lines 2 and data lines 3 via the protection elements 9. Thus, much crosstalk occurs, the display quality deteriorates and much current is consumed.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a thin film transistor array capable of reducing the possibility of the aforementioned display defect due to static electricity of a liquid crystal display device, increasing the yield, and decreasing power consumption with easy manufacturing, and to provide a liquid crystal display device using the thin film transistor array.

In order to achieve this object, there is provided a TFT array comprising: a plurality of pixel electrodes arranged in a matrix on an insulative substrate; a plurality of thin film transistors connected respectively to the pixel electrodes; a plurality of address lines connected to a plurality of control electrodes of the thin film transistors; and a plurality of data lines arranged such a manner as to intersect the address lines, each data line being connected to a plurality of data input electrodes of the thin film transistors, wherein there are provided short-wiring formed on the outside of a display region on which the pixel electrodes are arranged, and a two-terminal element for connecting the short-wiring to at least two lines of the address lines and the data lines, the two-terminal element having non-linear resistance characteristics defining voltage/current characteristics on the basis of a space charge limited current.

According to this invention, the thin film non-linear resistor element can be fabricated during the process of manufacturing the thin film transistor (TFT), without providing any special manufacturing step. Thus, the two-terminal element for preventing electrostatic breakdown can be formed without increasing the number of manufacturing steps of the TFT panel. Accordingly, the manufacturing yield of the TFTs can be increased.

In the present invention, it is desirable that the thin film non-linear resistor element be a double-injection type thin film non-linear resistor element in which holes and electrons are injected as carriers, or an electron-injection type thin film non-linear resistor element in which electrons are injected as a carrier. The double-injection type thin film non-linear resistor element is formed by connecting electrodes to both ends of an impurity-non-doped hydrogenated amorphous silicon film formed on the insulative substrate. The electron-injection type thin film non-linear resistor element is formed by connecting electrodes to both ends of an impurity-non-doped hydrogenated amorphous silicon film formed on the insulative substrate via an n-type amorphous silicon film doped with n-type impurities.

According to another aspect of the invention, there is provided a TFT array comprising: a plurality of pixel electrodes arranged in a matrix on an insulative substrate; a plurality of thin film transistors connected respectively to the pixel electrodes; a plurality of address lines connected to a plurality of control electrodes of the thin film transistors; and a plurality of data lines arranged such a manner as to intersect the address lines, each data line being connected to a plurality of data input electrodes of the thin film transistors, wherein there are provided a plurality of electrically insulated short means formed on the outside of a display region on the insulative substrate on which the pixel electrodes are arranged, said short means being connected to at least two of the address lines and the data lines.

According to this invention, the address lines are not connected to the data lines via the short-wiring. Thus, a high potential is not applied across the address line and data line owing to pulse-like static electricity which occurs most frequently during the TFT manufacturing process, and electrostatic breakdown can be prevented.

The above invention may have a structure wherein the short means is formed outside the display region and inside the terminal arrangement section of the address and data lines, and the short means is a two-terminal element having non-linear resistance characteristics and is connected to the address and data lines. In this case, the two-terminal element as the short means may be connected between two or more address lines and two or more data lines. Furthermore, the short-wiring may be formed outside the terminal arrangement region of the address and data lines. The short-wiring may be a two-terminal element having non-linear resistance characteristics formed outside the display region and inside the terminal arrangement region, and the two-terminal element may comprise first short-wiring connected to the address and data lines and second short-wiring formed outside the terminal arrangement region. Moreover, the short-means may comprise the short-wiring formed outside the display region and inside the terminal arrangement region and an outside short-wiring formed outside the terminal arrangement region and connecting the address lines and data lines.

According to still another aspect of the invention, there is provided a liquid crystal display element which comprises the TFT array; a second insulative substrate opposed to a surface of the first insulative substrate, on which the TFT array is provided, with a liquid crystal layer of a predetermined thickness being interposed, the second insulative substrate having a surface provided with opposed electrodes opposed to the pixel electrodes; and potential supply means, connected electrically to the short means, for applying a predetermined potential to the short means.

According to the liquid crystal display device of the invention, the potential of the short means is set at a predetermined level, and therefore a leak current flowing via the terminal element decreases, the power consumption decreases, the crosstalk decreases, and the display quality is enhanced.

In this display device, it is desirable that the potential applied to the short means be substantially equal to a potential applied to the opposed electrodes, be substantially equal to a lowest potential of the data signal supplied to the data lines, or be a potential which is synchronized with an inverted cycle of the data signal supplied to the data lines and is inverted with the same potential and the same or opposite phase with reference to a potential applied to the opposed electrodes formed on the second substrate.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a plan view showing a TFT array according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of a liquid crystal display (LCD) device using the TFT array of the present invention;

FIG. 3 is a partially enlarged view showing a part of the TFT array shown in FIG. 1;

FIG. 4 is a cross-sectional view of the TFT section taken along line IV--IV in FIG. 3;

FIG. 5 is a partially enlarged view showing a two-terminal element portion of the TFT array shown in FIG. 1;

FIG. 6 is a cross-sectional view of the two-terminal element portion taken along line VI--VI in FIG. 5;

FIG. 7 is a graph showing voltage/current characteristics of the two-terminal element shown in FIG. 6;

FIGS. 8A to 8E are views for illustrating sequential steps for manufacturing the TFT portion of the TFT array;

FIGS. 9A to 9E are views for illustrating sequential steps for manufacturing the two-terminal device portion of the TFT array;

FIGS. 10A to 10E are views for illustrating sequential steps for manufacturing the intersection portions of the short-wiring and address lines of the TFT array, and the connecting portions of the short-wiring;

FIG. 11 is a plan view showing a modification of the TFT array according to the first embodiment;

FIG. 12 is a partially enlarged view showing a two-terminal device portion of a TFT array according to a second embodiment of the invention;

FIG. 13 is a cross-sectional view of the two-terminal device portion taken along line XIII--XIII in FIG. 12;

FIG. 14 is a graph showing voltage/current characteristics of the two-terminal element shown in FIG. 13;

FIGS. 15A to 15E are views for illustrating sequential steps for manufacturing the two-terminal device portion of the TFT array;

FIG. 16 is a cross-sectional view showing a modification of the TFT portion according to the second embodiment of the invention;

FIG. 17 is a cross-sectional view showing a modification of the two-terminal device portion according to the second embodiment of the invention;

FIG. 18 is a plan view showing a TFT array according to a third embodiment of the invention;

FIG. 19 is a plan view showing a first modification of the TFT array according to the third embodiment;

FIG. 20 is a plan view showing a second modification of the TFT array according to the third embodiment;

FIG. 21 is a plan view showing a TFT array according to a fourth embodiment of the invention;

FIG. 22 is an enlarged plan view of a two-terminal device portion of the TFT array shown in FIG. 21;

FIG. 23 is a cross-sectional view of the two-terminal device portion taken along line XXIII--XXIII in FIG. 21;

FIG. 24 is a plan view showing a first modification of the TFT array according to the fourth embodiment;

FIG. 25 is a plan view showing a second modification of the TFT array according to the fourth embodiment;

FIG. 26 is a plan view showing a third modification of the TFT array according to the fourth embodiment;

FIG. 27 is a plan view showing a fourth modification of the TFT array according to the fourth embodiment;

FIG. 28 is a plan view showing a fifth modification of the TFT array according to the fourth embodiment;

FIG. 29 schematically shows the structure of an LCD apparatus according to a fifth embodiment of the invention;

FIG. 30 shows an equivalent circuit of the LCD apparatus, as viewed from the connection terminal of one data line;

FIGS. 31A to 31D show voltage waveforms of signals applied to the connection terminals of the lines LCD apparatus according to the fifth embodiment;

FIG. 32 is a plan view showing a conventional TFT array;

FIG. 33 is a plan view showing another conventional TFT array; and

FIG. 34 is a graph showing V-I characteristics of the two-terminal device used in the TFT array shown in FIG. 33.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

First Embodiment!

FIG. 1 is a plan view showing schematically the structure of a TFT array according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of an active matrix type liquid crystal display device (TFT-LCD) using the TFT array of the present invention.

As is shown in FIG. 2, a liquid crystal display (LCD) device using a TFT array according to the present invention comprises a TFT array 110 having an orientation film 20 formed to cover pixel electrodes 15 and TFTs 14, an opposed substrate 24 having an opposed electrode 22 facing the pixel electrodes 15 and an orientation film 23 covering the opposed electrode 22, a liquid crystal (LC) layer 21 with a predetermined thickness interposed between the opposed substrate 24 and TFT array 110, and a seal member for connecting the opposed substrate 24 and TFT array 110 with a predetermined gap therebetween.

The TFT array 110 has the following structure. Address lines 12 extending in rows and data lines 13 extending in columns are arranged on a transparent insulative substrate 11 such that the address lines 12 intersect the data lines 13 at right angles in a mutually insulated manner. TFTs 14 and pixel electrodes 15 are provided at intersections of the address lines 12 and data lines 13. The TFTs 14 are electrically connected to the lines 12 and 13, and the pixel electrodes 15 are electrically connected to the TFTs 14. The pixel electrodes 15 are arranged in rows and columns to form a display region.

A short-wiring or short-ring 16 made of an electrically conductive film is formed at an outer peripheral portion of the substrate 11. The address lines 12 and data lines 13 extend from the display region and electrically are connected to the short-wiring 16. The short-wiring 16 is cut out along broken lines 17 in FIG. 1, after the manufacturing process of the TFT array 110 has been completed or after the opposed substrate 24 facing the TFT array 110 has been bonded in the process of forming LC cells.

A short-wiring 18 surrounding the display region is formed in the vicinity of the outer edge of the display region and within the cut-out lines 17, such that the short-wiring 18 intersects the address lines 12 and data lines 13 in an insulated manner. A data-line connection portion 18a of the short-wiring 18, which is substantially parallel to the address lines 12, is formed on the substrate 11. An address-line connection portion 18b of the short-wiring 18, which is substantially parallel to the data lines 13, is formed on a gate insulating film 42 (described later). The short-wiring 18 is connected to the address lines 12 and data lines 13 by two-terminal elements (SCLC elements) 19 having non-linear voltage/current characteristics determined by a space charge limited current.

FIGS. 3 and 4 show the structures of the TFT 14 and pixel electrode 15 arranged at an intersection between the address lines 12 and data lines 13 of the TFT array 110. As shown in these figures, the address lines 12 intersect the data lines 13 via gate insulating films 42 and intersection insulating films 21 (described later). In the vicinity of the intersection, there is provided TFT 14 having a gate electrode 41 connected to the address line 12 and a drain electrode 46 connected to the data line 13. The source electrode of the TFT 14 is connected to the pixel electrode 15.

The TFT 14 has the following structure. The gate electrode 41 projecting from the address line 12 and the gate insulating film 42 covering the gate electrode 41 are formed on the substrate 11. A semiconductor film 43 of amorphous silicon is formed on the gate insulating film 42 at a location above the gate electrode 41, and thus a device region is formed. A blocking layer 44 of silicon nitride is formed on a channel portion of the semiconductor film 43. On one side of the semiconductor film 43, the drain electrode 46 is formed via an ohmic contact layer 45 made o