|
|
|
| United States Patent | 5504700 |
| Link to this page | http://www.wikipatents.com/5504700.html |
| Inventor(s) | Insley; Mark (Sunnyvale, CA);
Berry; Stephen (Littleton, MA);
Robinson; Jay C. (Sunnyvale, CA) |
| Abstract | The invention provides a method and apparatus for a memory device interface
between a memory device and a CPU as well as the dimensions of the memory
device. An electric circuit of the present invention has
one-hundred-twenty pins along the length of the housing. The housing of
the memory device has a length of approximately 85.6 mm and a width of
approximately 54.0 mm. The left and right side socket interface portions
of the housing have a minimum width of approximately 3.3 mm. The top
socket interface portion has a maximum thickness of approximately 3.5 mm
and a minimum height of approximately 3.0 mm. The bottom socket interface
portion has a maximum thickness of approximately 5.0 mm and a minimum
height of approximately 10.5 mm. Furthermore, the memory device interface
portion of the present invention includes at least one pin which provides
access to an address signal which indicates a memory array address
location within the memory device. The interface portion also includes at
least one pin which provides access to a data signal. Additionally, the
interface portion includes a row address strobe signal which indicates
that the address signal provided to the memory device is a row address,
similarly at least one pin providing access to a column address strobe
signal is included in the interface portion of the present invention. This
column address strobe signal indicates that the address signal provided to
the memory device is a column address. Further, at least one pin providing
access to a memory write signal and at least one pin providing access to a
memory output enable signal are included in the interface portion.
Finally, the memory device interface of the present invention provides
access to a power supply and to ground. |
|
|
 |
Title Information  |
|
|
|
|
|
|
| Publication Date |
April 2, 1996 |
|
|
|
|
|
| Filing Date |
February 22, 1994 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
 |
|
 |
Title Information |
|
|
|
References |
|
|
| *references marked with an asterisk below are user-added references |
 |
U.S. References |
|
|
|
 |
|
|
|
U.S. References |
|
|
|
Foreign References |
|
|
|
|
|
|
|
|
Foreign References |
|
|
|
Other References |
|
|
|
|
|
|
|
|
Other References |
|
|
|
|
|
|
|
References |
|
|
|
|
|
|
| Market Size |
|
Estimate the gross annual revenues of the relevant market
sector:
|
| | |
| |
|
|
| Market Share |
|
Estimate the percentage of the relevant market sector this invention will capture:
|
| | |
| |
|
|
| Reasonable Royalty |
|
What percentage of gross sales should the inventor or assignee be paid?
|
| | |
| |
|
|
|
Public's "Guesstimation" of Royalty Value
|
| Market Size | N/A | [No votes] | | x | Market Share | N/A | [No votes] | | x | Reasonable Royalty | N/A | [No votes] |
| | N/A | |
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Market Review |
|
|
|
Technical Review |
|
|
|
Claims |
|
|
What is claimed is:
1. A memory device for use with a computer system, said memory device
incorporating a word parity scheme and being capable of providing double
sided capacity, comprising:
a housing that has a length of about 85.6 mm and a width of about 54.0 mm;
an electric circuit within said housing and one-hundred-twenty pins which
extend along said length of said housing;
a first set of at least one pin providing access to at least one row
address strobe signal generated by the system that indicates to the memory
device that the row address is on an address line, only one of said at
least one row address strobe signal being necessary for selecting a side
of said memory device with said double sided capacity;
a first set of at least one pin providing the memory device with access to
ground followed in sequence by a first set of at least one pin providing
access to a predetermined signal generated by the memory device containing
data located in a predetermined memory array address location during a
read cycle and providing access to a predetermined signal generated by the
system containing data to be stored in said memory device during a write
cycle followed in sequence by a first set of at least one pin providing
access to a power supply from the system and accepted by the memory device
followed in sequence by a first set of at least one pin providing access
to a column address strobe signal generated by the system that indicates
to the memory device that a column address is on the address line;
a second set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
first set of at least one pin providing access to a memory output enable
signal generated by the system and accepted by the memory device followed
in sequence by a third set of at least one pin providing access to said
power supply;
a fourth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
second set of at least one pin providing access to a predetermined signal
generated by the memory device containing data located in a predetermined
memory array address location during a read cycle and provides access to a
predetermined signal generated by the system containing data to be stored
in said memory device during a write cycle followed in sequence by a
second set of at least one pin providing access to ground;
a third set of at least one pin providing the memory device with access to
ground followed in sequence by a first set of at least one pin providing
access to a signal generated by the system and accepted by the memory
device indicating a predetermined memory array address location within the
memory device to be accessed followed in sequence by a fourth set of at
least one pin providing access to ground;
a fifth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
first set of at least one pin providing access to a memory write enable
signal generated by the system and accepted by the memory device;
a sixth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
third set of at least one pin providing access to a predetermined signal
generated by the memory device containing data located in a predetermined
memory array address location during a read cycle and provides access to a
predetermined signal generated by the system containing data to be stored
in said memory device during a write cycle followed in sequence by a first
set of at least one pin providing access to parity data; and
a second set of at least one pin providing access to parity data signal
followed in sequence by a second set of at least one pin providing access
to a predetermined signal generated by the memory device containing data
located in a predetermined memory array address location during a read
cycle and provides access to a predetermined signal generated by the
system containing data to be stored in said memory device during a write
cycle followed in sequence by a seventh set of at least one pin providing
access to a power supply.
2. The memory device of claim 1 wherein said first set of at least one pin
providing access to a row address strobe signal further comprises:
pins 1 and 61 which provide access to a row address strobe signal generated
by the system and accepted by the memory device that indicate that a row
address is on the address line.
3. The memory device of claim 1 wherein said first set of at least one pin
providing the memory device with access to ground followed in sequence by
said first set of at least one pin providing access data signal located in
or to be stored in a predetermined memory array address location followed
in sequence by said first set of at least one pin providing access to said
power supply followed in sequence by said first set of at least one pin
providing access to a column address strobe signal further comprises:
pin 2 which provides the memory device with access to ground;
pins 3-10 which provide access to a signal generated by the memory device
that contains data located in a memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 11 which provides access to a power supply from the system and accepted
by the memory device;
pin 12 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line;
pin 36 which provide the memory device with access to ground;
pins 37-44 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pins 45-46 which provide access to a power supply from the computer and
accepted by the memory device;
pin 47 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line;
pin 62 which provides the memory device with access to ground;
pins 63-70 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 71 which provides access to a power supply from the computer and
accepted by the memory device; and
pin 72 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line.
4. The memory device of claim 1 wherein said second set of at least one pin
providing access to said power supply followed in sequence by said first
set of at least one pin providing access to a memory output enable signal
followed in sequence by said third set of at least one pin providing
access to said power supply further comprises:
pin 13 which provides access to a power supply from the system and accepted
by the memory device;
pin 14 which provides access to a memory output enable signal generated by
the system and accepted by the memory device; and
pin 15 which provides access to a power supply from the system and accepted
by the memory device.
5. The memory device of claim 1 wherein said fourth set of at least one pin
providing access to said power supply followed in sequence by said second
set of at least one pin providing access to a predetermined data signal
located in or to be stored in a predetermined memory array address
location followed in sequence by said second set of at least one pin
providing access to ground further comprises:
pin 16 which provides access to a power supply from the system and accepted
by the memory device;
pins 17-24 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 25 which provides the memory device with access to ground;
pin 50 which provides access to a power supply from the system and accepted
by the memory device;
pins 51-58 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 59 which provides the memory device with access to ground;
pins 108-110 which provide access to a power supply from the system and
accepted by the memory device;
pins 111-118 which provide access to a signal generated by the memory
device that contains data located in said memory array address location
during a read cycle and provide access to a signal generated by the system
that contains data to be stored in said memory device during a write
cycle; and
pin 119 which provides the memory device with access to ground.
6. The memory device of claim 1 wherein said third set of at least one pin
providing the memory device with access to ground followed in sequence by
said first set of at least one pin providing access to a predetermined
address signal followed in sequence by said fourth set of at least one pin
providing access to ground further comprises:
pin 26 which provides the memory device with access to ground;
pins 27-29 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed;
pins 30-31 which provide the memory device with access to ground;
pins 32-34 which provide access to a signal generated by the system and
accepted by the memory device that indicates to the memory device the
memory array address location within the memory device to be accessed;
pin 35 which provide the memory device with access to ground;
pin 86 which provides the memory device with access to ground;
pins 87-89 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed;
pins 90-91 which provide the memory device with access to ground;
pins 92-93 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed; and
pin 95 which provides the memory device with access to ground.
7. The memory device of claim 1 wherein said fifth set of at least one pin
providing access to said power supply followed in sequence by said first
set of at least one pin providing access to a memory write enable signal
further comprises:
pin 48 which provides access to a power supply from the system and accepted
by the memory device; and
pin 49 which provides access to a memory write enable signal generated by
the system and accepted by the memory device.
8. The memory device of claim 1 wherein said sixth set of at least one pin
providing access to said power supply followed in sequence by said third
set of at least one pin providing access to a predetermined data signal
located in or to be stored in a predetermined memory array address
location followed in sequence by said first set of at least one pin
providing access to parity data further comprises:
pins 73-76 which provide access to a power supply from the computer and
accepted by the memory device;
pins 77-84 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle; and
pin 85 which provides access to a parity bit.
9. The memory device of claim 1 wherein said second set of at least one pin
providing access to parity data followed in sequence by said second set of
at least one pin providing access to a predetermined data signal located
in or to be stored in a predetermined memory array address location
followed in sequence by said seventh set of at least one pin providing
access to said power supply further comprises:
pin 96 which provides access to a parity bit;
pins 97-104 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle; and
pins 105-106 which provide access to a power supply from the system and
accepted by the memory device.
10. The memory device of claim 1 further comprising:
pins 60, 94 and 120 which are left unconnected and reserved for future
expansion of the memory device.
11. The memory device of claim 1 wherein said housing has side socket
interface portions with a minimum width of approximately 3.3 mm.
12. The memory device of claim 1 wherein said housing has a top socket
interface portion with a maximum thickness of approximately 3.5 mm and a
minimum height of approximately 3.0 mm.
13. The memory device of claim 1 wherein said housing has a bottom socket
interface portion with a maximum thickness of approximately 5.0 mm and a
minimum height of approximately 10.5 mm.
14. The memory device of claim 1 further comprising a pin 107 which
provides access to a column address strobe signal generated by the system
that indicates to the memory device that a column address is on the
address line.
15. A method for providing a memory device for use with a computer system,
said memory device incorporating a word parity scheme and being capable of
providing double sided capacity, comprising the steps of:
providing a memory device interface for coupling to the computer system
including:
a housing that has a length of about 85.6 mm and a width of about 54.0 mm;
an electric circuit within said housing and one-hundred-twenty pins which
extend along said length of said housing;
a first set of at least one pin providing access to at least one row
address strobe signal generated by the system that indicates to the memory
device that the row address is on an address line, only one of said at
least one row address strobe signal being necessary for selecting a side
of said memory device with said double sided capacity;
a first set of at least one pin providing the memory device with access to
ground followed in sequence by a first set of at least one pin providing
access to a predetermined signal generated by the memory device containing
data located in a predetermined memory array address location during a
read cycle and providing access to a predetermined signal generated by the
system containing data to be stored in said memory device during a write
cycle followed in sequence by a first set of at least one pin providing
access to a power supply from the system and accepted by the memory device
followed in sequence by a first set of at least one pin providing access
to a column address strobe signal generated by the system that indicates
to the memory device that a column address is on the address line;
a second set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
first set of at least one pin providing access to a memory output enable
signal generated by the system and accepted by the memory device followed
in sequence by a third set of at least one pin providing access to said
power supply;
a fourth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
second set of at least one pin providing access to a predetermined signal
generated by the memory device containing data located in a predetermined
memory array address location during a read cycle and provides access to a
predetermined signal generated by the system containing data to be stored
in said memory device during a write cycle followed in sequence by a
second set of at least one pin providing access to ground;
a third set of at least one pin providing the memory device with access to
ground followed in sequence by a first set of at least one pin providing
access to a signal generated by the system and accepted by the memory
device indicating a predetermined memory array address location within the
memory device to be accessed followed in sequence by a fourth set of at
least one pin providing access to ground;
a fifth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
first set of at least one pin providing access to a memory write enable
signal generated by the system and accepted by the memory device;
a sixth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
third set of at least one pin providing access to a predetermined signal
generated by the memory device containing data located in a predetermined
memory array address location during a read cycle and provides access to a
predetermined signal generated by the system containing data to be stored
in said memory device during a write cycle followed in sequence by a first
set of at least one pin prodding access to parity data; and
a second set of at least one pin providing access to parity data signal
followed in sequence by a second set of at least one pin providing access
to a predetermined signal generated by the memory device containing data
located in a predetermined memory array address location during a read
cycle and provides access to a predetermined signal generated by the
system containing data to be stored in said memory device during a write
cycle followed in sequence by a seventh set of at least one pin providing
access to a power supply.
16. The method of claim 15 further comprising the steps of providing:
pins 1 and 61 which provide access to a row address strobe signal generated
by the system and accepted by the memory device that indicate that a row
address is on the address line;
pin 2 which provides the memory device with access to ground;
pins 3-10 which provide access to a signal generated by the memory device
that contains data located in a memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 11 which provides access to a power supply from the system and accepted
by the memory device;
pin 12 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line;
pin 36 which provide the memory device with access to ground;
pins 37-44 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pins 45-46 which provide access to a power supply from the computer and
accepted by the memory device;
pin 47 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line;
pin 62 which provides the memory device with access to ground;
pins 63-70 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 71 which provides access to a power supply from the computer and
accepted by the memory device;
pin 72 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line;
pin 13 which provides access to a power supply from the system and accepted
by the memory device;
pin 14 which provides access to a memory output enable signal generated by
the system and accepted by the memory device;
pin 15 which provides access to a power supply from the system and accepted
by the memory device;
pin 16 which provides access to a power supply from the system and accepted
by the memory device;
pins 17-24 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 25 which provides the memory device with access to ground;
pin 50 which provides access to a power supply from the system and accepted
by the memory device;
pins 51-58 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 59 which provides the memory device with access to ground;
pins 108-110 which provide access to a power supply from the system and
accepted by the memory device;
pins 111-118 which provide access to a signal generated by the memory
device that contains data located in said memory array address location
during a read cycle and provide access to a signal generated by the system
that contains data to be stored in said memory device during a write
cycle;
pin 119 which provides the memory device with access to ground;
pin 26 which provides the memory device with access to ground;
pins 27-29 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed;
pins 30-31 which provide the memory device with access to ground;
pins 32-34 which provide access to a signal generated by the system and
accepted by the memory device that indicates to the memory device the
memory array address location within the memory device to be accessed;
pin 35 which provide the memory device with access to ground;
pin 86 which provides the memory device with access to ground;
pins 87-89 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed;
pins 90-91 which provide the memory device with access to ground;
pins 92-93 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed;
pin 95 which provides the memory device with access to ground;
pin 48 which provides access to a power supply from the system and accepted
by the memory device;
pin 49 which provides access to a memory write enable signal generated by
the system and accepted by the memory device;
pins 73-76 which provide access to a power supply from the computer and
accepted by the memory device;
pins 77-84 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 85 which provides access to a parity bit;
pin 96 which provides access to a parity bit;
pins 97-104 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pins 105-106 which provide access to a power supply from the system and
accepted by the memory device;
pin 107 which provides access to a column address strobe signal generated
by the system that indicates to the memory device that a column address is
on the address line; and
pins 60, 94 and 120 which are left unconnected and reserved for future
expansion of the memory device.
17. The method of claim 15 wherein said housing has side socket interface
portions with a minimum width of approximately 3.3 mm.
18. The method of claim 15 wherein said housing has a top socket interface
portion with a maximum thickness of approximately 3.5 mm and a minimum
height of approximately 3.0 mm.
19. The method of claim 15 wherein said housing has a bottom socket
interface portion with a maximum thickness of approximately 5.0 mm and a
minimum height of approximately 10.5 mm.
20. A computer system comprising:
a) a memory device for coupling to the computer system, said memory device
incorporating a word parity scheme and being capable of providing double
sided capacity, and including:
a housing that has a length of about 85.6 mm and a width of about 54.0 mm;
and
an electric circuit within said housing and one-hundred-twenty pins which
extend along said length of said housing;
b) a CPU coupled to said memory device; and
c) an interface between said memory device and the computer system, said
interface including:
a first set of at least one pin providing access to at least one row
address strobe signal generated by the system that indicates to the memory
device that the row address is on an address line, only one of said at
least one row address strobe signal being necessary for selecting a side
of said memory device with said double sided capacity;
a first set of at least one pin providing the memory device with access to
ground followed in sequence by a first set of at least one pin providing
access to a predetermined signal generated by the memory device containing
data located in a predetermined memory array address location during a
read cycle and providing access to a predetermined signal generated by the
system containing data to be stored in said memory device during a write
cycle followed in sequence by a first set of at least one pin providing
access to a power supply from the system and accepted by the memory device
followed in sequence by a first set of at least one pin providing access
to a column address strobe signal generated by the system that indicates
to the memory device that a column address is on the address line;
a second set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
first set of at least one pin providing access to a memory output enable
signal generated by the system and accepted by the memory device followed
in sequence by a third set of at least one pin providing access to said
power supply;
a fourth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
second set of at least one pin providing access to a predetermined signal
generated by the memory device containing data located in a predetermined
memory array address location during a read cycle and provides access to a
predetermined signal generated by the system containing data to be stored
in said memory device during a write cycle followed in sequence by a
second set of at least one pin providing access to ground;
a third set of at least one pin providing the memory device with access to
ground followed in sequence by a first set of at least one pin providing
access to a signal generated by the system and accepted by the memory
device indicating a predetermined memory array address location within the
memory device to be accessed followed in sequence by a fourth set of at
least one pin providing access to ground;
a fifth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
first set of at least one pin providing access to a memory write enable
signal generated by the system and accepted by the memory device;
a sixth set of at least one pin providing access to said power supply from
the system and accepted by the memory device followed in sequence by a
third set of at least one pin providing access to a predetermined signal
generated by the memory device containing data located in a predetermined
memory array address location during a read cycle and provides access to a
predetermined signal generated by the system containing data to be stored
in said memory device during a write cycle followed in sequence by a first
set of at least one pin providing access to parity data; and
a second set of at least one pin providing access to parity data signal
followed in sequence by a second set of at least one pin providing access
to a predetermined signal generated by the memory device containing data
located in a predetermined memory array address location during a read
cycle and provides access to a predetermined signal generated by the
system containing data to be stored in said memory device during a write
cycle followed in sequence by a seventh set of at least one pin providing
access to a power supply.
21. The computer system of claim 20 wherein said first set of at least one
pin providing access to a row address strobe signal further comprises:
pins 1 and 61 which provide access to a row address strobe signal generated
by the system and accepted by the memory device that indicate that a row
address is on the address line.
22. The computer system of claim 20 wherein said first set of at least one
pin providing the memory device with access to ground followed in sequence
by said first set of at least one pin providing access data signal located
in or to be stored in a predetermined memory array address location
followed in sequence by said first set of at least one pin providing
access to said power supply followed in sequence by said first set of at
least one pin providing access to a column address strobe signal further
comprises:
pin 2 which provides the memory device with access to ground;
pins 3-10 which provide access to a signal generated by the memory device
that contains data located in a memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 11 which provides access to a power supply from the system and accepted
by the memory device;
pin 12 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line;
pin 36 which provide the memory device with access to ground;
pins 37-44 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pins 45-46 which provide access to a power supply from the computer and
accepted by the memory device;
pin 47 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line;
pin 62 which provides the memory device with access to ground;
pins 63-70 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 71 which provides access to a power supply from the computer and
accepted by the memory device; and
pin 72 which provides access to a column address strobe signal generated by
the system that indicates to the memory device that a column address is on
the address line.
23. The computer system of claim 20 wherein said second set of at least one
pin providing access to said power supply followed in sequence by said
first set of at least one pin providing access to a memory output enable
signal followed in sequence by said third set of at least one pin
providing access to said power supply further comprises:
pin 13 which provides access to a power supply from the system and accepted
by the memory device;
pin 14 which provides access to a memory output enable signal generated by
the system and accepted by the memory device; and
pin 15 which provides access to a power supply from the system and accepted
by the memory device.
24. The computer system of claim 20 wherein said fourth set of at least one
pin providing access to said power supply followed in sequence by said
second set of at least one pin providing access to a data signal located
in or to be stored in a predetermined memory array address location
followed in sequence by said second set of at least one pin providing
access to ground further comprises:
pin 16 which provides access to a power supply from the system and accepted
by the memory device;
pins 17-24 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 25 which provides the memory device with access to ground;
pin 50 which provides access to a power supply from the system and accepted
by the memory device;
pins 51-58 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pin 59 which provides the memory device with access to ground;
pins 108-110 which provide access to a power supply from the system and
accepted by the memory device;
pins 111-118 which provide access to a signal generated by the memory
device that contains data located in said memory array address location
during a read cycle and provide access to a signal generated by the system
that contains data to be stored in said memory device during a write
cycle; and
pin 119 which provides the memory device with access to ground.
25. The computer system of claim 20 wherein said third set of at least one
pin providing the memory device with access to ground followed in sequence
by said first set of at least one pin providing access to a predetermined
address signal followed in sequence by said fourth set of at least one pin
providing access to ground further comprises:
pin 26 which provides the memory device with access to ground;
pins 27-29 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed;
pins 30-31 which provide the memory device with access to ground;
pins 32-34 which provide access to a signal generated by the system and
accepted by the memory device that indicates to the memory device the
memory array address location within the memory device to be accessed;
pin 35 which provide the memory device with access to ground;
pin 86 which provides the memory device with access to ground;
pins 87-89 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed;
pins 90-91 which provide the memory device with access to ground;
pins 92-93 which provide access to a signal generated by the system and
accepted by the memory device indicating the memory array address location
within the memory device to be accessed; and
pin 95 which provides the memory device with access to ground.
26. The computer system of claim 20 wherein said fifth set of at least one
pin providing access to said power supply followed in sequence by said
first set of at least one pin providing access to a memory write enable
signal further comprises:
pin 48 which provides access to a power supply from the system and accepted
by the memory device; and
pin 49 which provides access to a memory write enable signal generated by
the system and accepted by the memory device.
27. The computer system of claim 20 wherein said sixth set of at least one
pin providing access to said power supply followed in sequence by said
third set of at least one pin providing access to a predetermined data
signal located in or to be stored in a predetermined memory array address
location followed in sequence by said first set of at least one pin
providing access to parity data further comprises:
pins 73-76 which provide access to a power supply from the computer and
accepted by the memory device;
pins 77-84 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle; and
pin 85 which provides access to a parity bit.
28. The computer system of claim 20 wherein said second set of at least one
pin providing access to parity data followed in sequence by said second
set of at least one pin providing access to a predetermined data signal
located in or to be stored in a predetermined memory array address
location followed in sequence by said seventh set of at least one pin
providing access to said power supply further comprises:
pin 96 which provides access to a parity bit;
pins 97-104 which provide access to a signal generated by the memory device
that contains data located in said memory array address location during a
read cycle and provide access to a signal generated by the system that
contains data to be stored in said memory device during a write cycle;
pins 105-106 which provide access to a power supply from the system and
accepted by the memory device; and
pin 107 which provides access to a column address strobe signal generated
by the system that indicates to the memory device that a column address is
on the address line.
29. The computer system of claim 20 further comprising:
pins 60, 94 and 120 which are left unconnected and reserved for future
expansion of the memory device.
30. The computer system of claim 20 wherein said housing has side socket
interface portions with a minimum width of approximately 3.3 mm.
31. The computer system of claim 20 wherein said housing has a top socket
interface portion with a maximum thickness of approximately 3.5 mm and a
minimum height of approximately 3.0 mm.
32. The computer system of claim 20 wherein said housing has a bottom
socket interface portion with a maximum thickness of approximately 5.0 mm
and a minimum height of approximately 10.5 mm. |
|
|
|
|
|
|
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a memory storage device interface between
a memory storage device and a computer, wherein the memory storage device
interface provides control signals and power to drive data between the
memory storage device and the computer with an increased throughput.
(2) Description of Related Art
The term single in-line memory module (SIMM) is used to describe a memory
module containing mostly memory chips and no other logic devices with the
possible exception of line drivers. SIMMs are small in size and are
typically added to an existing computer system through a mating socket. A
SIMM may use different types of memory devices in different
configurations. Typically, the memory device used is one of two types,
static RAM (SRAM), or dynamic RAM (DRAM).
Prior art SIMMs include SIMMs with only eight bits of data. In one version
of the SIMM, in order to add memory to a machine incrementally, a minimum
of four SIMMs at a time must be inserted into the machine. Another version
of a prior art SIMM is one which is double-sided seventy-two pin wide SIMM
containing thirty-two bits of data as opposed to only eight bits on the
previous version of the SIMM. To add memory to the machine, only one SIMM
needs to be inserted at a time as opposed to four SIMMs.
Standard SIMMs include PCMCIA cards (Personal Computer Memory Card
International Association) and currently two types of PCMCIA exist. One is
a memory card and the other is an IO-type card, such as serial ports and
modem cards. The data path for the PCMCIA is only sixteen bits wide. The
PCMCIA only supports either SRAM or pseudo-static RAM, and has a
sixty-eight pin interface.
With the desire for smaller computers and the ever prevailing need for
systems with high resolutions, it is desirable to have a SIMM with a
scaled-down dimensions with increased throughput. As will be described,
the present invention provides a method and apparatus for a SIMM with a
dimensions and interface portion which permits the SIMM to be inserted
into smaller computers with limited internal space as well as to permit
increased throughput for increased resolutions.
BRIEF SUMMARY OF THE INVENTION
The invention provides a method and apparatus for a memory device interface
between a memory device and a CPU as well as the dimensions of the memory
device. An electric circuit of the present invention has
one-hundred-twenty pins along the length of the housing. The housing of
the memory device has a length of approximately 85.6 mm and a width of
approximately 54.0 mm. The left and right side socket interface portions
of the housing have a minimum width of approximately 3.3 mm. The top
socket interface portion has a maximum thickness of approximately 3.5 mm
and a minimum height of approximately 3.0 mm. The bottom socket interface
portion has a maximum thickness of approximately 5.0 mm and a minimum
height of approximately 10.5 mm. Furthermore, the memory device interface
portion of the present invention includes at least one pin which provides
access to an address signal which indicates a memory array address
location within the memory device. The interface portion also includes at
least one pin which provides access to a data signal. Additionally, the
interface portion includes a row address strobe signal which indicates
that the address signal provided to the memory device is a row address,
similarly at least one pin providing access to a column address strobe
signal is included in the interface portion of the present invention. This
column address strobe signal indicates that the address signal provided to
the memory device is a column address. Further, at least one pin providing
access to a memory write signal and at least one pin providing access to a
| | |
