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BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor microcontrollers,
and more particularly to a self-programming microcontroller and method for
providing auto-programming of a microcontroller.
Microprocessors have evolved into complex instruments and machines which
require sophisticated, fast real-time control capability. Instead of using
large microprocessors of 16 or 32 bit capability along with interrupt
handler chips, programmable timer chips, ROM and RAM chips, the field has
gone to a single chip microcontroller in which all peripherals are
embedded on the same chip. Operation of the chip in an expanded mode
allows gaining the versatility of all on-chip features. Microcontrollers
are used in a wide diversity of present-day applications, with new
applications found almost daily. In hand-held instruments such as tiny
pocket-sized pagers, the microcontroller is responsive to received
characters to interpret them, produce a beep to notify the user of an
incoming message (or not if the user prefers an inaudible mode), and
poduces multiple mesages among the several last of those received on a
suitable display, typically an LCD. The microcontroller can also recall
from its internal memory any or all of the messages received in a given
period of time. The chip is also used in other instrumentation such as
meters and testers, capable of carrying out thousands of tests, each in a
millisecond or less.
Other applications include keyboard controllers for personal computers, in
which the microcontroller serves to offload many tasks formerly handled by
the processor. The chip continuously performs a series of diagnostic
procedures, and notifies the processor if it detects a problem. Among
other personal computer applications, microcontrollers are used in modems
for command interpretation and data transmission, in printer buffers for
high speed dumping of data in preparation for driving the printer at the
considerably lower speed at which the printer operates or for color
plotters, in color copiers, electronic typewriters, cable television
terminal equipment, lawn sprinkling controllers, credit card phone
equipment, automotive applications such as engine control modules,
antilock braking systems, automobile suspension control for desired
desination of ride softness or rigidity depending on user preference, and
a host of other applications used daily by industrial and consumer
customers.
A real time microcontroller is a microcomputer adapted to provide rapid
solutions to signal processing algorithms and other numerically intensive
computations, and, as well, to control real time events such as opening
and closing of relays, controlling the position and speed of a motor, and
others such as mentioned above. The central processing unit (CPU) of the
microcontroller operates in conjunction with certain peripherals for
purposes of such control. The peripherals may include devices such as
timers, signal ports, and baud rate generators, among others.
Customarily, prior art microcontrollers provide a special test mode to
program the on-chip program memory. This requires special schemes and
breadboards to enable the programming. In one prior art application, the
processor provides instructions to program itself, but the initial
programming of the self-programming instructions into memory nevertheless
requires a test mode.
SUMMARY OF THE INVENTION
Briefly, according to the invention, a simplified autoprogramming setup is
provided by means of an instruction to program the program memory of the
microcontroller. The microcontroller employs an auto-incrementing pointer
and an on-chip read-only memory (ROM) to store the program.
In essence, the processor of the microcontroller programs its own program
memory using the instruction. A pointer to the program memory is used by
the instruction to program the program memory, the pointer being capable
of autoincrementing for ease of stepping through the program memory. The
processor has an on-chip hard coded ROM with a program containing the
program memory programming instructions and other code to permit a
relatively simple autoprogramming setup.
Accordingly, it is a principal object of the present invention to provide a
system and method for auto-programming the program memory of a
microcontroller or processor.
A more specific object of the invention is to provide a microcontroller
having an on-chip unerasable memory used to store an instruction (and
other code) which initiates autoprogramming of an on-chip erasable program
memory of the microcontroller, and having an auto-incrementing pointer
which retrieves stored instructions of the desired program from an
off-chip location and loads them in the proper sequence into successive
address locations of the on-chip program memory.
Another object of the invention is to provide new and improved methods of
auto-programming microcontrollers.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and still further objects, features, aspect and attendant
advantages of the invention will become apparent from a consideration of
the following detailed description of the best mode of carrying out the
invention as presently contemplated, taken in conjunction with the
accompanying drawings in which:
FIG. 1 is a block diagram of the overall microcontroller chip incorporating
a preferred embodiment of the present invention;
FIG. 2 is a timing diagram illustrating the internal clocking scheme of the
microcontroller chip of FIG. 1;
FIG. 3 includes parts (a), (b) and (c) which are simplified block diagrams
of four (part (c) essentially defining two) different selectable
oscillator modes for the microcontroller chip of FIG. 1;
FIG. 4 is a timing diagram of the instruction fetch/execute pipeline in the
instruction cycle of the microcontroller chip of FIG. 1;
FIG. 5 is a memory map of the different operating modes of the
microcontroller chip of FIG. 1 which may be selected by chossing different
configurations of program memory;
FIG. 6 is a timing diagram for external program memory read and write;
FIG. 7 is an exemplary instruction decode map of the instruction set of the
microcontroller of FIG. 1, in mnemonic code;
FIG. 8 is a simplified block diagram of the on-chip reset circuit for the
microcontroller;
FIG. 9 is a timing diagram for a portion of the reset circuit of FIG. 8;
FIG. 10 is a preferred programming algorithm for use in auto-programming of
the microcontroller;
FIG. 11 is a simplified block diagram of the auto-programmer;
FIG. 12 is a timing diagram for the auto-programmer;
FIG. 13 is a table illustrating a test mode register for the
microcontroller; and
FIG. 14 is a table illustrating an organization of test latch emulating the
configuration fuses of the microcontroller to allow configuration of the
device without blowing the fuses.
DETAILED DESCRIPTION
The invention will be described in the context of a high performance
EPROM-based 8-bit microcontroller, but this is for purposes of example
only and not a limitation on the invention. In one suitable embodiment,
the microcontroller is fabricated in a CMOS semiconductor integrated
circuit chip which incorporates a central processing unit (CPU) having a
250 nanosecond (ns) instruction cycle, with an array of peripheral
resources for performing complex real-time control applications. Some of
the control applications for which such a device is suitable are described
in the above background section of this specification. The EPROM-based
device permits the user to develop and test code on a windowed ceramic
dual in-line package (ceramic DIP or, CERDIP) version, and having done so,
to move into production with a more cost effective, one-time programmable
(OTP) plastic DIP package version.
The features of the CPU in this exemplary embodiment preferably include
fully static design; 8 bit wide data path; 16 bit wide instructions (all,
single word); single cycle instructions in most instances, and two cycle
in the others; 250 ns cycle time at 16 megahertz (MHz) or higher
frequencies (e.g., 20 or 25 MHz); one megabit addressable program memory
space (in 64K.times.16 format); direct, indirect (with auto increment and
decrement), immediate and relative addressing; and four modes of operation
including microcontroller mode, secure (code protected) microcontroller
mode, extended microcontroller mode (both internal and external program
memory access), and microprocessor mode (external only program memory
access).
Preferably, a high level of device integration exists, including 32K
on-chip (i.e., embedded in the chip itself together with the
microcontroller) EPROM program memory, 2K of general purpose (SRAM)
registers, special function registers, hardware stack, external/internal
interrupts, I/O, timer/counters, capture registers, high speed PWM outputs
(10 bit, 15.6 KHz), and serial port (universal synchronous/asynchronous
receiver-transmitter, or USART) with baud rate generator.
Some of the features of the microcontroller embodiment to be described
herein to which at least some of the inventive aspects apply include a
watchdog timer with its own on-chip RC (resistance-capacitance) oscillator
for reliable operation; a power saving sleep mode; an on-chip power-up
timer and power on reset feature to reduce external circuitry; an on-chip
oscillator start-up timer; fuse selector oscillator options including
standard crystal oscillator, low frequency crystal oscillator, and RC
oscillator or external clocking; and fusible code protection.
The exemplary microcontroller in which the present invention is employed is
high performance, attributable in part to certain architectural features
found in conventional reduced instruction set calculation (RISC)
microprocessors. A modified Harvard architecture is used in which programs
and data are accessed from separate memories (referred to as program
memory and data memory, respectively). Bandwidth is improved over
traditional Von-Neuman architecture in which program and data are fetched
from the same memory. Separating the program and data memory also allows
instructions to be sized on other than 8-bit wide data words. 16-bit wide
op-codes are used in the microcontroller so that single word instructions
throughout are possible. A full 16-bit wide program memory access bus
fetches a 16 bit instruction in a single cycle, and a two-stage pipeline
overlaps fetch and execution of instructions. Consequently, all
instructions to be described below execute in a single cycle (250 ns @16
MHz) except for program branches and special instructions to transfer data
between program and data memories.
The microcontroller addresses 64K.times.16 program memory space and
integrates 2K.times.16 EPROM program memory on chip. Program execution can
be performed in a microcontroller mode which is internal only, or in a
microprocessor mode which is external only, or in an extended
microcontroller mode which is both internal and external. Data memory
locations (file registers), e.g., 256 such locations, are addressed
directly or indirectly by the microcontroller. Special function registers
including the program counter are mapped in the data memory. Use of a
substantially orthogonal (symmetrical) instruction set allows any
operation to be carried out on any register using any addressing mode.
The microcontroller will be described with reference to the block diagram
of a microcontroller chip 10 of FIG. 1, among other Figures, but it will
be helpful to the reader to first consider the internal clocking scheme of
the microcontroller is shown in FIG. 2. Microcontroller 10 can accept an
external clock (EC) input, among other oscillator options, on an OSC1 pin
12 of a circuit block or module 15 which incorporates timing and related
(reset and control) circuitry to be described in greater detail presently.
Internally, the clock input to the OSC1 pin is divided by four to generate
four phases (Q1, Q2, Q3 and Q4) each with a frequency equal to clock
input/4 and a duty cycle of 25%. If the EC input mode or an RC oscillator
mode (RC mode, described below) is selected, the OSC2 pin 13 of the
microcontroller chip provides a clock output (CLKOUT), which is high
during Q3, Q4 and low during Q1, Q2, as shown at the bottom of the timing
diagram of FIG. 2. While internal chip reset is active, the clock
generator holds the chip 10 (also sometimes referred to herein as the
device or the microcontroller) in the Q1 state, with the CLKOUT driven
low.
The function of the OSC1 pin 12 is as the external clock input in the EC
mode, and the oscillator input in the RC mode or crystal/resonator mode
(XT mode, described below). The OSC2 pin 13 functions as the oscillator
output. It connects to a crystal or resonator in the XT mode, and, in the
EC mode or RC mode, it outputs CLKOUT at one-fourth the frequency at OSC1,
and denotes the instruction cycle rate.
The oscillator options allow the device to be adapted to the particular
application in which it is to be used. For example, the RC oscillator
option reduces system cost, whereas an LF (low frequency)
crystal/resonator option saves power. The oscillator options or modes will
be described with reference to FIG. 3, which includes three circuit
diagrams labeled (a), (b) and (c) for the EC, RC and XT (or low frequency
crystal oscillator, LF) modes, respectively. Any one of these four
possible modes may be selected by appropriately defining the states of a
pair of EPROM configuration fuses FOSC1 and FOSC0 which are mapped in
predetermined address locations in program memory 17 (FIG. 1), and about
which additional details will be given later herein. In part (a) of FIG.
3, the OSC1 input is driven by CMOS drivers for an external clock, so that
pin 12 is a high impedance CMOS input. Circuit 15a performs a divide-by-4
function, and OSC2 pin 13 outputs CLKOUT. The preferred frequency range
for this mode is DC to 16 Mhz.
The RC mode depicted in part (b) requires an external resistance 18 and
capacitance 19 in series combination connected to power source V.sub.DD,
with the point of connection between the RC components connected to OSC1
pin 12, and the CLKOUT output at OSC2 pin 13. The internal components of
circuit 15b for this mode are as shown, the input SLEEP to gate 23 being
an instruction within the instruction set of the microcontroller, to be
described. While the RC mode is cost effective, it is subject to variation
of frequency of oscillation with power supply, temperature and from chip
to chip because of process variation. Accordingly, it is not an
appropriate choice for timing sensitive applications which require
accurate oscillator frequency. Frequency range for this mode is nominally
DC to 4 Mhz.
In the XT mode of part (c) of FIG. 3, a crystal or ceramic resonator 25 of
fundamental mode is connected across the OSC1 and OSC2 pins 12 and 13, and
the basic internal makeup of circuit 15c is as shown. If an overtone mode
crystal were used (e.g., above 20 Mhz), a tank circuit consisting of a
series LC circuit across capacitance C2 would be employed to attenuate the
gain at the fundamental frequency. The frequency range of XT is 0.2-16
Mhz. The LF mode is essentially the same as the XT mode, except that it is
used for crystals of frequency range 32 Khz to 200 Khz.
Referring to FIG. 4, which illustrates the instruction fetch/execute
pipeline, an instruction cycle in the microcontroller consists of phases
Q1, Q2, Q3 and Q4 of the internal clock. Instruction fetch and execute are
pipelined so that fetch occupies one instruction cycle and decode together
with execute occupy another instruction cycle (see lower portion of FIG.
4). The pipelining, however, effectively results in the execution of each
instruction in a single cycle, as shown in that portion of FIG. 4, with a
few exceptions (e.g., where an instruction causes program counter PC to
change, or instructions TABLRD and TABLWT are used) to be discussed
presently. A fetch cycle starts with the PC (generally shown at 30 of FIG.
1) incrementing in phase Q1. The address is presented on pins AD15-ADO
(labeled AD<15:0>, see 32 of FIG. 1) during Q2 for internal execution, and
the instruction is latched on the falling edge of Q4. The fetched
instruction is latched into an instruction register (IR) which is decoded
and executed during phases Q2, Q3 and Q4. Data memory (random access
memory, or RAM) 34 (FIG. 1) is read during Q2 (operand read) and written
during Q4 (destination write).
The portions of FIG. 4 designated ALE and OE (at 35 of FIG. 1) are at port
pins configurable as input or output in software, with TTL compatible
input (bits 0 and 1 of port E, respectively). In microprocessor mode or
extended microcontroller mode of operation (discussed below) of chip 10,
the ALE pin is the address latch enable output, and the address is latched
on the falling edge of the ALE output; and the OE pin is the output enable
control output (active low, as indicated by the bar above the
designation).
In addition to separate program and data memory space 17 and 34 (FIG. 1) in
the Harvard architecture employed by the microcontroller, a hardware stack
37 is provided which is separate from both. The data space in the
exemplary embodiment is 256 bytes in size, and is principally implemented
as static RAM. The remaining portion of the data space consists of special
function registers implemented as individual hardware registers.
In the exemplary embodiment, no data memory address bus or data bus is
brought outside the chip, and hence, data memory cannot be expanded
externally. If desired, however, data segments can be created in external
program memory. The 16 bit wide on-chip program memory 17 is addressed by
the 16 bit program counter 30 for instruction fetch, and by a 16 bit wide
table pointer register (TBLPTR) 38 for data move to and from data space.
In the exemplary embodiment, addressable program memory is 64K.times.16,
and the on-chip program memory is an EPROM array arranged 2K.times.16.
The microcontroller 10 may operate in any one of four different modes
having different program memory organization or configurations, which have
been referred to earlier herein. These are:
(1) A microcontroller mode, in which only internal execution is allowed
and, hence, only the on-chip program memory 17 is available. Any attempted
access to program memory beyond 2K automatically generates a "no
operation" (NOP) instruction. A set of EPROM fuses (configuration bits) is
used to select various options including these operating modes of the
device, the provision of code-security and write protection. The fuses, as
well as test memory used at the factory for testing the device, and boot
memory used to store programs used for programming and verification, are
accessible in this mode.
(2) A protected microcontroller mode, which is the same as the
microcontroller mode except that code protection is enabled, as will be
described presently.
(3) An extended microcontroller mode, in which on-chip program memory 17
(0-2K) and external memory (2K-64K) are available, but fuses, test memory
and boot memory are not accessible. Execution automatically switches to
external memory if the program memory address exceeds the highest address
available in the latter memory.
(4) A microprocessor mode, in which on-chip program memory 17 is not used,
and the entire 64K of external memory for programming is mapped
externally. Fuses, test memory and boot memory are not accessible in this
mode.
A memory map of the different modes is shown in FIG. 5. The protected
microcontroller mode is not shown because it is the same as the
microcontroller mode except as indicated above.
An external program memory interface used if external execution is selected
has ports C, D and E (see 32 and 35 of FIG. 1) configured as a system bus
for the external program memory access. Ports C and D together constitute
a 16 bit wide multiplexed address and data bus. Three bit E port outputs
control signals ALE (Address Latch Enable), OE (Output Enable) and WR
(Write Enable). External program memory read and write timings are shown
in FIG. 6. An external memory access cycle includes four oscillator cycles
(between rising edges of successive Q1's). During Q2, a 16 bit address is
presented on ports C and D, and ALE is asserted. The address output is
latched by the falling edge of ALE. In an instruction fetch or data read
cycle, OE is asserted during Q3 and Q4. The data is latched on the rising
edge of OE. One oscillator cycle separation between OE and address output
guarantees adequate time for external memories to shut off their output
drivers before the address is driven onto the bus. In a data write cycle
(only during TABLWT instruction), following address output during Q2, data
is driven onto the bus during Q3 and Q4. WR is asserted during Q4 and the
data output is valid both on its falling and rising edge.
The data memory 34 (FIG. 1) on the microcontroller chip is organized as
256.times.8, and is accessed via an internal 8 bit data bus 40 and an 8
bit data-memory-address bus 42 derived from the instruction register 45.
Addressing is done via direct addressing mode or through indirect
addressing mode using file select registers as pointer registers. All but
a few (e.g. TBLATH (table latch high byte), TBLATL (table latch low byte))
special function registers (such as W (accumulator), RTCC, program counter
and ports) are mapped in the data memory, and the remainder of the data
memory is implemented as static RAM. The watchdog timer and the stack
pointer, as well as TBLATH and TBLATL, are not addressable.
In the instruction set for the microcontroller, each instruction is a
single word, 16 bit s wide, and virtually all instructions are executed in
a single instruction cycle. The instruction set consists of 55
instructions, is highly orthogonal and is grouped into data move
operations, arithmetic and logical operations, bit manipulation
operations, program control operations and special control operations. The
orthogonal instruction set allows read and write of special function
registers, such as PC and status registers. The instructions, in mnemonic
code, and their descriptions are as follows (refer, also, to the
instruction decode map of FIG. 7).
ADDLW (Add literal to W): Contents of the W register 47 are added to the 8
bit literal field (constant data) "k" 49 and the result is placed in the W
register.
ADDWF (Add W to f): Add contents of W register 47 to data memory location
"f" (register file address). If "d" (destination select) is 0, result is
stored in W register. If "d" is 1, result is stored in data memory
location "f".
ADDWFC (Add W and Carry to f): Add the W register and the Carry Flag to
data memory location "f". If "d" is 0, the result is placed in the W
register. If "d" is 1, the result is placed in data memory location "f".
ANDLW (AND literal and W) : The contents of W register and AND'ed with the
eight bit literal "k". The result is placed in the W register.
ANDWF (AND W with f): AND the W register with data memory location "f". If
"d" is 0, the result is stored in the W register. If "d" is 1, the result
is stored in data memory location "f".
BCF (Bit Clear f): Bit "b" (bit address within 8-bit file register) in data
memory location "f" is reset to 0.
BSF (Bit Set f) : Bit "b" in data memory location "f" is set to 1.
BTFSC (Bit test, skip if clear): This can be one of the few two-cycle
instructions. If bit "b" in data memory location "f" is "0", then the next
instruction is skipped If bit "b" is "0", the next instruction, fetched
during the current instruction execution, is discarded and NOP (no
operation) is executed instead making this a 2-cycle instruction.
BTFSS (Bit test, skip if set): If bit "b" in data memory location "f" is
"1", then the next instruction, fetched during the current instruction
execution, is discarded and a NOP is executed instead making this a
2-cycle instruction.
BTG (Bit Toggle f): Bit "b" in data memory location "f" is inverted.
CALL (Subroutine Call): This is a 2-cycle instruction. Subroutine call
within 8K page. First, return address (PC+1) is pushed into the stack. The
thirteen bit value is loaded into PC bits <12:0>. Then the upper eight
bits of the PC is copied into PCLATH (program counter high holding latch).
CLRF (Clear f and Clear d): The contents of data memory location "f" are
set to 0. If "d" is "0"the contents of both data memory location "f" and W
register are set to "0". If "d" is "1", only contents of data memory
location "f" are set to "0".
CLRWDT (Clear Watchdog Timer): The watchdog timer (WDT) and the prescaler
of the WDT are reset. CPU status bits TO (tome-out) and PD (power-down)
are set.
COMF (Complement f): The contents of data memory location "f" are
complemented If "d" is "0", the result is stored in W. If "d" is "1", the
result is stored in data memory location "f".
CPFSEQ (Compare f with W, skip if f=W): If the contents of data memory
location "f" are equal to the contents of the W register, the next
instruction, fetched during the current instruction execution, is skipped
(discarded) and a NOP is executed instead, making this a 2-cycle
instruction.
CPFSGT (Computer f with @, skip if f>W): If the contents of data memory
location "f" are greater than the contents of the W register, the next
instruction, fetched during the current instruction execution, is skipped
(discarded) and a NOP is executed instead, making this a 2-cycle
instruction.
CPFSLT (Compare f with W, skip if f<W): If the contents of data memory
location "f" are less than the contents of the W register, the next
instruction, fetched during the current instruction execution, is skipped
(discarded) and a NOP is executed instead, making this a 2-cycle
instruction.
DAW (Decimal Adjust W Register): The eight bit value in the W register
resulting from the earlier addition of two variables (each in packed BCD
(binary coded decimal) format) is adjusted, and a correct packed BCD
result is produced If "d" is "0", the result is placed in the W register
and data memory location "f". If "d" is "1", the result is placed only in
data memory location "f".
DECF (Decrement f): Decrement data memory location "f". If "d" is "0", the
result is stored in the W register If "d" is "1", the result is stored in
data memory location "f".
DECFSZ (Decrement f, skip if 0): The contents of data memory location "f"
are decremented. If "d" is "0", the result is placed in the W register. If
"d" is "1", the result is placed in data memory location "f". If the
result is "0", the next instruction, which is already fetched, is skipped
by discarding, and a NOP is executed instead, making it a 2-cycle
instruction.
DCFSNZ (Decrement f, skip if not 0): The contents of data memory location
"f" are decremented. If "d" is "0", the result is placed in the W
register. If "d" is "1", the result is placed in data memory location "f".
If the result is not "0", the next instruction, fetched during the current
instruction execution, is discarded. A NOP is executed instead making this
a 2-cycle instruction.
GOTO (Unconditional Branch): This is a 2-cycle instruction. Allows an
unconditional branch anywhere within an 8K page boundary. The thirteen bit
immediate value is loaded into PC bits. Then the upper eight bits of PC
are loaded into PCLATH.
INCF (Increment f): The contents of data memory location "f" are
incremented. If "d" is "0", the result is placed in the W register. If "d"
is "1", the result is placed in data memory location "f".
INCFSZ (Increment f, skip if 0): The contents of data memory location "f"
are incremented. If "d" is "0", the result is placed in the W register. If
"d" is "1", the result is placed in data memory location "f". If the
result is "0", the next instruction, fetched during the current
instruction execution, is skipped "discarded" and a NOP is executed
instead, making this a 2-cycle instruction.
INFSNZ (Increment f, skip if not 0): The contents of data memory location
"f" are incremented. If "d" is "0", the result is placed in the W
register. If "d" is "1", the result is placed in data memory location "f".
If the result is not "0" the next instruction, fetched during the curr | | |
