A priority encoder-includes an encoder for coding an input consisting of a plurality of bits, selectors, respectively provided for bit input terminals of the encoder, for respectively receiving corresponding ones of a plurality of bits of an operand input, each of the selectors including a switch circuit to be controlled by an operand input bit, a carry line connected in series with the switch circuit and connected in series with all of the selectors, a first precharge circuit, connected to a carry line portion on one end side of the switch circuit, for precharging the carry line at a predetermined timing, a first detector which is controlled by an enable signal for designating upper bit priority and detects whether a potential of a carry line portion on an upper bit side of the switch circuit is at a discharge level, a second detector which is controlled by an enable signal for designating lower bit priority and detects whether a carry line portion on a lower bit side of the switch circuit is at a discharge level, and a third detector for detecting whether one of outputs from the first and second detectors and the operand input bit are both in an active state.
This application is a continuation of application Ser. No. 08/188,114 filed Jan. 28, 1994, now abandonded, which is a continuation of application Ser. No. 07/647,936, filed Jan. 30, 1991, now abandonded.
A priority encoder for encoding input data by scanning the input data in a predetermined direction, includes: a first voltage section for charging a plurality of output lines to a first voltage level; a plurality of switching elements connected to the plurality of the output lines, each of the plurality of switching elements being turned on in accordance with a value of the input data; and a second voltage section for charging a selected one of the plurality of output lines to a second voltage level different from the first voltage level, through the switching elements which are turned on.
There is disclosed, a converter for converting an input signal from one form to another includes a generator circuit for generating as a thermometer code a plurality of binary signals from the input signal. The converter includes one or more pseudo-majority gate circuits for correcting a broken thermometer code to be a corrected thermometer code. The corrected thermometer code is decoded to provide a digital code corresponding to the input signal. There may be more than one stage of pseudo-majority gate correction.
An encoder capable of making a processing time shorter, wherein the position of a first "1" bit seen from the MSB of digital data is output as a first bit encoded data and the second "1" bit is output as the second bit encoded data. A predetermined calculation is performed in parallel on the upper 8 bits of the digital data in the valid detector, the priority encoder, and the first valid bit mask unit, while a predetermined calculation is performed in parallel on the lower 8 bits in another priority encoder and another first valid bit mask unit.
A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.
One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by converting the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits. Next, the system converts the thermometer code into a one-hot code in which only one bit has a logical one value. Finally, the system converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.
