Self-aligned via and contact interconnect manufacturing method

Claims

What is claimed is:

1. A method of creating a vertical via interconnect between conductive layers in a semiconductor device comprising the following steps:

a. depositing a first conductive layer;

b. masking the first conductive layer with a topological etch mask having a mask pattern portion and a mask via portion, the mask via portion being situated above the mask pattern portion;

c. etching the first conductive layer to generate a first conductive pattern having integral via portions, the via portions having top surfaces, the first conductive pattern and via portions corresponding to the mask pattern portion and mask via portion, respectively;

d. depositing a dielectric layer over the first conductive pattern;

e. exposing the top surfaces of the via portions;

f. depositing a second conductive layer over said dielectric layer and the top surfaces of the via portions;

g. patterning said second conductive layer to create a second conductive pattern electrically connected to the first conductive pattern by the via portions.

2. The method of claim 1 wherein:

step (e) includes planarizing the dielectric.

3. The method of claim 1 wherein:

step (f) includes pre-cleaning the via portions to ensure ohmic contact between the second conductive layer and the via portions.

4. The method of claim 1 whereby:

etch of step (c) is selective to the topological etch mask and the first conductive pattern.

5. The method of claim 1 wherein:

the via portion of the topological etch mask of step (b) includes a bottom via barrier; and

step (c) further includes the substeps of

c.1. etching the conductive layer and topological etch mask to the bottom via barrier, the bottom via barrier being an etch stop preserving a remaining etch mask;

c.2. removing the bottom via barrier; and

c.3. etching the remaining conductive layer and stripping the remaining etch mask to create the first conductive pattern having via portions.

6. The method of claim 1 wherein:

step (b) includes forming the mask pattern portion over the first conductive layer, depositing a second conductive layer, and forming the via pattern portion over the second conductive layer.

7. The method of claim 1 wherein:

the via portion of the topological etch mask of step (b) includes a bottom via barrier; and

step (c) further includes the substeps of

c.1. etching the conductive layer and topological etch mask to the bottom via barrier, the bottom via barrier being an etch stop preserving a remaining etch mask; and

c.2. etching the remaining conductive layer and stripping the remaining etch mask including the bottom via barrier to create the first conductive pattern having via portions.

8. The method of claim 1, wherein step (a) further includes the substeps of:

a.1. depositing a first portion of the first conductive layer; and

a.2. depositing a second portion of the first conductive layer, wherein the second portion of the first conductive layer has etching properties differing from etching properties of the first portion of the first conductive layer.

9. The method of claim 1 wherein step (b) further includes the substeps of:

b.1. forming the mask pattern portion with a first mask material that has a first etch rate during etching; and

b.2. forming the mask via portion with a second mask material that has a second etch rate during etching, the second etch rate differing from the first etch rate.

10. A method of creating a vertical via interconnect in a semiconductor device comprising the following steps:

a. depositing a first conductive layer;

b. masking the first conductive layer with a topological etch mask having a mask pattern portion and a mask via portion, the mask via portion being situated above the mask pattern portion; and

c. etching the first conductive layer to generate a conductive structure having a conductive pattern and via portions, the via portions having top surfaces, the conductive pattern and via portions corresponding to the mask pattern portion and mask via portion, respectively.

11. The method of claim 10 further comprising the steps of;

d. depositing a dielectric layer over the conductive structure; and

e. exposing the top surfaces of the via portions.

12. A method of creating a vertical contact interconnect between a first conductive layer and a substrate layer in a semiconductor device comprising the following steps:

a. depositing a conductive contact layer on the substrate layer;

b. masking the conductive contact layer with a topological etch mask having a mask pattern portion and a mask contact portion, the mask contact portion being situated above the mask pattern portion;

c. etching the conductive contact layer to generate a conductive structure having a conductive pattern and contact portions, the contact portions having top surfaces, the conductive pattern and contact portions corresponding to the mask pattern portion and mask contact portion, respectively;

d. depositing a dielectric layer over the conductive structure;

e. exposing the top surfaces of the contact portions;

f. depositing a first conductive layer over the dielectric layer and the top surfaces of the contact portions; and

g. patterning the first conductive layer to create the first conductive layer electrically connected to the substrate layer by the conductive structure.

13. The method of claim 12 wherein step (b) further includes the substeps of:

b.1. forming the mask pattern portion with a first mask material that has a first etch rate during etching; and

b.2. forming the mask contact portion with a second mask material that has a second etch rate during etching.

14. The method of claim 12, wherein step (a) further includes the substeps of:

a.1. depositing a first portion of the conductive contact layer; and

a.2. depositing a second portion of the conductive contact layer, wherein the second portion of the conductive contact layer has etching properties differing from etching properties of the first portion of the conductive contact layer.

15. The method of claim 12 wherein:

the mask contact portion of the topological etch mask of step (b) includes a bottom contact barrier; and

step (c) further includes the substeps of

c.1. etching the conductive contact layer and topological etch mask to the bottom contact barrier, the bottom contact barrier being an etch stop preserving a remaining etch mask; and

c.2. etching the remaining conductive contact layer and stripping the remaining topological etch mask including the bottom contact barrier to create the conductive structure.

16. The method of claim 12 wherein:

the mask contact portion of the topological etch mask of step (b) includes a bottom contact barrier; and

step (c) further includes the substeps of

c.1. etching the conductive contact layer and topological etch mask to the bottom contact barrier, the bottom contact barrier being an etch stop preserving a remaining etch mask;

c.2. removing the bottom contact barrier; and

c.3. etching the remaining conductive layer and stripping the remaining topological etch mask to create the conductive structure.

17. The method of claim 12 wherein:

step (b) includes forming the mask pattern portion over the conductive contact layer, depositing a second conductive contact layer, and forming the mask contact portion over the second conductive contact layer.

18. A method of creating a vertical contact from a substrate layer, the method comprising the following steps:

a. depositing a conductive contact layer on the substrate layer;

b. masking the conductive contact layer with a topological etch mask having a mask pattern portion and a mask contact portion, the mask contact portion being situated above the mask pattern portion; and

c. etching the conductive contact layer to generate a conductive structure having a conductive pattern and contact portions, the contact portions having top surfaces, the conductive pattern and contact portions corresponding to the mask pattern portion and mask contact portions, respectively.

19. The method of claim 18 further comprising the steps of:

d. depositing a dielectric layer on the conductive structure; and

e. exposing the top surfaces of the contact portions.

20. The method of claim 19 wherein:

step (e) includes planarizing the dielectric.

21. The method of claim 20 wherein:

planarizing the dielectric includes chemical-mechanical polishing the dielectric.

22. The method of claim 19 further comprising the step of:

f. pre-cleaning the contact portions to ensure ohmic contact between a subsequently deposed conductive layer and the contact portions.

23. A method of creating a vertical via interconnect in a semiconductor device comprising the following steps:

a. depositing a first conductive layer;

b. masking the first conductive layer with a topological etch mask having a mask pattern portion and a mask via portion, a portion of the mask pattern portion being situated above the mask via portion; and

c. etching the first conductive layer to generate a first conductive pattern having integral via portions, the via portions having top surfaces, the first conductive pattern and via portions corresponding to the mask pattern portion and mask via portion, respectively.

24. The method of claim 23 further comprising the steps of:

d. depositing a dielectric layer over the first conductive pattern; and

e. exposing the top surfaces of the via portions.

25. The method of claim 24 wherein:

step (e) includes planarizing the dielectric.

26. The method of claim 25 wherein:

planarizing the dielectric includes chemical-mechanical polishing the dielectric.

27. The method of claim 24 further comprising the steps of:

f. depositing a second conductive layer over said dielectric layer and the top surfaces of the via portions;

g. patterning said second conductive layer to create a second conductive pattern electrically connected to the first conductive pattern by the via portions.

28. The method of claim 27 wherein:

step (f) includes pre-cleaning the via portions to ensure ohmic contact between the second conductive layer and the via portions.

29. The method of claim 23 wherein step (b) further includes the substeps of:

b.1. forming the mask pattern portion with a first mask material that has a first etch rate during etching; and

b.2. forming the mask via portion with a second mask material that has a second etch rate during etching.

30. The method of claim 23, wherein step (a) further includes the substeps of:

a.1. depositing a first portion of the first conductive layer; and

a.2. depositing a second portion of the first conductive layer, wherein the second portion of the conductive layer has etching properties differing from etching properties of the first conductive layer.

31. The method of claim 23 wherein:

the via portion of the topological etch mask of step (b) includes a bottom via barrier; and

step (c) further includes the substeps of

c.1. etching the conductive layer and topological etch mask to the bottom via barrier, the bottom via barrier being an etch stop preserving a remaining etch mask;

c.2. removing the bottom via barrier; and

c.3. etching the remaining conductive layer and stripping the remaining topological etch mask to create the first conductive pattern having via portions.

32. The method of claim 23 wherein:

the via portion of the topological etch mask of step (b) includes a bottom via barrier; and

step (c) further includes the substeps of

c.1. etching the conductive layer and topological etch mask to the bottom via barrier, the bottom via barrier being an etch stop preserving a remaining etch mask; and

c.2. etching the remaining conductive layer and stripping the remaining topological etch mask including the bottom via barrier to create the first conductive pattern having via portions.

33. A method of creating a vertical contact interconnect between a first conductive layer and a substrate layer in a semiconductor device comprising the following steps:

a. depositing a conductive contact layer on the substrate layer;

b. masking the conductive contact layer with a topological etch mask having a mask pattern portion and a mask contact portion, a portion of the mask pattern portion being situated above the mask via portion;

c. etching the conductive contact layer to generate a conductive structure having a conductive pattern and contact portions, the contact portions having top surfaces, the conductive pattern and contact portions corresponding to the mask pattern portion and mask contact portion, respectively;

d. depositing a dielectric layer over the conductive structure;

e. exposing the top surfaces of the contact portions;

f. depositing a first conductive layer over the dielectric layer and the top surfaces of the contact portions; and

g. patterning the first conductive layer to create the first conductive layer electrically connected to the substrate layer by the conductive structure.

34. The method of claim 33 wherein step (b) further includes the substeps of:

b.1. forming the mask pattern portion with a first mask material that has a first etch rate during etching; and

b.2. forming the mask contact portion with a second mask material that has a second etch rate during etching.

35. The method of claim 33, wherein step (a) further includes the substeps of:

a.1. depositing a first portion of the conductive contact layer; and

a.2. depositing a second portion of the conductive contact layer, wherein the second portion of the conductive contact layer has etching properties differing from etching properties of the first portion of the conductive contact layer.

36. The method of claim 33 wherein:

the mask contact portion of the topological etch mask of step (b) includes a bottom contact barrier; and

step (c) further includes the substeps of

c.1. etching the conductive contact layer and topological etch mask to the bottom contact barrier, the bottom contact barrier being an etch stop preserving a remaining etch mask; and

c.2. etching the remaining conductive contact layer and stripping the remaining etch mask including the bottom contact barrier to create the conductive structure.

37. The method of claim 33 wherein:

the mask contact portion of the topological etch mask of step (b) includes a bottom contact barrier; and

step (c) further includes the substeps of

c.1. etching the conductive contact layer and topological etch mask to the bottom contact barrier, the bottom contact barrier being an etch stop preserving a remaining etch mask;

c.2. removing the bottom contact barrier; and

c.3. etching the remaining conductive layer and stripping the remaining etch mask to create the conductive structure.

38. The method of claim 33 wherein:

step (b) includes forming the mask pattern portion over the conductive contact layer, depositing a second conductive contact layer, and forming the mask contact portion over the second conductive contact layer.

39. A method of creating a vertical contact from a substrate layer, the method comprising the following steps:

a. depositing a conductive contact layer on the substrate layer;

b. masking the conductive contact layer with a topological etch mask having a mask pattern portion and a mask contact portion, a portion of the mask pattern portion being situated above the mask via portion; and

c. etching the conductive contact layer to generate a conductive structure having a conductive pattern and contact portions, the contact portions having top surfaces, the conductive pattern and contact portions corresponding to the mask pattern portion and mask contact portions, respectively.

40. The method of claim 39 further comprising the steps of:

d. depositing a dielectric layer over the conductive structure; and

e. exposing the top surfaces of the contact portions.

41. The method of claim 40 wherein:

step (e) includes planarizing the dielectric.

42. The method of claim 41 wherein:

planarizing the dielectric includes chemical-mechanical polishing the dielectric.

43. The method of claim 40 further comprising the step of:

f. pre-cleaning the contact portions to ensure ohmic contact between a subsequently deposed conductive layer and the contact portions.

44. A method of creating a vertical via interconnect in a semiconductor device comprising the following steps:

a. depositing a first conductive layer having a vertical thickness;

b. masking said first conductive layer with a via mask, said via mask corresponding to desired via structures;

c. masking said first conductive layer and the via mask with a pattern mask;

d. etching said first conductive layer through the pattern mask to remove a portion of the vertical thickness of the first conductive layer to form a partially etched first conductive layer having upward extending pattern structures, said via mask covering at least a portion of said upward extending pattern structures; and

e. etching said first conductive layer and the via mask to forth a first conductive pattern including via structures extending upward therefrom, with each via structure having a top portion, the first conductive pattern and via structures corresponding to the pattern mask and via mask, respectively.

45. The method of claim 44, further comprising the steps of:

f. depositing a dielectric over said first conductive pattern; and

g. exposing the top portions of the via structures.

46. The method of claim 45, further comprising the steps of:

h. depositing a second conductive layer over said dielectric and the top portions of said via structures, the second conductive layer making conductive contact with the via structures; and

i. patterning said second conductive layer to create a second pattern electrically connected to the first pattern by the via structures.

47. The method of claim 44 wherein:

step (a) includes depositing a multilayered first conductive layer having a pattern portion and a via portion, the via portion situated over the pattern portion;

step (d) includes an etch that is selective to the via portion and not selective to the pattern portion, the pattern portion being an etch stop for the via etch; and

step (e) includes etching the pattern portion with an etch that is selective to the pattern portion.

48. The method of claim 44 wherein:

step (a) includes depositing a first conductive layer that includes a barrier layer dividing said first conductive layer into a lower pattern portion and an upper via portion; and

step (d) includes etching the first conductive layer to the barrier layer, the barrier layer functioning as an etch stop, said etching creating exposed barrier layer portions and unexposed barrier layer portions, the unexposed barrier layer portions being portions of the barrier layer covered by the pattern structures, the exposed barrier layer portions being subsequently stripped.

49. The method of claim 44 wherein:

step (b) includes using a masking material formed by photolithography and etching techniques.

50. The method of claim 44 wherein:

the etch of step (d) is an isotropic etch.

51. The method of claim 44 wherein:

the etch of step (d) is an-isotropic etch.

52. The method of claim 44 wherein:

step (c) further includes removing portions of the via mask not covered by the pattern mask.

TECHNICAL FIELD

The present invention relates to semiconductor device manufacturing, and more particularly, to an improved method of manufacturing via structures for providing vertical interconnects in multi-layer metallization designs.

BACKGROUND ART

Semiconductor processing has resulted in increasingly complex and powerful integrated circuits. By scaling down device size and employing improved materials, circuit power consumption continues to be reduced and operating speeds increased.

Large scale integrated circuits are now commonly utilizing multilevel metallization schemes involving two or more patterned conductive layers, each conductive layer being separated by insulation layers. The conductive layers are connected by vertically extending via structures. The combination of conductive layers and via structures creates the "wiring pattern" for the integrated circuit.

Prior art methods accomplish vertical, conductive interconnects between metallization layers using by depositing metal into an etched hole. These methods typically begin with the deposition of the first metallization layer. The first metallization layer is patterned, typically by creating an etch mask using photolithographic techniques, and subsequently etching the first metallization layer. The etch mask is stripped and the patterned layer is covered with a deposited dielectric. Via holes are then etched through the dielectric layer to the first metallization layer and filled with a conductive material. Prior art methods accomplish this step by a number of different methods. One prior art method involves depositing a first conductive layer over the dielectric layer and into the hole. The resulting structure includes a first metal line, a via hole and a second metal line that extends into the via hole. Unfortunately, the depth of via holes can result in poor step coverage, particularly at the bottom of the via hole. The lack of adequate step coverage leads to high resistance or "opens" between the metal layers, which can degrade circuit performance.

When manufacturing metallization patterns of very small geometries, structures using via holes to electrically connect a top and bottom conductive pattern also have the drawback of requiring an overlay. An overlay is a widening of the lower conductive pattern where a via hole is anticipated, to ensure the via hole will be properly aligned with the lower conductive layer. Overlays reduce the minimum packing density of patterns by forcing greater spaces between adjacent lines in a conductive pattern.

Another method of providing a conductive via structure between metallization layers is discussed in U.S. Pat. No. 5,202,579 issued to Fuji et al. Similar to the first prior art method described above, the '579 patent describes a process of depositing a tungsten film and subsequently etching back that film to produce a buried tungsten plug. The '579 patent, due to the reactivity between aluminum and tungsten, requires a complex sandwich layer structure of titanium and titanium nitride, tungsten, and then a second titanium and titanium nitride layer. Such complex metallization schemes can increases process complexity and processing time.

A third prior art method is taught in U.S. Pat. No. 5,192,713 issued to Yusuke Harada. The '713 patent utilizes a selective chemical vapor deposition (CVD) process to deposit tungsten in a via hole while doping another via hole with arsenic to retard the formation of a tungsten plug. The selective tungsten CVD process requires a particular types of substrate, typically polysilicon, and often requires an entire deposition system dedicated solely to depositing tungsten. This can increase processing time and be a costly method of creating viable via structures between metallization layers.

None of the prior an addresses the need for a simple via structure and contact manufacturing process that produces repeatable via structures having low resistance and that accomplishes these ends without excessive equipment costs.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a via structure and contact manufacturing process that produces via structures having improved resistance between conductive layers.

It is another object of the present invention to provide a via structure and contact manufacturing process that does not require a via hole etch process step.

It is yet another object of the present invention to provide a via structure and contact manufacturing process that does not require a via hole filling process step.

Yet another object of the present invention is to provide a via structure and contact manufacturing process that eliminates the need for specialized via deposition equipment.

Briefly, the preferred embodiment of the present invention is a via structure and contact manufacturing process for integrated circuits having multi-layer metallization schemes. The process creates an integral via structure that connects a first conductive pattern with a second conductive pattern. The interconnect and contact manufacturing process includes the general steps of creating a first conductive pattern with integrally formed via structures, depositing and planarizing a insulative interlayer over the first conductive pattern, and creating a second conductive pattern.

In the preferred embodiment, the creation of the first conductive pattern includes depositing a first conductive layer having a uniform vertical thickness and placing a via etch mask on the first conductive layer. The via etch mask has a number of via mask portions at desired via structure positions. The first conductive layer is partially etched, and the via masks result in a partially etched first conductive layer with upward extending via structures. A first pattern etch mask is then placed on the partially etched first conductive layer, including the via structures, and a first pattern etch is applied. The first pattern etch etches through the exposed portions of the first conductive layer and creates the first conductive pattern.

Once the first conductive pattern has been created an insulative interlayer is deposited over the first conductive pattern, including the via structures. The insulative interlayer is then planarized, bringing the top of the interlayer level with the via structures. This results in an interlayer top surface that includes exposed via structures.

A second conductive layer is deposited over the insulative interlayer and makes conductive contact with the via structures. A second pattern mask is created on the second conductive layer and the second conductive layer given a second pattern etch. The resulting second conductive pattern is now conductively connected to the first conductive pattern by the integrally formed via structures.

An advantage of the present invention is that it provides a via structure and contact manufacturing process for creating self aligned via structure.

Yet another object of the present invention is that it reduces the number of process steps necessary to create a vertical interconnection between horizontal conductive layers.

Still another advantage of the present invention is that it provides a process for simultaneously forming via structures with a metallization pattern.

Yet another advantage of the present invention is that it provides a via structure and contact manufacturing process that can be implemented to create multi-level metallization schemes.

Another advantage of the present invention is that it provides a via structure and contact manufacturing process that eliminates the problems created by redeposition of dielectric within via holes and contact holes during via etch and contact etch.

Yet another advantage of the present invention is that it provides a via structure and contact manufacturing process that eliminates the need for a pre-metal deposition via hole and contact hole cleaning step.

Another advantage of the present invention is that it eliminates plasma induced damage created by a via hole and contact hole etch.

Yet another advantage of the present invention is that overlay is not needed around the via and contact structures.

These and other objects and advantages of the present invention will become clear to those skilled in the art in view of the description of the best presently known mode of carrying out the invention and the industrial applicability of the preferred embodiment as described hereto and as illustrated in the several figures of the drawing.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1A-1B is a flow chart setting forth the process of the preferred embodiment of the present invention;

FIGS. 2A-2M are cross sectional views illustrating, sequentially, a portion of an integrated circuit manufactured with the preferred embodiment of the present invention;

FIGS. 3A and 3B illustrate a variation of the preferred embodiment employing a two layer first conductive layer;

FIGS. 4A-4C illustrate a variation of the preferred embodiment employing a first conductive layer having a barrier layer therein;

FIGS. 5A-5C illustrate an alternate embodiment of the present invention;

FIGS. 6A-6D illustrate a variation of the alternate embodiment of the present invention using an mask etch barrier;

FIGS. 7A-7C illustrate a variation of the alternate embodiment of the present invention using two different mask materials;

FIGS. 8A-8G illustrate a second alternate embodiment of the present invention; and

FIGS. 9A-9E illustrate a contact interconnect manufactured with the present invention.

BEST MODE OF CARRYING OUT THE INVENTION

The best presently known mode for carrying out the present invention is a process for manufacturing via structures between conductive layers on a semiconductor device. The process uses metallization patterning techniques to etch self-aligned via structures, integral to the metallization pattern below.

The inventive process is repeatable with each subsequent conductive layer. The same general method of creating a via structure between a first conductive layer and a second conductive layer can be used to create an interconnect between a second conductive layer and a third conductive layer. Thus, the via structure and contact manufacturing process of the present invention can be employed to accomplish all the vertical connections on an integrated circuit. The preferred embodiment, as set forth below, repeats the process twice to create via structures between three metallization layers.

In the process of the present invention a first conductive layer is deposited and then patterned with vertically extending via structures in place. A dielectric interlayer is deposited and subsequently planarized so as to be level with the via structures. A second conductive layer is then deposited over the interlayer and patterned in the same manner as the first conductive layer. A second dielectric layer is deposited over the second conductive layer and then planarized. The process concludes with the deposition and patterning of a third conductive layer over the second dielectric. The resulting structure is a triple metal device having first via structures connecting the first conductive layer with the second conductive layer, and second via structures connecting the second conductive layer with the third conductive layer.

The best presently known mode for carrying out the present invention is shown as a series of steps in FIGS. 1A and 1B, and designated by the general reference character 10. The process of the present invention is divided into three general process sections, which include a first conductive layer patterning section 12, a first interlayer deposition and planarization section 14, a second conductive layer patterning section 16 a, second interlayer deposition and planarization section 18, and a third conductive layer patterning section 20. Each process section includes a number of specific process steps discussed in further detail below. FIGS. 2A-2M set forth sequential, partial, cross sectional views of an integrated circuit manufactured with the present invention. FIGS. 2A-2M will be referred to in conjunction with process steps set forth in FIGS. 1A and 1B.

A cross sectional view of an integrated circuit prior to the process of the present invention 10 is illustrated in FIG. 2A, and sets forth a semiconductor substrate 22, field oxide 24, MOS gate 26, a gate contact hole 28, and base dielectric layer 30.

As set forth in FIG. 1A, the first conductive layer patterning section 12 begins with a "determine first conductive layer thickness" step 32. A first conductive layer 34 is selected to have a total vertical thickness that includes a desired vertical thickness of a first metallization pattern and a desired via structure vertical thickness. Via structure and metallization dimensioning are determined by design rules of particular processes and are well known in the art.

Once the first conductive layer 34 thickness is determined, a "deposit first conductive layer" step 36 deposits a first conductive layer 34 over the base dielectric 30. As illustrated in FIG. 2B the first conductive layer 34 can be conceptualized as having a first via portion 38 and a first pattern portion 40. The first via portion 38 is a top layer of the first conductor 34 having a uniform vertical thickness corresponding to the desired vertical thickness of a first via structures. Correspondingly, the first pattern portion 40 is a layer below the first via portion 38 having a uniform vertical thickness corresponding to the desired first conductive pattern vertical thickness. It is understood, that in the preferred embodiment 10, the entire first conductive layer 34 is of uniform material, and the division of the first conductive layer 34 into the first via portion 38 and the first pattern portion 40 is, for the preferred embodiment 10, purely a conceptual one.

In the preferred embodiment 10, the first conductive layer 34 is aluminum deposited via evaporation methods. The base dielectric layer 30 is reflowed borophosphosilicate