A high speed analog signal sampling system. The system comprises a timing chain having a plurality of delay elements arranged in series and a sample rate multiplier having a delay lock control system responsive to the outputs of first, second and third parallel delay elements in the sample rate multiplier to control the delay of the second parallel delay element so that its strobe signal output occurs one-half the time between the strobe signal outputs of the first parallel delay element and the third parallel delay element. The first, second and third parallel delay elements are the first three parallel delay elements of the timing chain, and a control signal of the delay lock control system is used to adjust and control the amount of delay introduced by every other parallel delay element after the second parallel delay element. The second and third parallel delay elements straddle one of the series delay elements in the timing chain, while the first parallel delay element has the same input as the second parallel delay element. The delay lock control system employs a sampling circuit which samples the strobe signal output of the first parallel delay element in response to an output of the second parallel delay element and which samples the strobe signal output of the second parallel delay element in response to an output of the third delay element, and further employs a control circuit which filters the difference between those two sampled output signals and provides that filtered difference as the control signal.
A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.
The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits. In one exemplary method, the timing mismatch is detected by converting the sample and hold circuit output data to digital data and performing a fast Fourier transform thereon, and analyzing the resulting energy spectrum.
In accordance with the present invention, circuits are disclosed for use in implementing higher order sigma delta analog to digital conversion of narrowband signals with cascaded lower order circuit networks. The lower order circuit networks employ resonator circuits utilizing unit delay functional blocks to implement a specific transfer function. The unit delays are implemented utilizing sample and hold circuits operated by controlled switching of the circuit elements. In one embodiment, the resonator circuit includes a first sample and hold circuit for implementing a unit delay of corresponding input signals where the output of the first sample and hold circuit is coupled into a feedback loop with one or more additional sample and hold circuits for implementing a dual cascaded unit delay. The delayed signals from the feedback loop are then summed with the input signals at the input of the first sample and hold circuit. Advantageously, the present invention overcomes performance limitations of complex higher order sigma delta analog to digital converters that suffer from circuit nonidealities such as component mismatch, finite operational amplifier gain, bandwidth and design complexities associated with integrator based implementations. Alternate embodiments of the present invention include a switched capacitor based circuit for implementing the lower order delay function block based networks and a current copier or switched current approach. The switched capacitor circuit employs a first operational amplifier for inputting signals and summing with delayed samples of the input signals and a second operational amplifier coupled in a feedback loop with the first operational amplifier for implementing the delayed samples of the input signals. The switched current circuit employs a first current copier for sampling input signals and summing with a delay of the input signals. Second and third current copiers are used for implementing delayed sampling and holding for two separate signals output from the first current copier. The sampling, holding, delaying and summing are implemented with controlled switching in the circuits.
A method and apparatus for real-time derivation of precise digital clock edges and synchronous logic samples from a digital signal having a clock channel and at least one data channel acquires a plurality of temporally offset analog samples during each of a sequence of sample periods and from consecutive samples where there is a logic level transition estimates an edge time. From the edge times for the clock channel an offset is added and applied to the at least one data channel to determine the synchronous logic samples for the data channel at each offset clock edge time.
The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to establish a timing relationship between a hold signal and a clock signal for each of the plurality of sample and hold subcircuits which is generally the same. The established timing relationship reduces a timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises synchronizing a hold signal to a clock signal by modifying the hold signal for each of a plurality of sample and hold subcircuits within the sample and hold circuit and utilizing the modified hold signals in the sample and hold subcircuits, respectively.
