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Claims  |
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What is claimed is:
1. A parallel optical interconnect system responsive to a plurality of dc
NRZ data signals and an independent clock signal, said system comprising:
an optical transmitter comprising:
a signal transmission generator comprising a plurality of integrally formed
light emitters and a plurality of drive circuits, each of said light
emitters driven by at least one of said drive circuits, each of said drive
circuits having a signal input and at least one control input, said signal
inputs for receiving said data signals and said clock signal, and
a drive current regulator having at least one control output coupled to
said at least one control input of said drive circuits, said control
output responsive to eliminate output power fluctuation of said light
emitters;
an optical receiver comprising:
a signal receiver comprising a plurality of channel signal receivers each
having a photodetector and a plurality of signal processing circuits, each
of said photodetectors coupled to at least one of said signal processing
circuits, each of said signal processing circuits having a signal output;
and
an optical connector comprising:
a plurality of optical fibers aligned with said light emitters of said
signal transmission generator and said photodetectors of said optical
receiver.
2. The parallel optical interconnect system of claim 1 wherein said drive
circuits drive said light emitters with a high level drive current when
said data signals or said clock signal equate to a first logic level and
with a low level drive current when said data signals or said clock signal
equate to a second logic level; and wherein said at least one control
output of said drive current regulator forces said high level drive
current generated by said drive circuits to a level approximately equal to
a predetermined high level current reference.
3. The parallel optical interconnect system of claim 2 wherein said drive
current regulator further comprises: a light emitter, a drive circuit, a
photodetector, and a drive current compensator, said drive current
compensator having an output corresponding to said at least one control
output; wherein said light emitter is driven by said drive circuit, said
light emitter is optically coupled to said photodetector, said
photodetector generating a photocurrent output which is coupled to said
drive current compensator; and wherein said drive circuit has a control
input terminal coupled to said output of said drive current compensator.
4. The parallel optical interconnect system of claim 3 wherein said light
emitter of said drive current regulator is located on a substrate adjacent
to at least one of said light emitters of said signal transmission
generator used for transmission of said clock signal.
5. The parallel optical interconnect system of claim 2 wherein said drive
current regulator has a signal input, said signal input for receiving said
clock signal; and wherein said at least one control output is generated
using said clock signal.
6. The parallel optical interconnect system of claim 3 wherein said drive
current compensator of said drive current regulator maintains said
predetermined high level current reference and monitors high level current
generated by said photodetector of said drive current regulator, said
drive current compensator feeding back a compensation signal over said at
least one control output to maintain said high level drive current
generated by said drive circuit of said drive current regulator and said
drive circuits of said signal transmission generator at a level
approximately equal to said predetermined high level current reference.
7. The parallel optical interconnect system of claim 2 wherein said at
least one control input of said drive circuits comprises a high level
control input and a low level control input; and wherein said at least one
control output of said drive current regulator comprises a first control
output to force said high level drive current generated by said drive
circuits to approximate said predetermined high level current reference,
and a second control output to force said low level drive current
generated by said drive circuits to approximate a predetermined low level
current reference.
8. The parallel optical interconnect system of claim 7 wherein said drive
current regulator comprises:
a high level drive current monitor coupled to a photodetector, said
photodetector optically coupled to a light emitter, said light emitter
driven by a drive circuit, said drive circuit having a high level control
input, a low level control input and a signal input;
a low level drive current monitor coupled to a photodetector, said
photodetector optically coupled to a light emitter, said light emitter
driven by a drive circuit, said drive circuit having a high level control
input, a low level control input and a signal input; and
a drive level corrector coupled to outputs of said high level and said low
level drive current monitors, said drive level corrector generating a
first output corresponding to said first control output and a second
output corresponding to said second control output.
9. The parallel optical interconnect system of claim 8 wherein said signal
inputs of said drive circuits of said high level drive current monitor and
said low level drive current monitor are coupled to said clock signal.
10. The parallel optical interconnect system of claim 8 wherein said light
emitters coupled to said high level drive current monitor and said low
level drive current monitor are located on a substrate adjacent to at
least one of said light emitters of said signal transmission generator
used for transmission of said clock signal.
11. The parallel optical interconnect system of claim 1 wherein said
optical receiver further comprises a photocurrent averager, said clock
signal photocurrent averager generating a reference current output which
is coupled to each of said channel signal receivers.
12. The parallel optical interconnect system of claim 11 wherein said clock
signal photocurrent averager comprises a photodetector optically coupled
to one of said optical fibers over which said clock signal is optically
transmitted, said photodetector generating a clock signal photocurrent
proportional to said optically transmitted clock signal, said clock signal
photocurrent coupled to a capacitor which averages said clock signal
photocurrent, said averaged clock signal photocurrent corresponding to
said reference current output.
13. The parallel optical interconnect system of claim 12 wherein said clock
signal photocurrent and said averaged clock photocurrent are superimposed
on one another and input to a multi-stage signal amplifier.
14. The parallel optical interconnect system of claim 13 wherein said
multi-stage signal amplifier of said clock signal photocurrent averager
generates a retrieved clock signal output which corresponds to said
optically transmitted clock signal.
15. The parallel optical interconnect system of claim 12 wherein said
photodetectors of said signal processing circuits generate a photocurrent
output proportional to said data signals optically transmitted over said
optical fibers to which said photodetectors are coupled; and wherein each
of said signal processing circuits of said channel signal receivers
comprise a current mirror coupled to said reference current output, said
current mirror superimposing said reference current output on said
photodetector output to create a retrieved data signal output coupled to a
multi-stage amplifier.
16. The parallel optical interconnect system of claim 15 wherein said
current mirror of said channel signal receivers comprises a PMOS
transistor, the gate of which is coupled to said reference current output,
and an NFET mirror circuit coupled to the drain of said PMOS transistor
and said photodetector output.
17. The parallel optical interconnect system of claim 15 wherein each of
said channel signal receivers, in conjunction with its photodetector,
retrieves said optically transmitted data signals with reference to said
reference current output.
18. The parallel optical interconnect system of claim 15 wherein said
multi-stage signal amplifier comprises a trans-impedance amplifier, a post
amplifier/limiter, and a CMOS output amplifier, said three amplifiers
being connected to each other in series in the same order as listed.
19. The parallel optical interconnect system of claim 15 wherein each of
said multistage signal amplifiers is connected to one and only one of said
photodetector outputs.
20. The parallel optical interconnect system of claim 1 wherein the light
emitter used for transmitting said clock signal is more precisely timed
than those used for transmitting said dc NRZ data signals.
21. The parallel optical interconnect system of claim 1 wherein:
at least two of said light emitters are used for transmitting said clock
signal, said clock transmitting light emitters being interspersed among
said light emitters used for transmission of said data signals.
22. The parallel optical interconnect system of claim 1 wherein said light
emitters are vertical cavity surface emitting lasers (VCSELs).
23. The parallel optical interconnect system of claim 1 wherein said light
emitters are light emitting diodes (LEDs).
24. The parallel optical interconnect system of claim 1 wherein said light
emitters are resonant cavity enhanced light emitting diodes (RCLEDs).
25. The parallel optical interconnect system of claim 1 wherein said light
emitters are edge emitting semiconductor lasers.
26. An optical transmitter responsive to a plurality of dc NRZ data signals
and an independent clock signal, said transmitter comprising:
a signal transmission generator comprising a plurality of integrally formed
light emitters and a plurality of drive circuits, each of said light
emitters driven by at least one of said drive circuits, each of said drive
circuits having a signal input and at least one control input, said signal
inputs for receiving said data signals and said clock signal; and a drive
current regulator comprising at least one control output coupled to said
at least one control input of said drive circuits, said control output
responsive to eliminate output power fluctuation of said light emitters.
27. The optical transmitter of claim 26 wherein said light emitters are
vertical cavity surface emitting lasers (VCSELs).
28. The optical transmitter of claim 26 wherein said drive circuits drive
said light emitters with a high level drive current when said data signals
or said clock signal equal a first logic level and with a low level drive
current when said data signals or said clock signal are a second logic
level; and wherein said at least one control output of said drive current
regulator forces said high level drive current of said drive circuits to
approximate a predetermined high level current reference.
29. The optical transmitter of claim 28 wherein said drive current
regulator further comprises: a light emitter, a drive circuit, a
photodetector, and a drive current compensator having an output
corresponding to said at least one control output; wherein said light
emitter is driven by said drive circuit, said light emitter is optically
coupled to said photodetector, and said photodetector is electronically
coupled to said drive current compensator; and wherein said drive circuit
has a control input coupled to said output of said current compensator.
30. The optical transmitter of claim 29 wherein said light emitter of said
drive current regulator is located on a substrate adjacent to at least one
of said light emitters of said signal transmission generator used for
transmitting said clock signal.
31. The optical transmitter of claim 30 wherein said drive current
regulator has a signal input, said signal input for receiving said clock
signal.
32. The optical transmitter of claim 29 wherein said drive current
compensator of said drive current regulator maintains said predetermined
high level current reference and monitors high level current generated by
said photodetector of said drive current regulator, said drive current
compensator feeding back a compensation signal over its output to maintain
said high level drive current generated by said drive circuit of said
drive current regulator and said drive circuits of said signal
transmission generator at a level approximately equal to said
predetermined high level current reference.
33. An optical transmitter responsive to a plurality of dc NRZ data signals
and an independent clock signal, said transmitter comprising:
a signal transmission generator comprising a plurality of integrally formed
light emitters and a plurality of drive circuits, each of said light
emitters driven by at least one of said drive circuits, each of said drive
circuits having a signal input and first and second control inputs, said
signal inputs for receiving said data signals and said clock signal; and
a drive current regulator having first and second control outputs coupled
to said first and second control inputs of said drive circuits
respectively, said first control output responsive to eliminate output
power fluctuation of said light emitters when said signal inputs of said
drive circuits are at a first logic level, said second control output
responsive to eliminate output power fluctuation of said light emitters
when said signal inputs of said drive circuits are at a second logic
level.
34. The optical transmitter of claim 33 wherein said drive current
regulator comprises:
a high level drive current monitor coupled to a photodetector, said
photodetector optically coupled to a light emitter, said light emitter
driven by a drive circuit, said drive circuit having first and second
control inputs and a signal input;
a low level drive current monitor coupled to a photodetector, said
photodetector optically coupled to a light emitter, said light emitter
driven by a drive circuit, said drive circuit having first and second
control inputs and a signal input; and
a drive level corrector coupled to said high level and said low level drive
current monitors, said drive level corrector generating a first output
corresponding to said first control output and a second output
corresponding to said second control output, said first and said second
outputs coupled to said first and second control inputs respectively of
said drive circuits of said high and said low level current monitors.
35. The optical transmitter of claim 34 wherein said light emitters of said
high level drive current monitor and said low level drive current monitor
are located on a substrate adjacent to at least one of said light emitters
of said signal transmission generator used for transmitting said clock
signal.
36. The optical transmitter of claim 34 wherein said signal inputs of said
drive circuits of each high level drive current monitor and said low level
drive current monitor are coupled to said clock signal.
37. The optical transmitter of claim 33 wherein said drive circuits drive
said light emitters with a high level drive current when said data signals
or said clock signal equate to a first logic level and with a low level
drive current when said data signals or said clock signal equate to a
second logic level; and wherein said first control output of said drive
current regulator forces said high level drive current generated by said
drive circuits to a level approximately equal to a predetermined high
level current reference, and said second control output of said drive
current regulator forces said low level drive current generated by drive
circuits to a level approximately equal to a predetermined low level
current reference.
38. The optical transmitter of claim 33 wherein said light emitters are
vertical cavity surface emitting lasers (VCSELs).
39. An optical receiver responsive to a plurality of optically transmitted
dc NRZ data signals and an optically transmitted independent clock signal,
said optical receiver comprising:
a plurality of channel signal receivers each having a photodetector
optically coupled to one of said optically transmitted data signals or
said optically transmitted clock signal, said photodetector generating a
photocurrent output proportional to said optically coupled data or clock
signal, each of said plurality of channel signal receivers further
comprising a multi-stage signal amplifier having an input coupled to said
photocurrent output of said photodetector;
a photocurrent averager comprising a photodetector optically coupled to
said clock signal, said photocurrent averager generating a reference
current output based on said optically coupled clock signal; and
wherein said reference current output is superimposed on said photocurrent
output of said photodetector of each of said channel signal receivers.
40. The optical receiver of claim 39 wherein said photocurrent averager
further comprises a capacitor coupled to said photocurrent output of its
photodetector, said capacitor generating an averaged photocurrent output
from said photodetector output which corresponds to said reference current
output.
41. The optical receiver of claim 39 wherein said channel signal receivers
further comprise a current mirror coupled to said reference current
output, said current mirror superimposing said reference current output on
said photocurrent output.
42. The optical receiver of claim 39 wherein each of said multi-stage
signal amplifiers further comprises a trans-impedance amplifier having an
input coupled to said superimposed reference current output and said
photocurrent output, said trans-impedance amplifier having an output
coupled to the input of a post amplifier/limiter, said post amplifier
limiter having an output coupled to the input of a CMOS output amplifier.
43. The optical receiver of claim 39 wherein said photocurrent averager
produces said reference current output from said optically coupled clock
signal, and further retrieves said optically coupled clock signal using
said reference current output.
44. The optical receiver of claim 39 wherein said channel signal receivers
retrieve said optically coupled data or clock signals using said reference
current output.
45. A method of reducing or avoiding clock skew in a parallel optical
interconnect system responsive to a plurality of dc data signals and an
independent clock signal, said method comprising the steps of:
generating a plurality of optical data signals each corresponding to one of
said data signals, each of said optical data signals generated with a
light emitter having a first timing accuracy;
generating one or more optical clock signals corresponding to said clock
signal with one or more light emitters having a second timing accuracy
more precise than said first timing accuracy;
transmitting said optical data signals along with said one or more optical
clock signals;
receiving said optical data signals and said one or more optical clock
signals at a remote receiver;
averaging photocurrent of at least one of said one or more optical clock
signals to determine a reference current.
46. A method of transmitting and receiving a plurality of dc data signals
and an independent clock signal in a parallel optical interconnect system,
said method comprising the steps of:
generating an optical clock signal using a light emitter coupled to said
clock signal;
generating a plurality of optical data signals using light emitters coupled
to said plurality of data signals;
transmitting said optical clock signal along with said plurality of optical
data signals;
receiving said optical clock signal along with said plurality of optical
data signals;
monitoring said light emitter used to generate said optical clock signal
for emitted output power; and
adjusting output power of said light emitters based upon said monitored
emitted output power.
47. The method of claim 46 wherein said receiving step further comprises
the steps of:
averaging photocurrent of said received optical clock signal to determine a
reference current;
recovering said clock signal and said plurality of data signals from said
received optical clock signal and said received optical data signals
respectively based upon said current reference.
48. The method of reducing or avoiding clock skew in the parallel optical
interconnect system of claim 45 wherein an odd number of at least three
optical clock signals corresponding to said clock signal are generated
during said generating step; wherein said generated optical clock signals
are transmitted along with said generated optical data signals, and
wherein said method further comprises the step of:
comparing said clock signal recovered from each of said received optical
clock signals to one another to determine an appropriate timing edge for
data recovery. |
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Claims |
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Description |
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FIELD OF THE INVENTION
This invention relates to parallel optical interconnects and, more
particularly, to a control circuit for parallel optical interconnects.
BACKGROUND OF THE INVENTION
Unlike a conventional single laser (serial) transmission link which
transmits signals in series, a parallel optical interconnect system
transmits signals in parallel. In operation, data signals in parallel form
are input to signal processing and laser drive circuits at a transmitter.
The circuits then control laser optical radiation emissions of the data
signals. At a receiver, the optical signals are transformed back to
electrical data signals via photo detectors and signal processing
circuits. For the parallel optical interconnect system of the invention, a
plurality of integrally formed vertical cavity surface emitting lasers
(VCSELs) are used for signal transmission from the transmitter.
Despite its success in achieving higher data transmission speed compared to
conventional single or serial transmission link, a parallel optical
interconnect system with VCSELs inevitably encounters problems in
performance control and reliability, some of which arise from the nature
of parallel signal processing.
One major problem stems from VCSEL performance. The output optical power of
the VCSELs fluctuates due to changing environment such as temperature
variation, aging behavior of the VCSELs, or circuit property drift in the
laser drive circuitry. In the conventional single or serial transmission
link, the data output from the laser is coded to be dc balanced. The dc
balancing technique allows one to place a photodetector monitor at one
face of the laser that is not coupled into the optical fiber. The
photodetector receives a proportional fraction of the laser light that is
emitted from the laser, and delivers a feedback signal to the laser drive
circuit to correct the laser output optical power fluctuation. However,
this method is inefficient and troublesome for a parallel optical
interconnect system. It would require a photodetector and a feedback
circuit for each and every one of the VCSELs. In addition, the dc balance
technique is incompatible with the use of uncoded dc signals as in present
parallel optical interconnect systems.
Recently, the inventor has developed a new method in which the monitoring
photodetector is integrated into VCSELs so as to provide for adjustment of
a laser output optical power in a parallel optical interconnect system.,
see U.S. patent application Ser. No. 08/217,531, which is incorporated
herein in its entirety by reference. However, there still remains a
significant need for a method and apparatus to monitor and automatically
compensate for the laser output optical power fluctuation, in order to
reliably utilize the parallel optical interconnect system.
Furthermore, the laser output optical power fluctuation at the transmitter
affects the data signal retrieval at the receiver. Thus, there also exists
a need to properly retrieve data signals despite any signal fluctuation.
Another kind of problem comes from the nature of parallel processing.
Unlike a conventional single (serial) transmission link which typically
uses ac coupled receivers, each having a clock recovery circuit, a
parallel optical interconnect system has skew, i.e., the signals on a set
of parallel interconnects do not all arrive at the receiver
simultaneously. The clock signal is transmitted on a separate line in
parallel with the data. Skew may be caused by the same factors that lead
to output optical power fluctuation of a VCSEL. For example, since the
signals being transmitted in the parallel optical interconnect system are
uncoded and not dc balanced, some VCSELs transmit more high level (1
level) signals than others during transmission. This almost ensures that
these VCSELs have higher temperatures during operation. The temperature
difference may be quite significant from one end of the VCSEL array to the
other. This laser substrate temperature difference is just one source of
skew problems.
A weak clock signal conceivably is another source of skew in the parallel
optical interconnect system. Because the clock signal is transmitted with
data and this clock signal is used to extract the data signals, there is
likely to be skew if there is uncertainty about the exact location in time
of the clock transition.
Since skew may cause serious distortion of data signals during
transmission, thus offsetting the advantage of using a parallel system, it
is essential for a parallel optical interconnect system to have minimal
skew.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide simple and
efficient electronic circuits to monitor and automatically compensate at a
transmitter and receiver for laser output optical power fluctuation
because of substrate temperature variation and aging behavior at the
transmitter, and to retrieve a data signal at the receiver of the parallel
optical interconnect system.
It is another object of the invention to monitor the output of one of the
vertical cavity surface emitting lasers (VCSELs) and use this output to
control the outputs of the other VCSELs in the array.
It is yet another object of the invention to reduce or avoid skew in
parallel data signal transmission.
The parallel optical interconnect system of the invention comprises an
optical transmitter, an optical receiver, and an optical connector formed
by optical fibers. The optical transmitter transmits a plurality of dc
Non-Return-to-Zero (NRZ) data signals and at least one clock signal via a
plurality of optical fibers to the optical receiver.
In one embodiment of the invention, the optical transmitter comprises a
plurality of integrally formed vertical cavity surface emitting lasers
(VCSELs) and laser drive circuits therefor and a laser drive current
regulator for high level laser output power. Each of the laser drive
circuits has one signal input terminal and one control terminal. The laser
drive current regulator comprises a VCSEL, a laser drive circuit therefor,
a photodetector, and a laser drive current compensator circuit.
The VCSEL used in the laser drive current regulator is integrally formed on
the same substrate as the other VCSELs using the same processes and is
selected to be adjacent to the VCSEL used for the clock signal
transmission. The drive current compensator monitors, via the
photodetector high level laser output, power fluctuation of its VCSEL and
feedbacks control signals to the control terminals of each of the VCSEL
drive circuits to automatically compensate for the high level laser power
fluctuation.
In another embodiment of the invention, the laser drive current regulator
comprises a high level laser drive current monitor, a low level laser
drive current monitor, and a laser drive level corrector. Each one of the
high level laser drive current monitor and the low level laser drive
current monitor comprises a VCSEL, a laser drive circuit therefor, a
photodetector, and a drive current detector. The laser drive current
regulator monitors both high level and low level laser output power
fluctuations and feedbacks to each of the VCSEL drive circuits control
signals that automatically compensate for the power fluctuations.
In another embodiment of the invention, the optical receiver responsive to
a plurality of dc NRZ data and an independent clock signal comprises a
plurality of signal receivers and multi-stage signal amplifiers and a
clock signal photocurrent averager.
The clock photocurrent averager retrieves the clock signal and produces a
reference current level from the received clock signal. Further, the
signal receivers retrieve the data signals using the reference current
level. Finally, the retrieved data signals are amplified by the
multi-stage signal amplifiers before exiting from the receiver.
Further in accordance with the invention clock skew is reduced or avoided
by using a more precisely timed VCSEL for clock signal transmission than
for data signals, by using at least two VCSELs for clock signal
transmission and by interspersing the clock VCSELs among the data VCSELs.
Other objects and features of the present invention will be apparent from
the following detailed description of the preferred embodiment.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be further described in conjunction with the
accompanying drawings, in which:
FIG. 1 is a schematic block diagram of an optical transmitter of a first
preferred embodiment of the parallel optical interconnect system;
FIG. 2 is a schematic block diagram of an optical transmitter of a second
preferred embodiment of the parallel optical interconnect system;
FIG. 3 is a preferred circuit configuration of a common cathode VCSEL drive
circuit used in the optical transmitters of the above embodiments;
FIG. 4 is a schematic block diagram of an optical receiver of a third
preferred embodiment of the parallel optical interconnect system;
FIG. 5 is a schematic of a high gain transimpedance amplifier for the
optical receiver of the embodiment of FIG. 4;
FIG. 6 is a schematic of a post amplifier/limiter for the optical receiver
of the embodiment of FIG. 4; and
FIG. 7 is a schematic of a CMOS output amplifier for the optical receiver
of the embodiment of FIG. 4.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The parallel optical interconnect system of the invention comprises an
optical transmitter, an optical receiver, and an optical connector. The
first two preferred embodiments are implemented at the transmitter of the
parallel optical interconnect system for steady transmission of
Non-Return-to-Zero (NRZ) data. The electronic circuits in these
embodiments have the capability of not only monitoring vertical cavity
surface emitting laser (VCSEL) output optical power fluctuation due to
laser substrate temperature variation and laser aging behavior but also
automatically compensating for VCSEL output power due to the
above-mentioned effects. The third preferred embodiment is implemented at
the receiver.
FIG. 1 is a schematic block diagram of a first embodiment of the present
invention implemented at the transmitter of the parallel optical
interconnect system. In this embodiment it is assumed that low level laser
drive current is very close to the lasing threshold so that it does not
require compensation and that it is only necessary to compensate for
fluctuations in higher level laser output power. The optical transmitter
comprises a signal transmission generator 100 and a laser drive current
regulator 150 for high level laser output power. The signal transmission
generator transmits dc NRZ data and clock signals via a plurality of
optical fibers of the optical connector to an optical receiver (not
shown). Signal transmission generator 100 comprises a plurality of
integrally formed VCSELs 110, each of which is driven by a laser drive
circuit 120. Preferably, laser drive circuits are connected to VCSELs 110
on a one to one basis. Each of the laser drive circuits has a signal input
terminal 121 and a control terminal 122. Laser drive current regulator 150
comprises a VCSEL 160, a laser drive circuit 170, a photodetector 180, and
a laser drive current compensator 190. Laser 160 is integrally formed on
the same substrate as VCSELs 110 by the same processes as used to form
VCSELs 110 and is the same size. Laser drive circuit 170 is the same as
laser drive circuits 120 and has a signal input terminal 121 and a control
terminal 122. Laser drive current compensator 190 has an input terminal
191 and an output terminal 192. The output terminal is connected to
control terminal 122 of each of the laser drive circuits, and input
terminal 191 is connected to photodetector 180.
Adjacent VCSELs on the same substrate may be fabricated to be identical and
may perfectly match each other in terms of L-I and I-V characteristics.
Moreover, the adjacent VCSELs experience the same thermal history and have
the same substrate temperature variation. Thus, one is able to determine
the operational behavior of one VCSEL by monitoring its adjacent VCSEL.
Preferably, VCSEL 160 of laser drive current regulator is selected so that
it is adjacent to the VCSEL used for the clock signal transmission so that
current regulator 150 precisely monitors the operation of the clock signal
VCSEL.
In the embodiment of FIG. 1, a 50% duty cycle clock signal is duplicated
and used to drive two adjacent VCSELs at the transmitter, one VCSEL 110
being used to transmit the clock signal along with the dc NRZ data into
the optical fibers of the optical connector, and the other VCSEL, laser
160, being used to modulate a laser beam in the laser drive current
regulator so that it carries an identical clock signal. The beam from
laser 160 irradiates photodetector 180 which converts the optical form of
the clock signal into an electrical form of the clock signal that is
applied to the laser drive current compensator. The current compensator
monitors a current corresponding to the high level laser output optical
power. If the high level laser output optical power remains above a level
sufficient for reliable transmission, the drive current compensator does
not interfere. However, when the high level laser output optical power
falls below the level necessary for optimal operation due to either a
variation in laser substrate temperature or aging behavior of the VCSEL,
laser drive current compensator 190 detects current magnitude and provides
a feedback to each of the laser drive circuits 120 to automatically
compensate for the fluctuation in laser output optical power. As a result,
the high level laser output power of the dc NRZ data and clock signal is
maintained in the optimal operation range, despite any environmental
change and/or aging behavior of the lasers. Selection at the transmitter
of the optimal power range simplifies the complexity, size and power
dissipation of the receiver.
The second embodiment of the invention deals with an automatic adjustment
of both high level and low level laser output powers due to laser
substrate temperature variation and/or aging behavior of VCSELs.
Electronic circuits dynamically determine which laser drive current level
must be adjusted in order to keep the VCSELs transmitting signals at the
optimal bias point, thus having a low error bit rate for the data.
As shown in FIG. 2, an optical transmitter responsive to a plurality of dc
NRZ data and an independent clock signal comprises a signal transmission
generator 200 and a laser drive current regulator 250 for both high level
and low level output powers. The signal transmission generator is used for
transmitting dc NRZ data and clock signals into a plurality of optical
fibers of the optical connector. Signal transmission generator 200
comprises a plurality of integrally formed VCSELs 210, each of which is
driven by a laser drive circuit 220. Preferably, laser drive circuits 220
are connected to VCSELs 210 on a one to one basis. Each laser drive
circuit 220 has a signal input terminal 221 and two control terminals 222,
223. Control terminal 222 is used to control the low level output of laser
drive circuit 220 and control terminal 223 is used to control high level
output. Laser drive current regulator 250 comprises a low level laser
drive current monitor 260, a high level laser drive current monitor 280,
and a laser drive level corrector 290. Each high level laser drive current
monitor 280 and low level laser drive current monitor 260 comprise a VCSEL
262, 282, a laser drive circuit 264, 284, a photodetector 266, 286, and a
laser drive current detector 268, 288, respectively. Laser drive circuit
264 has a signal input terminal 221 and a low level control terminal 222
and laser drive circuit 284 has a signal input terminal 221 and a high
level control terminal 223.
The laser drive level corrector has two input terminals and two output
terminals. The input terminals are connected to the laser drive current
detectors of the high level and low level laser drive current monitors,
respectively; and the output terminals are connected to the high level and
low level control terminals of each of the laser driving circuits.
Lasers 262 and 282 are integrally formed on the same substrate as lasers
210 by the same processes as used to form lasers 210 and they are the same
size. Preferably lasers 262 and 282 are selected so that they are adjacent
and thermally coupled to the VCSEL used for the clock signal transmission
such that they experience the same thermal history and have the same aging
behavior.
In the embodiment of FIG. 2, a 50% duty cycle clock signal is copied and
delivered to three adjacent VCSELs at the transmitter. The first VCSEL is
used to transmit the clock signal along with dc NRZ data into the optical
fibers; the second VCSEL is used in the high level laser drive current
monitor, and is continuously driven by high level (i.e., 1 level) clock
signals; and the third VCSEL is used in the low level laser drive current
monitor, and is continuously driven by low level (i.e., 0 level) clock
signals.
The monitoring and automatic compensation for the high level laser output
power fluctuation is similar to that in the first embodiment. In the low
level laser output power monitoring and automatic adjustment, the laser
beam from VCSEL 262 irradiates photodetector 266 which generates a current
signal corresponding to the clock low signal. This current signal is
applied to low level drive current monitor 260.
Laser drive level corrector 290 continuously examines the current
magnitudes of both high level and low level clock signal and dynamically
determines which laser drive current level must be adjusted to keep the
VCSELs 210 transmitting signals at an optimal bias point. As a result, the
high level laser output powers of dc NRZ data and clock signals are
maintained in the optimal operation range, while the low level laser
output powers remains at the lasing threshold level. This embodiment
enables the operation of the optical transmitter to avoid the effects of
any environmental change and/or aging behavior of the lasers, thus having
low error bit rate for the data.
FIG. 3 delineates a preferred circuit configuration of a common cathode
VCSEL drive circuit used in the optical transmitters of the first and
second embodiments. The VCSEL drive circuit comprises a high level laser
current supplier 300, a low level laser current supplier 350, and an
input-output control circuit 330. The signal to be transmitted is provided
to the drive circuit of FIG. 3 at node 311 and is provided to the VCSEL at
output terminal 312. The circuit further comprises four current mirrors:
transistors 301, 302; transistors 304, 306; transistors 307, 308; and
transistors 309, 310. In the preferred embodiment, both transistors 301
and 302 have an amplification constant of 60; both transistors 304 and 307
have an amplification constant of 240; transistor 306 has an amplification
constant of 480; transistor 308 has an amplification constant of 120; and
both transistors 309 and 310 have an amplification constant of 24.
The operating principle of the VCSEL drive circuit is as follows. When the
input signal at node 311 is low, transistor 303 is open, i.e.,
non-conducting or off, and transistor 305 is closed, i.e., conducting or
on, in input-output control circuit 330. As a result, no current from the
high level laser current supplier may flow beyond transistor 303. In low
level laser current supplier 350, an external resistor R.sub.1 supplies a
current I.sub.1 to an on-chip mirror circuit formed of transistors 310 and
309. The current I.sub.1 is further mirrored to the output terminal 312 to
the common cathode VCSEL via another mirror circuit formed of transistors
307 and 308. Therefore, a laser drive current having a magnitude of
2I.sub.1 is output to the VCSEL for the low level signal transmission.
Here, the factor two comes from amplification constant ratio product of
the mirror circuit 310 and 309 and the mirror circuit 307 and 308,
respectively.
When the input signal at node 311 is high, transistor 303 in input-output
control circuit 330 is closed. In laser high level current supplier 300,
an external resistor R.sub.h, supplies a current I.sub.h, to an on-chip
mirror circuit formed of transistors 301 and 302. The current I.sub.h goes
through transistor 303, and is further mirrored to the output terminal to
the common cathode VCSEL via another mirror circuit formed of transistors
304 and 306. The current becomes 2I.sub.h when it reaches output terminal
312 to the VCSEL. The factor two is obtained by the similar reason as
explained above. In the meantime, the current, 2I.sub.1, from low level
laser current supplier 350 still supplies the VCSEL. Therefore, a laser
drive current corresponding to the high input signal with a magnitude
equal to the sum of 2I.sub.h and 2I.sub.1 is output to the VCSEL for high
level signal transmission.
The third embodiment of the invention is directed to a method and apparatus
for establishing a dynamic threshold to properly retrieve the dc coupled
NRZ data at the receiver regardless of transmitting attenuation.
Referring to FIG. 4, an optical receiver responsive to a plurality of dc
NRZ data and an independent clock signal comprises a signal receiver 400,
a multi-stage signal amplifier 440 and a clock photocurrent averager 470.
The signal receiver comprises a plurality of channel signal receivers 430,
illustratively one for each fiber of the optical connector; and the
amplifier comprises a like number of channel amplifiers 450.
Each of the channel signal receivers 430 identically comprises a
photodetector 431, a P-type Metal-Oxide-Semiconductor transistor (PMOS)
432, and a N-type Field-Effect-Transistor (NFET) mirror circuit formed by
transistors 433 and 434.
Each of multi-stage channel signal amplifiers 450 identically comprises a
trans-impedance amplifier 455, a post amplifier/limiter 460 and a CMOS
output amplifier 465. The three amplifiers are connected to each other in
series in the same order as listed. The trans-impedance amplifier is
connected to a node between photodetector 431 and one of the NFET mirror
circuit transistors in each of the signal receivers as shown in FIG. 4.
Clock photocurrent averager 470 is used to retrieve the clock signal and
produce a current reference level. It comprises a photodetector 471, a
capacitor 473, and two mirror circuits: a PMOS mirror circuit formed by
two transistors 475 and 477 and an NFET mirror circuit formed by two
transistors 479 and 481. Capacitor 473 is connected between the positive
voltage supply and the gates of transistors 475 and 477 of the
photocurrent averager 470. An output of photocurrent averager 470 is
applied to a channel signal amplifier 450. Another output is applied to
the gate of a transistor 432 in each channel signal receiver 430.
The operating principle of the electronic circuit for establishing a
dynamic threshold to retrieve the dc NRZ data and clock signal at the
receiver is as follows. When photodetector 471 is irradiated by the
optical radiation carrying the clock signal, photodetector 471 generates a
photocurrent. The clock signal photocurrent is then averaged by capacitor
473. The average photocurrent is mirrored twice through the two mirror
circuits of the clock photocurrent averager back to node 485, and used as
a reference current level to output the clock signal to the transimpedance
amplifier 455 connected at node 485.
In addition, the average clock photocurrent serves as the reference current
level for retrieving the dc NRZ data at the receiver of the parallel
optical interconnect system. Accordingly, the average clock photocurrent
is delivered to transistor 432 of each channel signal receiver, and
subsequently is mirrored via the NFET mirror circuit to node 435 at the
input to trans-impedance amplifier 455. When the dc NRZ data photocurrent
generated by the photodetector is superposed upon the average clock
photocurrent, the resultant current is then output to the transimpedance
amplifier and the multi-stage amplifier amplifies the data signal.
The trans-impedance amplifier depicted in FIG. 4 is used for small signal
amplification. A suitable high gain trans-impedance amplifier circuit is
depicted in FIG. 5. Transistors 501-509 are
Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFETS) In addition,
the amplifier circuit requires a pair of voltage sources, +5 V and -5 V
respectively, as the power supply. As the current signal carrying dc NRZ
data enters input node 520, the trans-impedance amplifier transforms the
relatively small current signal to two large voltage signals, and outputs
these signals to the next amplifier from output terminals 530 and 540.
In a preferred embodiment of the trans-impedance amplifier, amplification
constants for transistors 501 through 508; transistors 509 and 510; and
transistors 511 through 514 are 24, 60, and 12, respectively.
The post amplifier/limiter 460 of FIG. 4 provides an interface between the
trans-impedance amplifier 455 and the CMOS output amplifier 465 to prevent
any signal surge in amplification. A schematic of the post
amplifier/limiter is shown in FIG. 6. The trans-impedance amplifier output
terminals 530 and 540 are connected to input terminals 620 and 630 of the
post amplifier/limiter. Transistors 601-609 are MOSFET transistors. The
circuit needs a pair of voltage supplies, +5 V and -5 V, as the power
supply. Transistor 605 controls circuit bias; and transistors 606 and 607
function as an resistive load for transistors 608 and 609 respectively.
The post amplifier/limiter may regulate s | | |
