Time slot exchanger mechanism in a network for data communication having isochronous capability

What is claimed is:

1. Apparatus for communicating between first and second entities in a time slot interchange fashion, the apparatus comprising:

a storage memory having first, second and third memory sections;

wherein said first memory section is coupled to receive data from said first entity;

wherein said second memory section is adapted to store data received from said first entity prior to receipt of said data by said first memory section;

wherein said third memory section is coupled to said second entity and outputs to said second entity data received from said first entity at a time previous to receipt of said data stored in said second memory section;

means coupled to said first and second entities for receiving a first cycle start reference from said first entity indicating the start of a cycle of data of said first entity and a second cycle start reference from said second entity indicating the start of a cycle of data of said second entity, respectively; and

control means coupled to said means for receiving for alternately assigning first, second and third physical storage locations to said first, second and third memory sections, respectively, responsive to receipt of said first and second cycle start references.

2. The apparatus of claim 1 wherein said first, said second and said third memory sections each comprise an individual ping pong buffer.

3. The apparatus of claim 1 wherein said storage memory is comprised of a single physical memory unit.

4. The apparatus of claim 1, wherein said control means designates said third memory section responsive to said second cycle start reference and designates said first and second memory sections responsive to said first cycle start reference.

5. The apparatus of claim 1 wherein said data are isochronous.

6. The apparatus of claim 1 wherein said third memory section is adapted to output said data to said second entity in a different order than as received from said first entity.

7. The apparatus of claim 1 wherein said means for receiving is comprised of cycle start detection logic.

8. The apparatus of claim 1 wherein said control means is comprised of cycle start detection logic.

9. Apparatus for communicating between first and second stations in a data communication system over a link, said data communication system including a plurality of data sources and sinks, a first of said sources and sinks configured to receive or transmit data isochronously and a second of said sources and sinks configured to transmit data non-isochronously, the apparatus comprising:

a first receiver and a first transmitter in said first station;

said link coupling said first station with said second station;

said second station being coupled to both said first and second sources and sinks;

a second transmitter in said second station adapted to transmit data to said first receiver;

a multiplexer in said second station adapted to permit the transmission of data from both said first and second sources and sinks over said link as multiplexed data, said multiplexer providing a dedicated bandwidth for data originating from an isochronous source, including said first of said sources and sinks; and

means, coupled to said first and second stations, for exchanging said isochronous data over said link including:

a storage memory having first, second and third memory sections;

wherein said first memory section is coupled to receive data from said second station;

wherein said second memory section is adapted to store data received from said second station prior to receipt of said data by said first memory section;

wherein said third memory section is coupled to said first station for outputting data received from said second station at a time previous to receipt of said data stored in said second memory section, to said first station;

means coupled to said second and first stations for receiving a first cycle start reference from said second station indicating the start of a cycle of data of said first station and a second cycle start reference from said first station indicating the start of a cycle of data of said second station, respectively; and

control means coupled to said means for receiving for alternately assigning first, second, and third physical storage locations to said first, second and third memory sections responsive to receipt of said first and second cycle start references.

10. The apparatus of claim 9 wherein said third memory section is adapted to output said data to said first station in a different order than as received from said second station.

11. The apparatus of claim 9 wherein said means for receiving is comprised of cycle start detection logic.

12. The apparatus of claim 9 wherein said control means is comprised of cycle start detection logic.

13. In a data communications system, a method for exchanging data between first and second entities in a time slot interchange fashion comprising the steps of:

receiving data from said first entity and placing said data in a first portion of memory;

storing data received from said first entity prior to receipt of said data by said first portion of memory, in a second portion of memory;

outputting to said second entity, from a third portion of memory, data received by said third portion of memory from said first entity at a time earlier than said data is received by said second portion of memory;

alternately designating a first one of three physical memory locations for said first portion of memory and a second one of said three physical memory locations for said second portion of memory upon receipt of a first cycle frame reference from said first entity; and

alternately designating a third one of said three physical memory locations for said third portion of memory upon receipt of a second cycle frame reference from said second entity such that said three physical memory locations are alternately designated for said first, second and third portions of memory.

14. The method of claim 13 wherein the designating steps further comprise the steps of designating individual ones of three ping pong buffers as said first, second and third memory portions, respectively.

15. The method of claim 13 wherein said designating steps comprise the steps of designating first, second and third physical regions of a common memory, respectively.

16. The method of claim 13 wherein said data is isochronous.

17. The method of claim 13 wherein said third portion of memory is adapted to output said data to said second entity in a different order than as received from said first entity.

18. Apparatus for exchanging data between first and second entities in a time slot interchange fashion, the apparatus comprising:

a buffer memory coupled to said first and second entities comprised of first, second and third physical memory sections;

means coupled to said first and second entities for receiving a cycle start reference from said first entity indicating the start of a cycle of data from said first entity and a cycle start reference from said second entity indicating the start of a cycle of data from said second entity; and

means coupled to said means for receiving for designating the first, second and third physical memory sections to alternately:

(1) input data from said first entity responsive to receipt by said means for receiving of a cycle start reference from said first entity,

(2) hold data received from said first entity responsive to a preceding cycle start reference from said first entity upon receipt by said means for receiving of said cycle start reference from said first entity, and

(3) output data received during a further preceding cycle start reference from said first entity to said second entity upon receipt by said means for receiving of a first cycle start reference from said second entity.

19. The apparatus of claim 18 wherein said data is isochronous.

20. The apparatus of claim 18 wherein said third physical memory section is adapted to output said data to said second entity in a different order than as received from said first entity.

21. The apparatus of claim 18 wherein said means for receiving is comprised of cycle start detection logic.

22. The apparatus of claim 18 wherein said means for designating is comprised of cycle start detection logic.

23. The apparatus of claim 18 wherein

(1) said means for designating, upon receipt of said cycle start reference from said first entity,

(a) designates said first physical memory section to input data from a cycle of data from said first entity corresponding to said cycle start reference from said first entity and

(b) designates said second physical memory section to hold data which was inputted to said second physical memory section from a cycle of data from said first entity corresponding to a preceding cycle start reference from said first entity, and

(2) said means for designating, upon receipt of said cycle start reference signal from said second entity, designates said third physical memory section to output data from a further preceding cycle of data from said first entity.

24. In a data communications system, a method for exchanging data between first and second entities in a time slot interchange fashion comprising the steps of:

inputting first data from said first entity into a first memory section upon receiving a first cycle start reference from said first entity indicating the start of a first cycle of data from said first entity;

outputting said first data to said second entity from said first memory section upon receiving a first cycle start reference from said second entity indicating a start of a new cycle of data from said second entity;

inputting second data from said first entity into a second memory section upon receiving a second cycle start reference from said first entity;

outputting said second data to said second entity from said second memory section upon receiving a second cycle start reference from said second entity indicating the start of a second cycle of data from said second entity;

inputting third data from said first entity into a third memory section upon receiving a third cycle start reference from said first entity; and

outputting said third data from said second entity from said third memory section upon receiving a third cycle start reference from said second entity indicating the start of a third cycle of data from said second entity.

25. The method of claim 24 wherein said first, second and third data are isochronous.

26. The method of claim 24 herein said first data is adapted to be output from said memory section in a different order than as input to said first memory section.

Description Submit all comments and votes

The present invention relates to communication between stations or between two high bandwidth buses in a data communication system, such as a local area network or wide area network, and in particular to a network for transferring isochronous data with a transfer port, a hub cascade port and/or a frame synchronizing signal.

BACKGROUND OF THE INVENTION

In general terms, isochronous data is data which is non-packetized and of indeterminate, potentially continuous duration. Increasing availability of multi-media computers and work stations has contributed to an increase in interest in the transfer of data from isochronous data sources and sinks. An isochronous data source is a device which outputs data in a continuous stream, usually at a substantially constant average data rate. Examples include video cameras, which output a substantially continuous stream of data representing images and associated sounds, and telephone output, which can be a substantially continuous output of voice data (either analog or digitized). An example of an isochronous data sink is a video monitor which can receive a substantially continuous stream of video data for display.

Related to isochronous sources and sinks is the concept of data transfer which can also be either isochronous or non-isochronous. One type of non-isochronous data transfer is a packet-type transfer. As shown in FIG. 1A, data can be transferred in a plurality of packets 12a, 12b which can be either constant-sized or variable-sized. Each packet includes a field of data 14a, 14b which may be preceded and/or followed by non-data information such as preamble information 16a, 16b housekeeping information such as data source information, data destination information, and the like 18a, 18b and a frame end marker 20a. As seen in FIG. 1A, because the fields provided for data 14a, 14b are not substantially continuous, the packetized scheme of FIG. 1A is not isochronous but "bursty" in nature. An example of packetized data transfer is the commonly-used ethernet system. Standard ethernet systems are described in IEEE Standard 802.3. One implementation of which, known as 10 Base T, is described in the draft nine supplement to IEEE standard 802.3, dated Nov. 15, 1989.

Another type of non-isochronous data transfer is a token ring system. In a token ring system, a node is permitted to transmit data only after receipt of an electronic "token." As depicted in FIG. 1B, a first station may transmit a token 22a which is received 24a by a second station whereupon the second station may begin transmission of data 26a. After a period of data transmission, the second station transmits the token 22b which is received by a third station 24b that can then begin its own transmission of data 26b. As seen in FIG. 1B, because data transmission is synchronized with the occurrence of an event (the arrival of a token), the token ring system is not an isochronous data transfer system. One commonly used token ring Network is described in IEEE standard 802.5.

In contrast, FIG. 1C schematically depicts isochronous data transfer. In isochronous data transfer, the data transfer or connection is initiated, such as by initiating a telephone conversation or beginning a video camera transmission 30. After the connection is initiated, transmission of the data, possibly accompanied by transmission of housekeeping information (such as destinations, audio or video timing, and the like) is provided substantially continuously for an indeterminate period, such as until termination of the connection 32. Although it may be that not every bit transferred represents a data bit (since "housekeeping" bits may be also transferred), the transfer of data is substantially continuous in the sense that there are no substantial periods during which no data bits are transferred. It is possible that the data being transferred is "Null" data such as silence during a telephone conversation or transfer of a blank video image. One type of isochronous data transfer is the Fiber Distributed Data Interface-II (FDDI-II) as described, for example, in FDDI-II Hybrid Multiplexer, Revision 2.4, dated Mar. 25, 1991.

Previous attempts to accommodate isochronous data on a data network have resulted in characteristics which are disadvantageous for at least some applications. In some previous isochronous devices, the bandwidth available for accommodating a given isochronous source or sink was at least partially dependent on the demand on the network (i.e. on the total amount of data from and to sources and sinks transmitting and receiving on the network). In this type of system, performance of an isochronous source or sink could perceptibly degrade as additional sources or sinks were added to the network, such as by increasing data transfer delay. Preferably, both isochronous and non-isochronous bandwidth is provided, with the isochronous bandwidth being fixed and insensitive to non-isochronous demand and the non-isochronous bandwidth being fixed and insensitive to isochronous demand.

Many types of isochronous data transfer systems fail to provide for inter-operability with data derived from non-isochronous sources or sinks. In this type of system a given link is unable to transfer data from both an isochronous source/sink and a non-isochronous source/sink in a concurrent fashion (i.e. both within a time frame sufficiently short that the transfer is effectively simultaneous such that the ability of data sinks to process the data and the user's perception of the data are not substantially impacted). In these systems, it is infeasible to provide a single node which is coupled to both isochronous and non-isochronous source/sinks (such as a multimedia PC having ethernet capabilities and a video camera).

Some previous isochronous systems provide little or no compatibility with previous networks so that extensive replacement of hardware or software becomes necessary. For example, in some schemes, it is necessary to replace the physical medium such as twisted pair media, or if existing in-place physical media are used, the performance is degraded, such as by a decrease in bandwidth for the type of communication formerly carried by the existing media.

Some isochronous systems require installation of new Media Access Controllers (MAC) or provision of new application software (such as local area network software). Some previous isochronous systems introduce an undesirable degree of delay or "jitter" (data discontinuities). Some types of isochronous systems are inflexible in the amount of bandwidth provided for isochronous data such that if the data rate of an isochronous source or sink is not precisely matched to the available bandwidth, the bandwidth will be either overwhelmed or substantially under-utilized by the isochronous traffic.

SUMMARY OF THE INVENTION

The present invention provides for communication of data to and from isochronous data sources and sinks so that the bandwidth available to an isochronous source/sink is independent of changes in isochronous demand on the network. Of the total bandwidth used for communication over the network links or physical media, at least a portion of the total bandwidth is dedicated to isochronous traffic. Preferably the bandwidth available for isochronous traffic can be selected or allocated with a predetermined granularity, e.g. so that the quality of transmission service desired for a given isochronous source or sink can be selected and the selected bandwidth can be sustained throughout the isochronous communication or connection. Preferably, a portion of bandwidth on the link is also dedicated to convey data to and from non-isochronous sources and sinks, as well as to permit conveying housekeeping information (such as information relating to data sources and destinations) and status and control maintenance information.

Preferably, the data communications system is implemented as a star-topology network with data sources transmitting to a central hub which, in turn, transmits the data to data sinks. Although, for convenience, much of the following discussion is in terms of hubs and nodes, aspects of the present invention can be implemented in topologies other than hub-and-node topologies (e.g., ring topologies, and tree topologies), as will be apparent to those of skill in the art. Descriptions of this circuitry in the following could be implemented, e.g., on a PBX adapter card for a personal computer. Several star-topology systems can be connected by providing inter-connection of the hubs, for example, in a ring structure (FIG. 3A). The system could also be arranged in a tree structure where one hub 44d is connected to others (44e, 44f) as depicted, e.g., in FIG. 3B. The multiplexed data from the node which arrives at the hub is de-multiplexed to separate the isochronous-source data, the non-isochronous-source data and the D channel and M channel information. The non-isochronous-source data can be provided to hub circuitry specialized for handling the non-isochronous data stream. Preferably, circuitry in the hub will convert the separated non-isochronous data stream into a form substantially similar to the form the data stream would have after arrival over a previously available non-isochronous network. For example, where non-isochronous data is sourced from an ethernet MAC, the hub will convert the separated non-isochronous data to a form such that it can be properly handled by standard ethernet hub repeater circuitry.

The separated isochronous data is conveyed to locations where it can be transmitted to the destination nodes of the network. The separated isochronous data is placed on a high bandwidth hub bus, with bandwidth capable of transmitting the collective isochronous data streams arriving from all nodes connected to the hub. The data arriving from the nodes can be placed onto the high bandwidth bus by e.g. a time slot interchange (TSI) function. One type of time slot interchange is described in FDDI-II Hybrid Multiplexer, Revision 2.4, dated Mar. 25, 1991. Preferably, the isochronous data is placed onto the high bandwidth bus and retrieved from the high bandwidth bus (for transmission back to the destination nodes) according to switching tables programmed in accordance with source/destination data transmitted over the D channel. In this way, the hub has sufficient intelligence to set up and maintain isochronous communication sessions or connections which may be requested on the D channel.

According to an embodiment of the present invention, the time slot interchange (TSI) function is implemented by making use of a set of three ping pong buffers. By controlling of the timing of the system, a third buffer exchanges data onto the TSI bus while a first buffer begins receiving data from one or more nodes. A second buffer serves as a holding buffer to account for skew between the two entries exchanging data. Upon completion of the data transfer, the second buffer is then designated as the output buffer. The third buffer is filled with incoming data and the first buffer holds the previously received data to account for the skew.

According to another embodiment of the present invention, a triple pointer scheme may be used in place of the three ping pong buffers. The pointer points to the buffer location to be used for incoming, outgoing and data temporarily held to correct for skew. Logic in the switching system detects the receipt of a frame start delimiter marking the beginning of a new data cycle. The logic then aligns the pointers with the appropriate buffer location.

Further features and advantages of the present invention will be described in greater detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B and 1C of the timing of a packet transmission system, a token ring transmission system, and an isochronous transmission system respectively.

FIG. 2 is a schematic block diagram showing three nodes connecting to a hub card according to one embodiment of the present invention;

FIG. 3A is a schematic block diagram showing a number of hubs connected together using a ring structure;

FIG. 3B is a block diagram showing a number of hubs connected together using a tree structure;

FIG. 4. is a schematic block diagram of circuitry for multiplexing and preparing data for transmission over the media and for receiving information from the media and demultiplexing the data;

FIG. 5. is a schematic block diagram of receiver circuitry according to an embodiment of the present invention;

FIG. 6 is a block diagram depicting the packet receive interface, according to an embodiment of the present invention;

FIG. 7 is a schematic block diagram of a signaling processor in the hub and its connection to hub circuitry for receiving and buffering data for placement on a high bandwidth bus and connections to nodes;

FIG. 8 is a schematic block diagram of an isochronous time slot data exchange switching mechanism according to an embodiment of the present invention;

FIG. 9 is a schematic block diagram of another embodiment of an isochronous time slot data exchange switching mechanism according to the present invention;

FIG. 10 is a schematic block diagram of a pa