or
Bookmark and Share
Multilayer article comprising a toughened polycyanurate with embedded electrically conductive patterns
   
Document Number
US Patent 5523148
Issued Date
June 4, 1996
Link
Inventors
Map
Abstract
A prepreg which is heat curable within a temperature range of between about 200.degree. C. and 325.degree. C. comprising a reinforcing material impregnated with a curable material said curable material comprising a blend of a fluorine-containing cyanate and a fluorine-containing arylene ether polymer wherein said cyanate is a monomer having the structure said fluorine containing arylene ether polymer has the structure wherein X is any group capable of reacting with a --C.tbd.N group; R is an aliphatic or aromatic group which may or may not be fluorosubstituted; R.sup.1 is an aliphatic or aromatic group which may or may not be fluoro substituted or R.sup.1 is selected from the group consisting of ether, carbonyl, sulfone, phosphine oxide and sulfide, and at least one of R or R.sup.1 must be fluoro substituted; n is 0-10; and m is 0-100; said material in the cured state comprising a fluorine-containing polycyanurate network having a plurality of discrete phases of said fluorine-containing thermoplastic polymer dispersed therein wherein said thermoplastic polymer phases are of submicron size.
Drawing
Multilayer article comprising a toughened polycyanurate with embedded electrically conductive patterns - US Patent 5523148 Drawing
Drawing from US Patent 5523148
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
10
Comments:
no comments yet
Published
June 4, 1996
Application Number
08/344,475
Filed
November 23, 1994
US Classification
442/169   442/180 442/233 442/234 442/251 442/378 442/392
Int'l Classification
C08L   79/00   (20060101)   C08L   79/04   (20060101)   H05K   1/03   (20060101)  
Attorney/Law Firm
Parent Case
This application is a division of application Ser. No. 07/923,723, filed Jul. 31, 1992, pending.
USPTO Field of Search
428/260   428/290  
Related Patents
6174800 - Via formation in a poly(arylene ether) inter metal dielectric layer - Owned by Taiwan Semiconductor Manufacturing Company (Hsin-Chu,TW)

A process for removal of residual hardmask used to etch vias in low-k organic polymer dielectric layers is described. The hardmask deteriorates by developing an angular aspect or faceting along the pattern edges when used to etch organic polymer layers in an oxygen/inert gas plasma in a high density plasma etcher. The residual hardmask is removed after the via etch with an aqueous etchant to prevent subsequent bridging shorts. A protective layer, formed over the subjacent conductive layer of a material resistant to the aqueous etchant, protects the conductive layer from attack during hardmask removal. The protective layer is subsequently removed by sputter etching immediately prior to the sputter deposition of barrier metallurgy into the via opening. Residual silicon oxide hardmasks are etched in aqueous HF using a protective layer of silicon nitride or silicon oxynitride and residual silicon nitride or silicon oxynitride hardmasks are removed with H.sub.3 PO.sub.4 in the presence of a silicon oxide protective layer.

5780159 - Plastic optical components - Owned by Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung e.V. (Munich,DE)

The invention concerns optical elements made from polycyanurate resins, wh exhibit a refractive index, at 633 nm, in the range from 1.45 to 1.70 and an optical absorption, at 1.3 or 1.55 .mu.m, in the range from 0.1 to 1.0 dB/cm.

5847327 - Dimensionally stable core for use in high density chip packages - Owned by W.L. Gore & Associates, Inc. (Newark, DE)

A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

6344371 - Dimensionally stable core for use in high density chip packages and a method of fabricating same - Owned by W. L. Gore & Associates, Inc. (Newark, DE)

A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us