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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for processing image data and an
apparatus therefor, and more particularly to such method and apparatus for
synthesizing at least two image signals.
2. Description of the Prior Art
As an example of high-speed image synthesis there is already known that
employed in the field of television in which a synthesized image can be
obtained by receiving and storing the image signal of a program in a
random-access frame memory while receiving and reproducing another
program, reading the thus stored signal at a determined position in said
other reproduced program, and switching two signals by a switching
circuit. In such case said switching circuit can be composed of an analog
switch since the image synthesis is basically effected between analog
signals. Such conventional method is however not applicable to the
run-length encoded signals obtained for example in facsimile devices.
As already known, the run-length encoding is employed for compressing the
amount of continuous signals such as image signals. For example 320
consecutive white pixels, conventionally requiring a memory capacity of
320 bits, can be compressed in said encoding to less than 20 bits, i.e.
several bits indicating white pixels and also several bits representing
"320". The rate of compression can be further increased by so-called
modified Huffman code with variable length. It has been difficult in the
known art to synthesize such encoded and compressed signals.
Also computer processing, such as synthesis, of such encoded image signals
has been quite slow.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an image processing
method and an apparatus therefor not associated with the above-mentioned
drawbacks.
Another object of the present invention is to provide a method and an
apparatus for synthesizing run-length encoded image signals.
Still another object of the present invention is to provide a method and an
apparatus capable of a real-time high-speed image processing.
Still another object of the present invention is to provide a reproducing
apparatus provided with a control circuit for synthesizing run-length
encoded image signals;
Still another object of the present invention is to provide a method and an
apparatus for compressing, encoding, synthesizing and reproducing document
image signals;
Still another object of the present invention is to provide a method and an
apparatus for partial synthesis of run-length encoded image signals stored
in memories;
Still another object of the present invention is to provide a method and an
apparatus for reproducing an image by synthesizing an image in a memory
with an image of a scanned document.
Still another object of the present invention is to provide a method and an
apparatus for synthesizing a run-length encoded image signal with an
uncoded image signal.
Still another object of the present invention is to provide an improvement
over an image reproducing method and an apparatus therefor in which the
image reproducing position can be arbitrarily selected.
Still another object of the present invention is to provide an improvement
over an image reproducing method and an apparatus therefor having plural
image memories.
Still another object of the present invention is to provide an improvement
over an image reproducing method and an apparatus therefor in which a
document image is electrically read, processed and printed.
The foregoing and still other object of the present invention will be made
fully apparent from the following description of the preferred
embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing the entire system of an image
synthesizing apparatus embodying the present invention;
FIGS. 2, 2A and 2B are a block diagram showing the structure of an image
synthesizing apparatus of the present invention;
FIG. 3 is a block diagram of a main image data expander;
FIGS. 4, 4A and 4B are a block diagram showing an embodiment of a decoder
for modified Huffman's code;
FIG. 5 is a block diagram of an auxiliary image data expander;
FIGS. 6, 6A and 6B are a block diagram of an X-Y coordinate detecting
circuit;
FIGS. 7, 7A and 7B are a block diagram of a synthesized image compressor;
FIG. 8 is a block diagram of a modified Huffman encoder;
FIG. 9 is a schematic view of an embodiment of a coordinate input device;
FIG. 10 is a schematic view of another embodiment of the coordinate input
device;
FIG. 11 is an explanatory view showing the synthesis of a main image and an
auxiliary image;
FIG. 12 is an explanatory view showing the principle of addressing in
synthesis of a main image and an auxiliary image;
FIGS. 13, 13A and 13B are a block diagram of an apparatus synthesizing a
run-length encoded image signal and a signal from a character generator;
FIG. 14 is a block diagram showing the details of a principal part in FIG.
13;
FIG. 15 is an explanatory view showing the addresses for image synthesis;
FIG. 16 is an explanatory view of run-length;
FIG. 17 is a control flow chart for the coordinate input; and
FIG. 18 is an explanatory view of character synthesis.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Now the present invention will be clarified in detail by the following
description of preferred embodiments to be taken in conjunction with the
attached drawings.
FIG. 1 shows the entire system of an image synthesizing apparatus of the
present invention in a block diagram wherein an original document 1 is
displaced in a direction indicated by a thick arrow, hereinafter referred
to as the auxiliary scanning direction or X-direction, while it is
illuminated by an unrepresented illuminating device. The image on said
document 1 is focused through a lens 2 onto a solid-state linear imaging
device 3 such as a charge-coupled device CCD. The thin arrow on the
original 1 indicates the scanning direction of the CCD 3, hereinafter
referred to as the main scanning direction or Y-direction, in response to
clock signals from a clock generating circuit 4. There are provided a
video amplifying circuit 5 for amplifying thus obtained video signal into
a desired value, and a digitizing circuit 6 for digitizing said video
signal into a binary signal. A run-length encoder 7, for example utilizing
the modified Huffman's encoding according to the CCITT standard, is
utilized for compressing said video signal as explained in the foregoing.
An image memory 8, having a layered structure of at least three layers 8a,
8b, 8c as will be explained later and composed for example of a random
access memory, is used in combination with a magnetic disk 12 and a
magnetic tape 13 as auxiliary memories. An image synthesizing circuit 9 of
the present invention has a function of extracting a particular part from
one of for example two run-length encoded images and fitting said part
into a determined part of the other image.
The signal encoded by the run-length encoder 7 is either transmitted
through a signal line 17 to a run-length decoder 10 for decoding followed
by printing in a printer 11, or through a signal line 14 to the image
memory 8, then subjected to synthesis with a stored image in the image
synthesizing circuit 9 through a signal line 16, released from a signal
line 15 to the run-length decoder 10 for decoding and printed in the
printer 11. Signal lines 21, 22 perform input and output of signals to and
from the image synthesizing circuit.
A signal not requiring memory or synthesis as mentioned above is
transmitted through the signal line 17, which is functionally equivalent
to a signal line 18 bypassing the encoding circuit. The image synthesis
can be effected not only on two images stored in the image memory 8 but
also on a signal 21 or 19 obtained from the CCD 3 in combination with an
already stored image supplied from a signal line 16. Also a synthesis of a
stored image with a character image from a character generator 155 is
possible. Furthermore the synthesized image may not only be stored in the
image memory 8 but also be transmitted directly to the printer 11 through
the signal line 22 or 20. A sequence controller 23 controls the function
of the image synthesizing circuit.
FIG. 2 is a block diagram showing the principal part of the image memory 8,
image synthesizing circuit 9 and sequence controller 23 shown in FIG. 1.
The image memory 8 has a layered structure of at least three layers,
divided into a main image memory 8a, an auxiliary image memory 8b and a
synthesized image memory 8c, respectively provided with independent
hardware address counters 26, 29 and 46 for enabling independent address
access. It is naturally possible also to allot the addresses of said
memories to a certain address space of the sequence controller 23 for
enabling image data access by said controller. The memories 8a, 8b store
the image signals from the CCD 3 in the form of run-length encoded signals
obtained through the run-length encoder 7 and a modified Huffman
(M-H)encoder. The address counters 26, 29 are advanced by enable signals
EN supplied from the M-H encoder and through an unrepresented OR gate.
A modified Huffman (M-H) decoder 24 separates the main image stored in the
form of run-length code into a main image video signal 48 (B/W(1)) for
identifying black and white, a main image end-of-line signal 57 (EOL(1))
indicating the end of data of one line in the Y-direction, and a main
image run-length signal 62 (RUN(1)) indicating the number of consecutive
white or black bits. The numeral (1) attached to said signals indicates
that said signals are related to the main image. Said signals 48, 57 and
62 are respectively supplied to data selectors 30, 33 and a run-length
counter 25. The run-length counter 25 is advanced in synchronization with
clock pulses 2.phi.T and is reset when the count meets the run-length
signal 62 (RUN(1)) from the M-H decoder 24. Simultaneously with said
resetting the address counter 26 is started to read succeeding M-H encoded
data from the main image memory 8a. Consequently the output signal 51 from
the run-length counter 25 corresponds to the real time and is therefore
referred to as the real-time main image run-length signal (RUN-LENGTH
(1)). Also the signal 54 for resetting the run-length counter 25 is
hereinafter called the main image end-of-run-length signal (EOR(1)). Said
signals 51, 54 are respectively supplied to the data selectors 31, 32.
The auxiliary image signal is similarly decoded as explained in the
foregoing, wherein an M-H decoder 27, a run-length counter 28 and an
address counter 29 respectively correspond to the M-H decoder 24,
run-length counter 25 and address counter 26 for the main image. An
auxiliary image video signal 49 (B/W(2)), an auxiliary signal end-of-line
signal 58 (EOL(2)) and an auxiliary image run-length signal 63 (RUN(2))
obtained from said M-H decoder 27 are respectively supplied to data
selectors 30, 33 and the run-length counter 28. In a similar manner as
explained in the foregoing, the run-length counter 28 generates an
auxiliary image run-length signal 52 (RUN-LENGTH(2)) processed in
real-time and an auxiliary image end-of-run-length signal 55 (EOR(2)) for
resetting. Said signals 52, 55 are also supplied to the data selectors 31,
32. The numeral (2) attached to said signals indicates that said signals
are related to the auxiliary image.
The foregoing various signals obtained from the main and auxiliary images
are suitably selected by the data selectors 30, 31, 32, 33 in response to
an EOC signal to be explained later to provide a synthesized image video
signal 50 (R/W(3)), a real-time synthesized image run-length signal 53
(RUN-LENGTH (3)), a synthesized image end-of-run-length signal 56
(EOR(3)), and a synthesized image end-of-line signal 59 (EOL(3)), wherein
the numeral (3) indicates that said signals are related to the synthesized
image. Said signals 50, 53, 59 are supplied to an M-H encoder 45 for M-H
encoding in response to the signal 56 (EOR(3)) as will be explained later,
and thus encoded signal is stored in the synthesized image memory 8c
addressed by an address counter 46.
The data selectors 30, 31, 32 are real-time selected by an
enable-of-composite signal 60 (EOC) from a flip-flop 64 for effecting the
image synthesis.
Said EOC signal is generated in the following manner. At first a start
address Y0 for the Y-direction is stored in a Y-start address memory 35
through a data bus 61 of the sequence controller 23, and an end address Y1
is similarly stored in a Y-end address memory 36. Then a start address X0
for the X-direction is stored in an X-start address memory 40, and an end
address X1 is stored in an X-end address memory 41. Said storages are for
example conducted in response to the actuations of keys shown in FIG. 9.
As shown in FIG. 12, said addresses Y0, Y1, X0 and X1 stored in the
address memories 35, 36, 40 and 41 define a rectangular area in which the
image is to be extracted from the auxiliary image. Then the clock pulses
from the clock circuit 4 shown in FIG. 1 are counted, comparators 37, 38
compare the output signal from a Y-counter 34 indicating the position in
the Y-direction with output signals Y0, Y1 from said memories 35, 36. Said
comparators respectively supply enable signals for the Y-direction to gate
circuits 44, 65 at Y0 and Y1. Similarly comparators 42, 43 compare the
output signal from an X-counter 39 indicating the X-position of auxiliary
scanning with output signals X0, X1 from said memories 40, 41 and
respectively supply enable signals for X-direction to a flip-flop 66 at X0
and X1. The gate circuits 44, 65 generate logic products of the enable
signals in the Y- and X-directions, and the aforementioned EOC signal 60
is obtained through a flip-flop 64. Consequently, in the positive logic,
the EOC signal is at the high level when access is made to the interior of
the rectangle in the auxiliary image shown in FIG. 12.
Then a synthesized image signal obtained from the synthesized image video
signal 50 (B/W(3)), real-time synthesized image run-length signal 53
(RUN-LENGTH(3)) and synthesized image end-of-line signal 59 (EOL(3)) and
encoded by the M-H encoder 45 is stored in the synthesized image memory
8c. The address counter 46 counts the signal EOR(3) for addressing said
memory. Also when the signal EOR(3) is entered consecutively, for example
five times, a completion detecting circuit 47 identifies the end of an
image of a page and terminates the counting action of the address counter
46.
A synthesis start signal XY.sub.S from the AND gate 44 and a synthesis end
signal XY.sub.E from the AND gate 65 are supplied through OR gates 71, 70
to the synthesized image end-of-run-length signal 56 (EOR(3)) in order
that, when the image synthesis is conducted by the inversion of the
channel switching EOC signal 60 during the counting action of run length
by the counter 25 or 28, the run length in said counting action before
said switching is no longer counted but encoded at said switching and
stored in the memory 8c for step advancing the address counter 46. This
operation is called a pre-process for synthesis. The aforementioned
signals XY.sub.S, XY.sub.E are generated corresponding to the synthesizing
positions as shown in FIG. 15.
The run-length counters 25, 28 are respectively reset by the synthesis
start signal XY.sub.S and the synthesis end signal XY.sub.E, in order
that, when the image synthesis is conducted by the inversion of the
channel switching EOC signal 60 during a counting action of run length by
the run-length counter 25 or 28, the run length in the image after said
switching is counted only from said switching to the end of said run
length. This operation is called a post-process for synthesis. These
processes ensure continuity of the image at the channel switching.
The aforementioned pre- and post-processes enable a synthesis in real time
basis of the run-length codes which are non-real-time data.
An initial value setting circuit 67 stores addresses for extracting the
auxiliary image. The memories 35, 36, 40 and 41 initially store the
coordinates Y0, Y1, X0 and X1 defining a rectangle in the auxiliary image
shown in FIG. 12, through the controller 23. Then the image synthesis is
experimentally conducted, and the initial value setting circuit 67 detects
the inversion of the synthesis start signal XY.sub.S to the high level at
(X0, Y0) to stop the run-length counter 28 and the address counter 29,
thereby holding the run length and the address at this point. Then the
coordinates Y0', Y1', X0' and X1' defining a rectangle in the synthesized
image shown in FIG. 12 are stored in the memories 35, 36, 40 and 41. Then
the image synthesis is conducted in the following manner. When the
scanning of the principal image reaches (X0', Y0'), the stopped address
counter for the auxiliary image memory is restarted to release the data of
the auxiliary image starting from (X0, Y0). In this manner a part of the
auxiliary image inside a rectangle defined by X0, X1, Y0 and Y1 as shown
in FIG. 12 is fitted into a rectangular area defined by X0', X1', Y0' and
Y1' in the synthesized image. The synthesis is conducted in a manner as
shown in FIGS. 11 and 12 to obtain the corresponding synthesized image
from the printer 11, wherein A, A' indicate the main image, B, B' the
auxiliary image and C, C' the synthesized image. In this manner the
present invention allows one to extract an image from an arbitrary
position and to fit said image into an arbitrary position of another
image. Also using an entirely white main image, it is possible to extract
a part of the auxiliary image and to move it to an arbitrary position. As
explained in the foregoing, the above-explained embodiment is based on the
change of image position through the hardware structure by controlling the
address counters in response to the data of coordinates. This concept and
some other concepts are applicable not only to the run-length encoded
data.
In case of synthesizing a document image currently read by the CCD 3 with a
stored auxiliary image, the output signal from the run-length encoder 7 is
processed in the similar manner as the processing for the signal from the
main memory, and the controller 23 controls the addresses to interrupt the
output from said main memory. In such case a signal HSYNC to be explained
later corresponds to the start or end of a main scanning by the CCD, and
another signal VSYNC corresponds to the start or end of the auxiliary
scanning i.e. of a page. These signals have equivalent functions also in
the synthesis of two stored images. Furthermore said signals can be made
to correspond to the synchronizing signals for printing laser beam in the
case of printing the synthesized data.
FIG. 3 is a more detailed block diagram principally showing the main image
memory 8a, run-length counter 25 and address counter 26 shown in FIG. 2.
In FIG. 3 the components the same as those in FIG. 2 are represented by
the same numbers. The main image data stored in the main image memory 8a
are decoded by the M-H decoder 24 into the video signal 48 (B/W(1)),
run-length signal 62 (RUN(1)) and end-of-line signal 57 (EOL(1)).
A signal line 73 transmits an enable-of-Huffman signal EOH(1) which is
shifted to the high level when the signals on the signal lines 48, 62 and
57 assume the enabling state. The run-length signal RUN(1) is supplied to
an input port B of a comparator 72, so that counters 25a, 25b
corresponding to the run-length counter shown in FIG. 1 simultaneously
start counting of the clock pulses 2.phi.T at the shifting of said enable
signal EOH(1) to the high level. When the counter 25a counts up to the run
length RUN(1), the output Q of said counter is supplied to the input port
A of the comparator 72 whereby the output port A=B thereof provides a
high-level end-of-run-length signal EOR(1) to a line 54. Simultaneously
the address counter 26 is step advanced, and the counters 25a, 25b are
reset through OR gates 74, 75. After the step advancing of the address for
the memory 8a for releasing the succeeding data and after the completion
of decoding by the M-H decoder 24, the signal EOH(1) is again shifted to
the high level whereby the counters 25a, 25b start to count the run length
corresponding to said succeeding data. Said counters usually function in
the identical manner but the latter alone is reset upon receipt of the
synthesis end signal XY.sub.E through a line 69. In such case the
run-length signal RUN(1) corresponds to the count by said counter 25b
after the entry of said synthesis end signal XY.sub.E, thus performing the
aforementioned post-process. An auxiliary scan synchronizing signal VSYNC
resets the counters 25a, 25b at each end of the scanning in the
X-direction. Also an auxiliary scan enable signal VERT EN assumes the high
level only during the data processing to interrupt the counting action of
the address counter 26 during other periods.
The sequence controller 23 is provided with signal lines 76, 77 for
initializing the address counters, by setting a start address of a desired
image out of plural images stored in the main image memory 8a. A signal
line 156 supplies the count of the address counter 26 into the sequence
controller in order to identify the capacity required for storing an image
in the form of run-length code, and to confirm the size of stored images
and the amount of entire images. FIG. 16 shows an example of a change in
the run length count by the counters 25a, 25b, wherein a main image having
2,000 black bits and 2,000 white bits is synthesized with an auxiliary
image having 3,300 black bits and 700 white bits in the central part
thereof. In this case the synthesized run-length is obtained as 1,000
black bits (1) and 1,000 white bits (3) from the counter 25b. Also 2,000
black bits (2) are selected from the auxiliary image run-length counter
28b. Consequently the synthesized run length becomes composed of 3,000
black bits and 1,000 white bits taking the above-mentioned signals in the
order of (1), (2) and (3).
FIG. 4 is a detailed block diagram of the M-H decoder 24 and the address
counter 26 shown in FIG. 3. The following explanation will be concentrated
on the main image channel as it is identical with the auxiliary image
channel.
The main image memory is for example composed of a structure wherein one
byte is composed of eight bits. A parallel-in-serial-out shift register 78
converts parallel data into serial signals for supply to a shift register
81 through a signal line 94 in response to clock pulses 2.phi.T supplied
through an AND gate 80 when a shift enable signal 93 is at the high level.
The octal counter 26a, constituting the address counter 26 shown in FIG. 3
in combination with the counter 26b, releases a high-level output signal
RCO upon complation of 8-bit shifting of the shift register 78, thereby
shifting said shift register 78 to the data parallel-loading mode through
an inverter 79 and advancing the address counter 26b by one byte.
Consequently, in response to a shift of the shift enable line 93 to the
high level, a series of encoded image signals is supplied, in
synchronization with the clock pulses 2.phi.T, through a signal line 94 to
a serial-in-parallel-out shift register 81 having a length of 13 bits. A
read-only memory (ROM) 83 is provided for converting the modified Huffman
code, which is composed, according to the CCITT standard, of a code word
for a white run, a code word for a black run, and a make-up code. The
output signal from said ROM 83 is composed of a video signal B/W, a
run-length signal R, a make-up code output signal M, an end-of-line signal
EOL and an enable signal EN (EOH).
When the enable signal EN is shifted to the high level. by decoding of the
data, a flip-flop 91 provides a low-level shift-enable signal 93 to close
an AND gate 82, whereby the data shifting is interrupted and the data are
latched in latches 86, 88 through AND gates 87, 89. In case the data
represent a black or white run, the make-up code output signal M assumes
the low level, whereby data selectors 84, 85 select input ports B thereof
to reduce the upper 6 bits to zero and to allot the black or white run
length to the lower five bits. Also if the data represent a make-up code,
the make-up code output signal M assumes the high level whereby the data
selectors 84, 85 select input ports A to reduce the lower 5 bits to zero
and to allot the make-up data to the upper 6 bits. The number of data in
the ROM 83 can be reduced in this manner. Consequently the run-length
signal RUN is composed of 11 bits, in which the upper 6 bits and lower 5
bits are respectively constituted by the output signals from the latches
86 and 88.
A flip-flop 90 detects the enable signal EN from the ROM 83 in
synchronization with the clock pulses 2.phi.T, and releases a high-level
output signal 92 to initiate the counting function of the run-length
counter 25a when gates 87, 89 are opened by the high-level enable signal
EN to fix the outputs from the latches 86, 88. Subsequently, when the
output signal from the run-length counter 25a becomes equal to the
run-length signal RUN on the line 62, the comparator 72 releases a
high-level output signal to reset the counter 25a, to shift the flip-flop
90 to the low-level output for terminating the counting action of the
counter 25a, and to shift the flip-flop 91 to the high-level output for
starting the shift of the succeeding image data. The decoding of the image
data is effected by the repetition of the above-explained procedure.
FIG. 5 is a detailed block diagram corresponding to FIG. 3 and showing
principally the auxiliary image memory 8b, run-length counter 28 and
address counter 29, wherein shown are an enable-of-Huffman signal 95
(EOH(2)); OR gates 96, 97; AND gates 98, 99; an inverter 100; a comparator
101; an inverter 102; an AND gate 103; a flip-flop 104; a data selector
105; and a signal line 106.
This circuit is different from that shown in FIG. 3 by the fact that the
signal EOR(2) is not released by the inverter 102 and the AND gate 103 at
the high-level state of the signal EOL(2), and that an initial value
setting circuit 67, indicated by a broken-lined rectangle, is additionally
provided. In the example shown in FIG. 12, the area to be extracted from
the auxiliary image does not contain the signal EOL therein since said
area is relatively small. However the signal EOL may be detected in case
the extracted area extends to an end of the image or by a certain
erroneous function. The detection of the signal EOL of the auxiliary image
is not desirable since the present embodiment solely depends on the signal
EOL of the main image. For this reason the aforementioned AND gate 103
interrupts the EOR signal, thereby preventing the EOL signal of the
auxiliary image from storage in the synthesized image memory 8c.
In the trial image synthesis phase, an initial value setting signal (X0,
Y0) SET from the sequence controller 23 is at the high level to open the
AND gate 98 in the initial value setting circuit 67, and the data selector
105 controlled by the inverter 100 selects an input B from the flip-flop
104. Consequently the counters 28a, 28b, constituting the run-length
counter 28 shown in FIG. 2, start counting action after the flip-flop 104
is reset by the signal VSYNC, and terminate said counting in response to
the synthesis start signal XY.sub.S for extracting the auxiliary image,
which shifts the output Q of the flip-flop 104 to the low level thereby
shifting the input signal ENP to the counter 28a and the input signal ENT
to the address counter 29 to the low level through the data selector 105
and the AND gate 99. Consequently the address counter 29 and the
run-length counter 28a respectively store an address of the auxiliary data
corresponding to the synthesis start position (X0, Y0) and the
corresponding run-length position when the counting action is terminated.
The main image memory is also scanned in said trial image synthesis phase,
but this causes no incon | | |
