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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a bus linkage unit for connecting a bus of a
computer system with a bus of an expansion box or a bus of another
computer system through a signal transfer path in which the signal mode is
different from that of said buses, and more particularly, a bus linkage
unit for enabling wired-OR signal lines to be connected without
interlocking.
2. Prior Art
When the functions of a conventional personal computer are expanded, it is
conventional to lead out all signal lines of the bus through a connector
or the like to connect to a bus within an expansion box. However, as the
performance of personal computers is more and more sophisticated year
after year, high speed signals increase in these over the bus, and the
number of signal lines significantly increases for the bus, resulting in
the following problems:
(1) The waveforms of signals are distorted as the signal lines, through
which high-speed signals are carried, are extended.
(2) High-speed signals give causes a problem of unnecessary emission.
(3) External noise tends to easily intrude, causing malfunctions.
(4) The increased number of signal lines necessitates using multicontact
connectors.
(5) Use of multicontact connectors tends to lower reliability.
These problems used to put severe restrictions on the extendibility of
sophisticated personal computers. To code with these problems, it is
proposed to link a bus of a computer to a bus of another computer or a bus
of peripheral equipment through a communication link.
For instance, the computer system disclosed in Published Unexamined Patent
Application (PUPA) No. 59071527 is to link a host processor and remote
equipment with one communication link, and to support cycle stealing
transfer.
Also, the system bus data linkage unit disclosed in PUPA No. 3-4351, is to
provide special linkage modules for the respective parallel buses in order
to connect, for example, two parallel buses with a serial link. Thus, when
data is sent from the system initiator of one parallel bus to the system
target of the other parallel bus, the link module of the one parallel bus
simulates the other parallel data, and converts the parallel data into
serial data, which is then sent to the other parallel bus. The link module
of the other parallel bus converts the serial data into parallel data,
simulates the system initiator, and transfers the parallel data to the
system target. In such a configuration as mentioned above where two
systems are connected through a communication path, attention must be paid
to the handling of wired-OR signal lines. That is, in a bus of a personal
computer or the like, negative logic OR is taken on signal lines in some
cases by driving the same signal line with an open collector or open-drain
type drive element so that an unspecified number of devices can transfer a
specific request. An example of such a signal line is the interrupt
request signal line in the bus architecture in the specifications for
MicroChannel (a trademark of International Business Machines Corporation).
If such signal lines are connected through a transfer path in which a
signal mode is different from that of the bus, such as an optical fiber
communication path for example, so that signal levels are simply
transferred with each other and participated in wired-OR by an open
collector at the destination of each communication path, a stiff situation
such as the following is generated (interlock).
(1) In one system, one device drives signal lines to low voltage level,
this level is transferred to the other system through a communication
path, and the signal lines in that system are driven to low voltage level.
Then, the low voltage level of the signal lines of said other system is
transferred to said one system, and the signal lines of said system are
driven to low voltage level. Even if said device stops the low voltage
drive in said one system, signal lines are continued to be driven to low
voltage level sent from the communication path.
(2) The above problem can be prevented through the communication path if
the communication path itself is driving to low voltage level. However, if
separate devices drive the same signal to low voltage at the same time on
both sides of the communication path, there arises such a situation as
that the communication path continuing to drive both sides to low voltage
level occurs.
The following are prior art references relevant to this invention:
IBM Technical Disclosure Bulletin, Vol. 28, No. 6, pp. 2346-2347,
"STACKABLE UNIT PACKAGING CONCEPT," (Nov. 1985): This publication
discloses a technique for connecting signal lines between two functional
units through a connector by putting one functional unit on the housing of
the other functional unit equipped with extendable buses.
IBM Technical Disclosure Bulletin, Vol. 26, No. 10A, pp. 5147 -5152,
"EXTENDED DATA BUS WITH DIRECTION AND ENABLE CONTROL FEATURES," (March
1984): This publication discloses a method of controlling data transfer
directions such that a computer system and an expansion system are linked
in parallel and directions of data transfer are controlled by detecting
from which of the two systems the DMA request in question has been issued.
PUPA No. 56-166536: This gazette discloses a technique for asynchronous
communication between interface buses such that a pair of extenders are
installed between two interface buses, and asynchronous communication
control is exercised between the extenders to establish asynchronous
communication between the interface buses. It also discloses a technique
for connecting two buses in parallel through the use of an optical cable.
IBM Technical Disclosure Bulletin, Vol. 19, No. 8, pp. 3139-3143, "SERIAL
CHANNEL TO I/O INTERFACE," (Jan. 1977): This publication discloses a
serial I/O interface replacing a parallel I/O interface. This interface
allows data to be transferred serially by use of frames or packets each
consisting of a flag and its subsequent serial data.
PUPA No. 3-88055, 1991: This gazette discloses a technique for setting up a
data chain (CCW record) flag and a command chain (CCW record link) flag in
an extender connecting a serial channel to a device on a parallel bus.
Patent application Ser. No. 3-15926: This patent application describes an
invention relating to speeding up serial data transfer between a channel
and a device by use of a microcode routine.
PUPA No. 62-251951: This patent application discloses the invention whereby
a transfer byte count can be included in the command field of an extender
connecting a serial channel with a parallel device.
PUPA No. 2-230356, 1990: This patent application describes a technique for
holding levels in registers and looking in via main system when an
interrupt signal is notified to the main system from an expansion system.
PUPA No. 1-93941, 1989: This patent application describes a technique for
serially transferring a snap shot of parallel signals and holding said
transferred signals in shift registers.
However, none of the above references mentions about the interlock of
wired-OR signal lines that is generated when the buses of two different
systems are connected by a transfer path in which the signal mode is
different from those of the buses.
SUMMARY OF THE INVENTION
Problems to be solved by the invention
The purpose of this invention is to eliminate the interlock of wired-OR
signal lines mentioned above.
Means for solving the problems
This invention adopts the following configuration to achieve the above
purpose. First, a shadow register that acts for the level of a wired-OR
signal line of the other bus is provided in both a first system and a
second system that are connected through a communication path in a signal
transfer mode different from the ordinary bus signal transfer mode. The
levels of wired-OR signal lines of each system are sent to the shadow
registers of the other system through a communication path. When the
shadow register of the system is at a predetermined level, the level of
said wired-OR signal lines will not be sent to the other system. Interlock
is eliminated by avoiding repetition of echoes of level transfer between
both systems in this way. Both systems are, further, provided with
shadow-shadow registers for forming mirror images of the shadow registers
of the other system. Since the level transfer to a shadow register is
prohibited as mentioned above (because the shadow register of the other
system is at a predetermined level), there is a case that a shadow
register is temporarily unable to reproduce the predetermined wired-OR
level. But, the level will be sent to the shadow register of the other
system according to the nonconformity between the level of the
shadow-shadow register of said system and the level of the wired-OR signal
line when the shadow register of said other system is released from the
predetermined level. In this way, levels are reliably transferred to each
other while interlock caused by echoes is avoided.
In addition, when levels are simultaneously transferred, a shadow register
in one system only receives the level while the shadow register of the
other system discards the transferred levels. In this way, interlock
caused by simultaneous transfer can also be avoided. Also in this case,
levels are sent by shadow-shadow registers at an appropriate point later
in time.
DRAWINGS
The following describes an embodiment of this invention with reference to
the relevant drawings:
FIG. 1 is a diagram showing the use mode of an embodiment of this
invention;
FIG. 2 is a block diagram of the overall configuration of the
above-mentioned embodiment;
FIG. 3 is a block diagram of the configuration of the OSMC controller as
the fundamental part of the above-mentioned embodiment;
FIG. 4 is a diagram showing the positional relationship between FIGS. 5 and
6;
FIG. 5 is a block diagram showing the details of the OSMC controller shown
in FIG. 3;
FIG. 6 is a block diagram showing the details of the OSMC controller shown
in FIG. 3;
FIG. 7 is a diagram illustrating the operation of the bus cycle monitor 17
shown in FIG. 5;
FIG. 8 is a diagram illustrating the packet configuration of the
above-mentioned embodiment;
FIG. 9 is a diagram illustrating the types of packets used in the
above-mentioned embodiment;
FIG. 10 is a diagram illustrating the operation of the bus cycle
transmitter 18 shown in FIG. 5;
FIG. 11 is a diagram illustrating the bus cycle receiver 21 shown in FIG.
5;
FIG. 12 is a diagram illustrating the operation of the bus cycle generator
20 shown in FIG. 5;
FIG. 13 is a diagram illustrating the operation of bus cycles;
FIG. 14 is a diagram illustrating the operation of bus cycles;
FIG. 15 is a diagram illustrating the sending sequence of the
above-mentioned packets;
FIG. 16 is a circuit diagram showing the configuration of the modulator 26
shown in FIG. 5;
FIG. 17 is a timing chart of the operation of the modulator 26 shown in
FIG. 5;
FIG. 18 is a circuit diagram showing the configuration of the demodulator
30 shown in FIG. 5;
FIG. 19 is a timing chart of the operation of the demodulator 30 shown in
FIG. 5;
FIG. 20 is a timing chart explaining interruption;
FIG. 21 is a diagram illustrating the operation of the IRQ processor 45;
FIG. 22 is a diagram illustrating the operation of the IRQ processor 45;
FIG. 23 is a block diagram of the detailed configuration of the IRQ
processor 45;
FIG. 24 is a block diagram of the detailed configuration of the IRQ
processor 45;
FIG. 25 is a timing chart showing the outline of arbitration;
FIG. 26 is a block diagram of the detailed configuration of the MSC
processor 46;
FIG. 27 is a block diagram of the detailed configuration of the MSC
processor 46;
FIG. 28 is a timing chart of the operation of the SMC processor 46;
FIG. 29 is a circuit diagram showing the configuration of a local arbiter;
FIG. 30 is a timing chart which explains conventional arbitration by a
local arbiter;
FIG. 31 is a block diagram of the configuration of the remote arbiter 77
shown in FIG. 6;
FIG. 32 is a timing chart which explains the operation of the remote
arbiter 77 shown in FIG. 6; and
FIG. 33 is a timing chart which explains the behavior of the remote arbiter
77 shown in FIG. 6.
DETAILED DESCRIPTION
FIG. 1 shows the use mode of an embodiment of this invention. In the
figure, 1 refers to a notebook-type compact personal computer, which is
connected through an optical fiber assembly 2 to an expansion box 3. This
personal computer 1 may be for example, a PS/55 notebook computer from IBM
Japan, Ltd., which employ a bus conforming to specifications of the
Microchannel (a trademark of International Business Machines Corporation).
The expansion box 3 has slots for the MicroChannel, an SCSI standard slot
(for a DASD), a serial port, a parallel port, and so on.
As shown in FIG. 2, an optical serial card (OSMC) 4 is mounted in the
predetermined slot la of the personal computer 1. The OSMC card 4 is
installed with an electro-opto conversion assembly 5, an OSMC controller
6, and a location map (SRAM) 7. On the other hand, the expansion box 3,
also contains an electro-opto conversion assembly 8, an OSMC, controller
9, and a location map (SRAM) 10. Then, an optical fiber assembly 2 is
connected between the electro-opto conversion assembly 5 and the expansion
box 3. The optical fiber assembly 2 consists of six optical fiber links,
and was a length of, for example, 10 meters. These optical fiber links are
a carrier clock link, a packet link, and an arbitration link transmitting
signals from the personal computer 1 to the expansion box a as well as a
carrier clock link, a packet link, and an arbitration link transmitting
signals from the expansion box 3 to the personal computer 1.
FIG. 3 shows the configuration of the OSMC controller 6 of the OSMC card 4
and the configuration of the OSMC controller 9 of the expansion box. The
OSMC controller 6 has substantially the same configuration as the OSMC
controller 9. In the following, it does not matter which of the two OSMC
controllers is referred to, except when especially necessary. For
convenience of reference, instead, we shall call the one directly referred
to as "the primary" and the other as "the secondary."
In FIG. 3, there is an interface with a bus 11 meeting the MicroChannel
specifications of the primary system on the left side. On the right side,
there are interfaces with an electro-opto conversion assembly 5 (reference
numeral, used being those on the personal computer 1, except when
necessary) and an optical fiber assembly 2 (FIG. 2). An OSMC controller 6,
consists of a bus cycle signal encoder/decoder 12, a miscellaneous signal
encoder/decoder 13, a packet data transmitter-receiver 14, a non-packet
data transmitter-receiver 15, a clock transmitter-receiver 16, and the
like. The signals on bus 11 conform tothe MicroChannel architecture, and
are described in detail at the end of the specification in the section
"Explanation of Signal over MicroChannel Architecture"/ The bus signals
are converted by the bus cycle signal encoder/decoder 12, miscellaneous
signal encoder/decoder 13, packet data transmitter-receiver 14, and
non-packet data transmitter-receiver 15. The resulting signals are then
partially omitted before being sent through the electro-opto conversion
assembly 8 of the primary system to the secondary system. Signals over the
MicroChannel of the secondary system are similarly converted and partially
omitted before being sent through the electro-opto conversion assembly 8
of the secondary system to the primary system.
The optical signals thus sent to the primary system are fed through the
electro-opto conversion assembly 5 of the primary system to the bus cycle
signal encoder/decoder 12, miscellaneous signal encoder/decoder 13, packet
data transmitter-receiver 14, and the non-packet data transmitter-receiver
15, where they are restored to the MicroChannel signals. The optical
signals sent to the second any system are also restored to the
MicroChannel signals.
In the OSMC controller shown in FIG. 3, signals (among other signals)
passing over the MicroChannel which are problematic with respect to a
delay in timing are processed by the non-packet data transmitter 15;
signals relating to bus cycles are processed by the bus cycle signal
encoder/decoder 12 and the packet data transmitter-receiver 14; and the
remaining signals are processed by the miscellaneous signal
encoder/decoder 13 and the packet data transmitter-receiver 14.
Bus cycle signal encoder/decoder
FIGS. 5 and 6 shows the details for FIG. 3. FIG. 4 shows the positional
relationship between FIGS. 5 and 6. FIG. 5, especially, shows the bus
cycle signal encoder/decoder 12 and the packet data transmitter-receiver
14. In the figure, the bus cycle signal encoder/decoder 12 consists of a
bus cycle monitor 17, a bus cycle transmitter 18, an address cache 19, a
bus cycle generator 20, and a bus cycle receiver 21.
Bus cycle monitor
The bus cycle monitor 17 operates as shown in FIG. 7, with the following
states of operation:
State 0; idle state
Makes a transition to state 2 if -S0 or -S1 is asserted.
State 1; address is valid
Makes a transition to state 2 if -ADL is asserted and address is detected
on the location map 7. Makes a transition to state 0 if -S0 and -S1 are
negated.
State 2; the bus cycle transmitter 18 is kicked if the bus cycle is a
secondary bus cycle.
Makes a transition to state 3 if -CMD is detected.
State 3; write data is valid if the cycle is a write cycle.
Makes a transition to state 0 if -CMD is negated.
Bus cycle transmitter
The bus cycle transmitter 18 requests the packet data transmitter-receiver
14 to packetize MicroChannel signals relating to a bus cycle started at
the primary system and to be completed at the secondary system and to
transfer packets. The packet data transmitter-receiver 14 generates a
packet in reply to a request for signal transfer and transmits the packet
to the secondary system. The packet thus transmitted to the secondary
system is used to regenerate MicroChannel signals. As shown in FIG. 8, a
packet consists of a command field, an argument field, and a compensation
field, which are each composed of 10 bits. The types of commands are as
shown in FIG. 9. The argument field is buried with an address and transfer
data. The compensation field is buried in a packet when no other field is
transferred. The null argument in the compensation field takes one of a
plurality of specific bit patterns. It is arranged to eliminate direct
current in the transferred signals by appropriately selecting a bit
pattern for the null argument. The packet transmitter-receiver 14 will be
detailed later.
The bus cycle transmitter 18 is arranged to be able to eliminate the
transfer of address information by taking advantage of the locality of bus
cycle addresses. That is, the address cache 19 is designed so that it can
store a previous bus access address, in order that the command field
contains the corresponding information if the difference between the
current address and the previous address is 0, 1, or 2 and the transfer of
the previous address is eliminated instead.
The bus cycle transmitter 18 operates as shown in FIG. 10, with the
following states of operation:
State 0; idle state
Makes a transition to state 1 if the bus cycle monitor 17 detects a bus
cycle
State 1; accesses the address cache 19 and compares a bus address with a
cache address.
If the bus address minus the cache address is 0, +1, or +2, a cache hit is
scored; otherwise, a cache miss is scored.
If the bus cycle monitor activates the bus cycle transmitter 18, a
transition is made to state 2. Otherwise, a transition is made to state 0.
State 2; requests to send a command packet, and negates CDCHRDY.
The address cache 19 is updated.
If a cache hit is scored and a read operation is performed, a transition is
made to state 5.
If a cache hit is scored and a write operation is performed, a transition
is made to state 4.
If a cache miss is scored, a transition is made to state 3.
State 3; requests to send an address packet.
If a read operation is performed, a transition is made to state 5.
If a write operation is performed, a transition is made to state 4.
State 4; requests to send a data packet and makes a transition to state 5.
State 5; Waits for the completion of a bus cycle sent to the secondary
system.
A transition is made to state 6 if an acknowledgement of the secondary bus
cycle is returned.
State 6; asserts CDCHRDY
If a read operation is performed, returned data is output.
A transition is made to state 0.
Bus cycle receiver
The bus cycle receiver 21 activates the bus cycle generator 20 according to
information about bus cycles to be transferred from the secondary system
to the primary system to reproduce the bus cycle signals of the secondary
system in the primary system. The packet data transmitter-receiver 14
decodes packets from the secondary system and sends them to a bus cycle
receiver 21. The bus cycle receiver 21 generates addresses by reference to
the address cache 19, if necessary, and feeds the addresses to the bus
cycle generator 20. The bus cycle receiver 21 also requests the packet
data transmitter-receiver 14 to send an ACK packet to the primary system
when the bus cycle sent from the secondary system to the primary system is
about to be completed.
The bus cycle receiver 21 operates as shown in FIG. 11, with the following
states of operation:
State 0; idles state
Makes a transition to state 1 if a primary bus cycle command is identified.
State 1; calculates effective address by use of the cache state data of the
command packet.
If the address incremental value is 11, the corresponding cache address is
discarded.
State 2; completes the reception of the command packet.
If a parity error is detected, a transition is made to state 1 and an error
flag is set.
If a cache hit is scored, the bus cycle generator 20 is kicked and the
address cache 19 is updated.
If a cache hit is scored and a read operation is performed, a transition is
made to state 5.
If a cache hit is scored and a write operation is performed, a transition
is made to state 4.
If a cache miss is detected, a transition is made to state 3.
State 3; receives an address packet. After all the addresses are received,
the bus cycle generator 20 is kicked and the address cache 19 is updated.
If a read operation is performed, a transition is made to state 5.
If a write operation is performed, a transition is made to state 4.
State 4; receives a data packet and makes a transition to state 5.
State 5; waits until a bus cycle sent to the secondary system is about to
end.
If the bus cycle generator 20 makes notification that a bus cycle is about
to end, a transition is made to state 6.
State 6; makes a request to send an ACK packet for a bus cycle started in
the secondary system.
If a read operation is to be performed, a request is made to send a packet
of read data.
A transition is made to state 0.
Bus cycle generator
The bus cycle generator 20 reproduces a bus cycle started in the secondary
system in the primary system. When the bus cycle generator 20 becomes
ready to output an effective address, the bus cycle receiver 21 activates
the bus cycle generator 20. Signals over the MicroChannel of the primary
system to the bus cycle reproduced by the bus cycle generator 20 are sent
to the MicroChannel bus 11 of the secondary system.
The bus cycle generator 20 operates as shown in FIG. 12, with the following
states of operation:
State 0; idle state
If the generator 20 is kicked by the bus cycle receiver, a transition is
made to state 1.
State 1; asserts -S0 or -S1 and makes a transition to state 2.
State 2; asserts -ADL.
If a read operation is performed, a transition is made to state 3.
If a write operation is performed, a transition is made to state 3 as soon
as data arrives.
State 3; negates -ADL and asserts -CMD.
It samples CHRDYTN and distinguishes between a default cycle and an
extended cycle.
State 4; negates -S0 or -S1.
If the cycle is a default cycle, a state transition to state 6 is made 40
ns later than the assertion of -CMD.
If the cycle is an extended cycle, a state transition to state 6 is made
140 ns later than the assertion of -CMD if CHRDYRTN is at high voltage
level, or to state 5 if CHRDYRTN is low voltage level.
State 5; asynchronous extended cycle.
A transition is made to state 6 as soon as CHRDYRTN becomes high voltage
level.
State 6; notifies the bus cycle receiver 21 that it is ready to return an
ACK.
A transition is made to state 7, 60 ns later.
State 7; terminates the bus cycle.
If the bus cycle is not a DMA IO cycle, it negates--CMD and goes to state
0.
If the bus cycle is a DMA IO cycle, the generator 20 waits until -TC is
received, or negates -CMD after receiving the end of -CMD over the
secondary bus through an arbitration link, and then goes to state 0.
FIGS. 13 and 14 show how the primary system gains 16-bit write and read
access to the secondary system. In view of the fact that much of the
operation of each individual functional block has been described so far,
detailed explanations of those individual functional blocks are omitted
here.
Packet data transmitter-receiver
The packet data transmitter-receiver 14 will be described packet data
transmitter-receiver 14 has a packet prioritizer 22, a packet encoder 23,
a serializer 24, a mark/space compensator 25, modulator 26, a decoder 27,
a deserializer 28, a phase-locked-loop (PLL) 29, and a demodulator 30.
The packet prioritizer 22 requests the packet encoder 23 to generate
packets in such a priority as shown in FIG. 15. The packet encoder 23
generates packets in response to a request for packet generation from the
packet prioritizer 22. Each 10-bit packet field is fed into the serializer
24 through which they are to be output as a pair of 5-bit stream. Such
pair of bit stream is fed into the modulator 26, from which one bit of
each bit pair is sequentially output to the driver 27 for the electro-opto
conversion assembly 5 at the falling edge of a clock pulse, and the other
bit of each bit pair is similarly output to the driver 17 at the rising
edge. The output from the modulator 26 is fed through the electro-opto
conversion assembly 5 and the optical fiber assembly 2 to the secondary
system.
The mark/space compensator 25 is provided to reduce the direct current of
signals over a data line by use of a null data field for compensation.
When there are excessive marks (`1`s), a null data field including
excessive spaces (`0`s) is inserted, whereas a null data packet including
excessive marks is inserted when there are excessive spaces.
As shown in FIG. 16, the modulator 26 consists of a buffer 28a, an inverter
29a, latches 30a, 31, 32, AND circuits 33, 34, and an OR circuit 35. The
modulator 26 is fed with clock pulses from the clock pulse generator 36 of
the clock transmitter-receiver 16 along with a transfer bit pair, Xbit0
and Xbit1. These clock pulses are turned through the buffer 28a to XBclock
pulses that control gates 31 and 32 and the AND circuit 34. These clock
pulses are also turned through the inverter 29a to XCclock pulses that
control the latch 30a and the AND circuit 34. The transfer bit pair, Xbit0
and Xbit1, are merged into an X bit stream which is then fed through the
driver 27 to the electro-opto conversion assembly 5, as shown in FIG. 17.
Clock pulses generated by the clock pulse generator 36 are turned through
the inverter 37 to transfer clock XCLOCK pulses, which are then fed to the
electro-opto conversion assembly 5 before being sent to the secondary
system for demodulation of transmission signals. As apparent from FIG. 17,
the bit rate of transfer data is set at twice that of those clock pulses.
Accordingly, a relatively slow circuit is acceptable as the one relating
to the clock generation.
Each bit stream from the secondary system is converted by the demodulator
30 into a stream of bit pairs and then converted by the deserializer 28
into a packet field, which is fed to the packet decoder 27. The PLL unit
29 is used to detect synchronization of a packet field and extract the
packet field. The packet decoder 27 feeds the bus cycle receiver 21 of the
bus cycle encoder/decoder 12 and the IRQ receiver 38 and MSC receiver 39
of the miscellaneous signal encoder/decoder 13 with control signals and
data appropriate to each packet so that signals over the MicroChannel of
the secondary system should be sent to the primary MicroChannel bus 11.
As shown in FIG. 18, the demodulator 30 consists of a buffer 40, an
inverter 41, and latches 42, 43, 44. As shown in FIG. 19, the demodulator
30 demodulates R bit streams sent from the primary system and streams of
bit pairs from RCLOCK.
Miscellaneous signal encoder/decoder
The miscellaneous signal encoder/decoder is described in reference to FIG.
6 and the like.
In FIG. 6, the miscellaneous signal packet encoder/decoder 13, which
processes the -IRQn, CHRESET, and -PREEMPT signals, consists of and IRQ
processor 45 and an MSC (miscellaneous) processor 46.
IRQ processor
The IRQ processor 45 consists of an IRQ shadow register 46, an IRQ
shadow-shadow register 47, an IRQ prioritizer 48, an IRQ transmitter 49,
and an IRQ receiver 50.
To facilitate understanding, the -IRQn signal is described here. The
"-IRQn" signal includes not only proper interrupt request signals, -IRQ3
to -IRQ7, -IRQ9 to -IRQ12, -IRQ14 and -IRQ15, but also the -CHCK signal
for the sake of convenience. These signals are active-low wired-OR type
signals driven by open-collector-type drive elements. For example, as
shown in FIG. 20, when a particular peripheral device (an adapter)
requests an interrupt for an MPU, the -IRQn line assigned to the
peripheral device is driven to its low (low voltage level) state (A). A
peripheral interrupt controller (PIC; not shown) then detects this signal,
sends an interrupt request (-INT) to the MPU (B), and sets an in-service
register (C). The MPU then executes a corresponding interrupt processing
routine. On termination of the interrupt processing routine, the MPU makes
notification of the end of interrupt (EOI) to the adapter of the
peripheral device so that to drive the -IRQn line to its high (high
voltage level) state (D). The MPU notifies of an EOI to the in-service
register of peripheral interrupt controller so that to enable another -INT
(E). The MPU then terminates the interrupt processing routine and proceeds
to the next process (F).
To transmit the level of a -IRQn line between the primary system and the
secondary system it is necessary to take account of the following factors:
first, an echo causes the low level driving not to be released
permanently. That is, when a -IRQn line is driven to its low state by a
peripheral device in one system, the signal is transferred to the other
system and the corresponding -IRQn line is driven to its low state by the
IRQ processor, if the IRQ processor in the second system echos back the
low state of the -IRQn line of the second system, the -IRQn line of the
first system is driven low by the IRQ processor as well as the peripheral
device, thus the -IRQn lines of both systems are driven low permanently
even if the peripheral device receives an EQI (end of interrupt); second,
a similar lock-up state results from peripheral devices of both systems
driving the same -IRQn lines at almost the same time and the low-driven
state being transferred to each other.
In this embodiment, a shadow register 46 is provided for each -IRQn line
which represents the state of an -IRQn line of the secondary system.
Moreover, when the shadow register indicates the low-driven state of the
-IRQn line of the secondary system, no notification is sent to the
secondary system even if a -IRQn line of the primary system is driven to
its low state. The low-driven state thus not notified will be sent again
later after drawing a comparison with the shadow-shadow register 47. This
point will be described in detail later. By doing so, the notification of
a low-driven state will not produce any echo, so that the problem of
locking-up by an echo will be resolved.
To represent the level of a -IRQn line of the secondary system by the
shadow register 46 of the primary system, it is necessary to send an IRQ
packet from the secondary system to the primary system whenever the level
of the -IRQn line of the secondary system is toggled.
A second problem is solved by a communication protocol. First, the
secondary system returns a response packet to an IRQ packet sent from the
primary system. If an IRQ packet is sent from the secondary system when a
response packet is not yet received after an IRQ packet is sent from the
primary system, it is regarded as simultaneous transmission of IRQ
packets. In this case, one system (the personal computer 1, for example)
toggles the shadow register in response the IRQ packet and sends a
positive acknowledgement (ACK) to the other system. The other system
(expansion box 3, for example) rejects the IRQ packet and sends a negative
acknowledgement (NAK) to the one system. On the part of the other system,
neither the shadow register nor its counterpart shadow-shadow register is
toggled because the IRQ packet is rejected. Thus, the simultaneous high to
low transition of the outputs of both shadow registers inverted by the
inverters 57 is avoided, and thus the second problem is solved as well.
If the low-driven state of the primary system is not reflected in the
secondary shadow register 46 on account of the denial as described above,
notification to the secondary system of the low-driven state is again made
by use of the primary shadow-shadow register 47. That is, the primary
shadow-shadow register 47 is so designed that it will toggle in response
to an ACK from the secondary system and maintain the state in response to
an NAK. Consequently, the primary shadow-shadow register 47 operates as a
mirror image of the secondary shadow register 46. Also, if no notification
from the primary system to the secondary system has been rejected, the
secondary shadow register 46 operates as a mirror image of the primary
-IRQn line. Accordingly, if the state of the primary -IRQn line agrees
with the state of the shadow-shadow register 47, the given notification
has been accepted positively and therefore it is not necessary to send
notification again.
By contrast, if the state of the primary -IRQn line is different from that
of the primary shadow-shadow register 47, it is because the notification
is rejected. In this case, the secondary system is again notified of the
primary system's low-drive state after the primary shadow register 46 has
recovered from the low-driving state.
FIG. 21A shows the operation of the -IRQn line in its high state at the
outset being toggled to the low state only in the primary system. In FIG.
21A, as the level adapter of the -IRQn line is toggled from the high state
to the low state, the wired-OR type -IRQn line goes low (1). Then an IRQ
packet is sent from the primary system to the secondary system, so that
the inverted output by inverter 57 of the secondary shadow register 46 is
toggled from the high state to the low state (2). In response to this
toggle, an ACK is returned from the secondary system to the primary
system, so that the primary shadow-shadow register 47 is toggled from the
high indication state to the low indication state (3). In this case, the
secondary -IRQn line is similarly toggled to the low indication state as
the inverted output by the inverter 57 of the secondary shadow register 46
has been toggled (4). However, in view of the fact that the inverted
output by the inverter 57 of the secondary shadow register 46 is already
low, no IRQ packet is sent to the primary system as the secondary -IRQn
line is toggled to low state (5).
FIG. 21B shows the operation of the primary -IRQn line being returned from
the state shown in FIG. 21A to the high state. In FIG. 21B, the wired-OR
type -IRQn line goes high as the adapter toggles the -IRQn line from the
low state to the high state (1). Then an IRQ packet is sent from the
primary system to the secondary system (an IRQ packet is sent because the
shadow-shadow register 47 still remains in its low indication state when
the -IRQn line has gone high, or the secondary shadow register 46 does not
yet represent the primary IRQn line.), so that the secondary register 46
is toggled from the low indication state to the high indication state (2).
Then, in response to this toggle, the secondary system returns an ACK to
the primary system, so that the primary shadow-shadow register 47 is
toggled from the low indication state to the high indication state (3). In
this case, the secondary -IRQn line also is turned from the low indication
state to the high indication state in response to the toggle of the
secondary shadow register 46 (4). However, since the secondary
shadow-shadow register 47 also is in its high indication state, or the
primary shadow register 46 is in the high indication state, no IRQ packet
is sent to the primary system in response to the toggle of the secondary
-IRQn line.
FIG. 22A shows the operation of the -IRQn lines in both the primary and
secondary systems bei | | |
