Ions of arsenic are selectively implanted at a high concentration into a substrate through a first passivation film of silicon dioxide to obtain a shallow junction, thereby forming a source region with a low resistivity and a first drain region. Then, after the first passivation film is removed, a second passivation film of silicon dioxide is deposited over the substrate as well as over a stacked cell electrode by a CVD process performed at a relatively low temperature. Thereafter, the substrate is annealed in a nitrogen ambient at such a temperature as activating the dopant introduced. In this manner, the dopant in source region and first drain region is activated.

A two step source/drain annealing process which permits a dopant to be ion implanted directly into the silicon without a protective oxide. The gate oxide is removed before the ion implantation of the dopant occurs, thus the dopant is implanted directly into bare silicon. In a first step of the annealing process, a thin oxide is grown over the source and drain regions at a relatively low temperature (e.g., 600.degree. C.) this temperature to prevent the evaporation of the dopant from the silicon substrate and polysilicon gate. The second step of the annealing process occurs at a higher temperature allowing the dopant to be driven into the substrate forming the source and drain regions.

A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution. As a result, particularly, a miniaturized PMOS with a larger current, punch-through hard and an ultra miniaturized configuration is achieved, and this can be applied also to NMOS, and, therefore, a CMOS with a larger current, punch-through hard and a more miniaturized configuration can be achieved without complicating the fabrication steps, namely, economically.

The invention provides a method for fabricating ultra-shallow, low resistance junctions. In the preferred embodiment, a nitrogen containing screen oxide layer is formed on an undoped area of a substrate by poly re-oxidation using rapid thermal processing in a nitrogen containing atmosphere. Impurity ions are implanted into the substrate, in the undoped area, through the nitrogen containing screen oxide layer to form lightly doped source and drain regions. A post-implant anneal is performed on the lightly doped source and drain regions using a rapid thermal anneal in a nitrogen containing atmosphere. The nitrogen containing screen oxide layer: prevents surface dopant loss during post implant anneal; prevents gate oxide degradation during ion implantation and screen oxide stripping; and acts as a diffusion barrier, reducing oxygen enhanced diffusion. Alternatively, the poly re-oxidation can be performed in an O.sub.2 atmosphere followed by a rapid thermal anneal in a nitrogen containing atmosphere.

A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.