A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs. The clamping performed by the invention reduces wearout and other deleterious effects of excess voltage.
A method of simulating hot carrier deterioration of a P-MOS transistor uses the following formulas (A1), (A2), (A3) and (A4) or the following formulas (A1), (A5), (A3) and (A4) (A2), and coefficients A, n, B and m are determined by a preliminary measuring experiment, whereby a transistor lifetime r can be estimated:
The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source of at least one transistor of a field effect transistor integrated circuit. The use of one or more Schottky barriers is useful for reducing the susceptibility of latch-up for circuits having two opposite type transistors, i.e., two opposite polarity carriers, in which the two transistors are in close enough proximity to experience latch-up. This can allow the spacing between n- and p-type transistors to be reduced, thus reducing the area of the circuit. The subject invention can also allow the elimination of a metal contact by utilizing the metal layer used to form the metal-semiconductor junction in a complementary IGFET structure, to further reduce the circuit area. The subject invention is applicable to complementary metal oxide silicon (CMOS) devices. Advantageously, the manufacturing process required to produce the subject devices can require minimal adjustments to the standard processing steps used in conventional CMOS processing.
A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a snapback device during normal operation, but do not substantially affect triggering of the device during an unbiased electrostatic discharge event. Minority carrier injection from n+ devices is substantially reduced, and the circuit may also be used to clamp an oxide voltage in a thin oxide semiconductor device.
A method of designing improved CMOS input circuits by understanding and selecting appropriate drive strength for a CMOS output from a previous stage. The method involves modeling the net using HSPICE and including a transit time term to accurately model charge storage, then size drivers as needed to keep the V.sub.ss clamps out of forward conduction. Excessive ringing can cause data errors in the input stage if unterminated, falling edge transitions in such a net can turn on a receiver's V.sub.ss clamp diode (stored charge in the V.sub.ss clamp diode combined with the line's inductance and the receiver's capacitance form an energized resonant circuit which can release energy at a time to cause a data glitch). Currently, XNS simulation miscalculates the ring amplitude by a factor of three. Driver scaling and termination can eliminate the problem by keeping the receiver's V.sub.ss clamp out of forward conduction. Driver sizing can control the problem. Lower current will turn the clamp on for a shorter amount of time, and change the position of the ring. Improved modeling or simulation can allow selection of correct driver sizes and other circuit elements.
A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a snapback device during normal operation, but do not substantially affect triggering of the device during an unbiased electrostatic discharge event. Minority carrier injection from n+ devices is substantially reduced, and the circuit may also be used to clamp an oxide voltage in a thin oxide semiconductor device.
