A self-timed data streaming receiver for a routing chip. Incoming flits are received by a distributor that distributes the flits between two self-timing FIFOs. A collector coupled to both FIFOs at their opposite ends takes the two streams of flits and recreates the original stream of flits prior to coupling the flits to routing control circuitry. A self-timed data streaming transmitter is also described.
A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.
