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Claims  |
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What is claimed is:
1. A bus bridge for transferring data between a first bus and a second bus in a computer system, the bus bridge comprising:
a first bus interface coupled to the first bus for receiving data from and placing data onto the first bus;
a second bus interface coupled to the second bus for receiving data from and placing data onto the second bus;
an inbound request queue and an outbound request queue coupled to the first bus interface and the second bus interface;
decoding circuitry coupled to the inbound request queue and the outbound request queue for placing requests in the outbound request queue and for issuing a deferred response to the first bus interface to be placed on the first bus based on
available space in the inbound request queue; and
an inbound queue allocation unit for determining whether an outbound request may be given the deferred response.
2. The bus bridge as defined in claim 1 further comprising at least one data buffer coupled to the inbound request queue and the outbound request queue.
3. The bus bridge as defined in claim 1 wherein the inbound request queue has a plurality of inbound slots and the inbound queue allocation unit determines whether the outbound request may be given the deferred response based on a total number
of inbound slots, a number of inbound slots in the inbound request queue currently holding information, and a number of inbound slots in the inbound request queue currently labeled as deferred reply slots.
4. The bus bridge as defined in claim 1 further comprising bus control circuitry coupled to the first bus interface and the second bus interface, the bus control circuitry for determining whether an outbound request has been deferred,
transferring the outbound request to the second bus interface, receiving response information from the second bus interface generated in response to the outbound request, and
returning the response information to the first bus interface if the outbound request has not been deferred, and
transferring the response information to the inbound request queue if the outbound request has been deferred.
5. The bus bridge as defined in claim 4 further comprising a deferred reply generator for receiving response information from the bus control circuitry and transferring the response information to the inbound request queue.
6. The bus bridge as defined in claim 1 further comprising bus target circuitry for receiving inbound requests from the second bus interface and transferring the inbound requests to the inbound request queue.
7. The bus bridge as defined in claim 1 wherein the outbound request queue has a plurality of outbound slots, and wherein each slot of the plurality of outbound slots contains information corresponding to requests issued by agents coupled to the
first bus.
8. The bus bridge as defined in claim 1 wherein the inbound request queue has a plurality of inbound slots, and wherein each slot of the plurality of inbound slots stores information corresponding to requests issued by agents coupled to the
first bus or the second bus.
9. The bus bridge as defined in claim 8 wherein at least one of the plurality of inbound slots is a deferred reply slot.
10. The bus bridge as defined in claim 1, wherein:
the first bus has a first command protocol;
the second bus has a second command protocol; and
the second bus interface is for translating commands between the first command protocol and the second command protocol.
11. The bus bridge as defined in claim 7, wherein each slot of the plurality of outbound slots comprises a tag portion, a command portion, an address portion, and a data pointer portion.
12. The bus bridge as defined in claim 8 wherein each slot of the plurality of inbound slots comprises a command portion, an address portion, and a data pointer portion.
13. A bus bridge for transferring data between a first bus and a second bus in a computer system, the bus bridge comprising:
a first bus interface coupled to the first bus for receiving data from and placing data onto the first bus;
a second bus interface coupled to the second bus for receiving data from and placing data onto the second bus;
an inbound request queue and an outbound request queue coupled to the first bus interface and the second bus interface, wherein the inbound request queue has a plurality of inbound slots, and wherein each slot of the plurality of inbound slots
stores information corresponding to requests issued by agents coupled to the first bus or the second bus; and
decoding circuitry coupled to the inbound request queue and the outbound request queue for placing requests in the outbound request queue and for issuing a deferred response to the first bus interface to be placed on the first bus based on
available space in the inbound request queue, wherein the decoding circuitry determines whether to issue the deferred response to the first bus interface based on whether each inbound slot of the plurality of inbound slots contains information, the
decoding circuitry issuing the deferred response to the first bus interface if an inbound slot does not contain information.
14. The bus bridge as defined in claim 11 wherein the tag portion identifies whether a request has been deferred.
15. A method for transferring a command between a first bus and a second bus using a bus bridge, the bus bridge including an inbound request queue and an outbound request queue, the method comprising the steps of:
(a) transferring a first outbound request from a source agent on the first bus to the outbound request queue;
(b) determining whether the first outbound request is to be deferred;
(c) issuing a deferred response to the source agent and reserving a slot in the inbound request queue when the first outbound request is deferred;
(d) transferring the first outbound request from the outbound request queue to a target agent on the second bus; and
(e) returning response information from the target agent to the source agent if the first outbound request is not deferred, and placing the response information from the target agent into the inbound request queue if the first outbound request is
deferred.
16. The method of claim 15 wherein the step (d) comprises removing the first outbound request from the outbound request queue and transferring the first outbound request to a second bus interface.
17. The method of claim 15 wherein the step (c) comprises:
determining a number of slots in the inbound request queue;
determining a number of slots in the inbound request queue which are not currently in use;
determining a number of slots in the inbound request queue which are currently labeled as deferred reply slots; and
issuing the deferred response if an inbound slot exists which is not in use and fewer than a predetermined number of inbound slots are labeled as deferred reply slots.
18. The method of claim 15 wherein the step (d) comprises translating the first outbound request from a first command protocol to a second command protocol.
19. The method of claim 15 further comprising transferring a second outbound request from the outbound request queue to a second target agent on the second bus and transferring response information for the second outbound request to the source
agent before the response information for the first outbound request is transferred to the inbound request queue.
20. The method of claim 15 wherein the step (e) comprises placing response data in a data buffer if the target agent returns response data, the inbound request queue containing an indicator denoting a location of the data buffer.
21. The method of claim 15 wherein the step (c) comprises determining whether a deferred reply slot in the inbound request queue is available and issuing the deferred response if the deferred reply slot in the inbound request queue is available.
22. A computer system comprising:
a bus bridge for transferring data between a first bus and a second bus;
the first bus for transferring data between a first agent coupled to the first bus and the bus bridge;
the second bus for transferring data between a second agent coupled to the second bus and the bus bridge; and
the bus bridge including,
a first bus interface coupled to the first bus for receiving data from and placing data onto the first bus,
a second bus interface coupled to the second bus for receiving data from and placing data onto the second bus,
an inbound request queue and an outbound request queue coupled to the first bus interface and the second bus interface,
decoding circuitry coupled to the inbound request queue and the outbound request queue for placing requests in the outbound request queue and for issuing a deferred response to the first bus interface to be placed on the first bus based on
available space in the inbound request queue, and
an inbound queue allocation unit for determining whether an outbound request may be given the deferred response.
23. The computer system as defined in claim 22 wherein the inbound request queue has a plurality of inbound slots and the inbound queue allocation unit determines whether the outbound request may be given the deferred reply based on a total
number of inbound slots, a number of inbound slots in the inbound request queue currently holding information, and a number of inbound slots in the inbound request queue currently labeled as deferred reply slots.
24. The computer system as defined in claim 22 wherein the bus bridge further comprises bus control circuitry coupled to the first bus interface and the second bus interface, the bus control circuitry being for determining whether an outbound
request has been deferred, transferring the outbound request to the second bus interface, receiving response information from the second bus interface generated in response to the outbound request, and
returning the response information to the first bus interface if the outbound request has not been deferred, and
transferring the response information to the inbound request queue if the outbound request has been deferred.
25. The computer system as defined in claim 22 wherein the bus bridge further comprises bus target circuitry for receiving inbound requests from the second bus interface and transferring the requests to the inbound request queue.
26. The computer system as defined in claim 22 wherein the outbound request queue has a plurality of outbound slots, and wherein each slot of the plurality of outbound slots holds information corresponding to requests issued by agents coupled to
the first bus.
27. The computer system as defined in claim 26, wherein each slot of the plurality of outbound slots comprises a tag portion, a command portion, an address portion, and a data pointer portion.
28. The computer system as defined in claim 22 wherein the inbound request queue has a plurality of inbound slots, and wherein each slot of the plurality of inbound slots stores information corresponding to requests issued by agents coupled to
the first bus or the second bus.
29. The computer system as defined in claim 28 wherein each slot of the plurality of inbound slots comprises a command portion, an address portion, and a data pointer portion.
30. A computer system comprising:
a bus bridge for transferring data between a first bus and a second bus;
the first bus for transferring data between a first agent coupled to the first bus and the bus bridge;
the second bus for transferring data between a second agent coupled to the second bus and the bus bridge; and
the bus bridge including,
a first bus interface coupled to the first bus for receiving data from and placing data onto the first bus,
a second bus interface coupled to the second bus for receiving data from and placing data onto the second bus,
an inbound request queue and an outbound request queue coupled to the first bus interface and the second bus interface, wherein the inbound request queue has a plurality of inbound slots, and wherein each slot to the plurality of inbound slots
stores information corresponding to requests issued by agents coupled to the first bus or the second bus, and
decoding circuitry coupled to the inbound request queue and the outbound request queue for placing requests in the outbound request queue and for issuing a deferred response to the first bus interface to be placed on the first bus based on
available space in the inbound request queue, wherein the decoding circuitry determines whether to issue the deferred response to the first bus interface based on whether each inbound slot of the plurality of inbound slots contains information, the
decoding circuitry issuing the deferred response to the first bus interface if an inbound slot does not contain information.
31. An apparatus for transferring commands between a first bus and a second bus, the apparatus including an inbound request queue and an outbound request queue, the apparatus comprising:
means for transferring a first outbound request from a source agent on the first bus to the outbound request queue;
means for determining whether the first outbound request is to be deferred;
means for issuing a deferred response to the source agent and reserving a slot in the inbound request queue when the first outbound request is deferred;
means for transferring the first outbound request from the outbound request queue to a target agent on the second bus; and
means for returning response information from the target agent to the source agent if the first outbound request is not deferred, and placing the response information from the target agent into the inbound request queue if the first outbound
request is deferred.
32. The apparatus as defined in claim 31 wherein the means for transferring comprises means for removing the first outbound request from the outbound request queue and transferring the first outbound request to a second bus interface.
33. The apparatus as defined in claim 31 wherein the means for issuing a deferred response comprises:
means for determining a number of slots in the inbound request queue;
means for determining a number of slots in the inbound request queue which are not currently in use;
means for determining a number of slots in the inbound request queue which are currently labeled as deferred reply slots; and
means for issuing the deferred response if an inbound slot exists which is not in use and fewer than a predetermined number of inbound slots are labeled as deferred reply slots.
34. The apparatus as defined in claim 31 wherein the means for transferring the first outbound request from the outbound request queue to a target agent on the second bus comprises means for translating the first outbound request from a first
command protocol to a second command protocol.
35. The apparatus as defined in claim 31 further comprising means for transferring a second outbound request from the outbound request queue to a second target agent on the second bus, and transferring response information for the second
outbound request to the source agent before the response information for the first outbound request is transferred to the inbound request queue.
36. The apparatus as defined in claim 31 wherein the means for returning further comprises means for placing response data in a data buffer if the target agent returns response data, the inbound request queue containing an indicator denoting a
location of the data buffer.
37. The apparatus as defined in claim 31 wherein the means for issuing a deferred response comprises means for determining whether a deferred reply slot in the inbound request queue is available and issuing the deferred response if the deferred
reply slot in the inbound request queue is available. |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the field of data transfer in a computer system. More particularly, this invention relates to bus bridges which transfer information between multiple buses while maintaining transaction ordering and supporting
deferred replies.
2. Background
Modern computer systems generally include multiple agents, such as microprocessors, storage devices, display devices, etc. which are interconnected via a system bus. The system bus operates to transfer address, data and control signals between
these agents. Some modern computer systems employ multiple buses, in which various agents are coupled to one or more buses. Typically, each agent is coupled to a single bus.
Bus bridges are often utilized in multiple-bus systems to connect the buses and thereby allow agents coupled to one bus to access agents coupled to another bus. The function of the bridge typically involves transferring commands between two
buses. The commands transferred by the bus bridge frequently have data associated with them (e.g., read or write commands).
One problem which frequently arises in computer systems with multiple agents is the need to preserve transaction ordering. Support for transaction ordering implies that if an agent writes to location A in memory followed by a write to location B
in memory, another agent cannot read the new data in location B and stale (i.e., old) data in location A. A number of software algorithms require a producer-consumer relationship and thus depend on this support to ensure proper functionality. For
example, in a system comprising multiple processors, assume that processor P1 is a producer of information and processor P2 is a consumer of information. P1 performs a write operation W1 to location 1 followed by a write operation W2 to location 2.
Location 2 contains a flag variable that signals that the data in location 1 is valid. Processor P2 continuously performs a read operation R2 on location 2 until the flag becomes valid. After the flag is observed valid, P2 performs a read operation R1
on location 1 to read the data. In order for this algorithm to successfully execute in a multiprocessor system, the order in which W1 and W2 are written by processor P1 should be the same order in which R1 and R2 appear to be updated to processor P2.
A bus bridge in a multiple-bus system must address the problem of transaction ordering. In the example above, processors P1 and P2 may be coupled to one bus while locations 1 and 2 are coupled to a second bus, and a bus bridge is supporting
access between the two buses. Thus, the bus bridge must ensure that transaction ordering is maintained. That is, the order in which W1 and W2 are written by an agent(s) should be maintained by the bus bridge.
One method of maintaining transaction ordering is shown in FIG. 1. A bus bridge 100 is shown which interfaces between two buses: a first system bus 102 and a second system bus 104. An agent 130 is coupled to system bus 102 and an agent 140 is
coupled to system bus 104. In this system, bus bridge 100 contains a first queue 110 which contains requests issued on system bus 102 which target an agent on system bus 104. Bus bridge 100 also contains a second queue 115 which contains requests
issued on system bus 104 which target an agent on system bus 102. A temporary storage buffer 120 may also be contained in bridge 100.
Bridge 100 transfers commands between buses 102 and 104. For example, assume agent 130 issues a request targeting agent 140. This request is received by bridge 100 and placed in queue 110. Alternatively, if agent 140 issues a request targeting
agent 130, the request is placed in queue 115.
Data transferred between buses is stored in temporary storage buffer 120. For example, a read request placed into queue 110 is executed on system bus 104. When the target agent responds, the read data is placed in temporary storage buffer 120.
The agent issuing the original request knows to look in temporary storage buffer 120 for the data to satisfy its request.
In the prior art system shown, both queues 110 and 115 contain pending requests and transfer the requests onto the appropriate buses. When a write request is issued by either agent 130 or agent 140, bridge 100 forces transaction ordering by
preventing any read transactions from being placed in the opposite queue until the queue with the write request is flushed (i.e., the write transaction is executed on the targeted bus). For example, if a write operation were placed in queue 115, bridge
100 would prevent any read operations from being placed in queue 110 until queue 115 is flushed.
Although this prior art method effectively resolves the transaction ordering problem, it does not do so efficiently because it prevents the use of one queue while the other is being flushed. As described above, transactions are not placed in one
queue while the other queue contains a write operation.
Thus, it would be advantageous to provide a system which resolves the transaction ordering problem in an effective and efficient manner. The present invention provides such a solution.
In addition, in many multiple-bus systems, if an agent on a first bus issues a request which targets an agent on a second bus, then the agent issuing the request waits for a reply from the agent on the second bus. During this waiting period, the
agent may prevent other transactions from being issued on the first bus. Preventing other transactions from being issued on the first bus, however, reduces system performance because other agents cannot utilize the first bus during that time. Thus, it
would be beneficial to provide a bridge which supports the requesting agent in waiting for a reply without preventing transactions from being issued on the first bus. The present invention provides such a solution.
SUMMARY OF THE INVENTION
The present invention comprises a method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge. The bus bridge comprises two interfaces for interfacing between two separate buses. Two queues are
contained within the bus bridge: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus (termed "outbound requests") are input to decoding circuitry after being received
by the interface to the first bus. The decoding circuitry issues a deferred response if the request can be deferred. This deferred response is returned to the originating agent on the first bus, thereby informing the originating agent that the request
will be serviced at a later time. In response to the deferred response the originating agent releases control of the first bus, thus allowing other agents to utilize the first bus.
The decoding circuitry then transfers the outbound request into the outbound request queue. When the outbound request reaches the top of the outbound request queue, the request is executed on the second bus. The bus bridge receives a response
from the destination agent on the second bus in response to the execution of the outbound request, which in turn is returned as a deferred reply to the agent originating the request on the first bus.
The entries in both the outbound request queue and the inbound request queue contain pointers to data buffers contained in the bridge. The data buffers contain data which must be passed between the first bus and the second bus, dependent on the
specific command of the request. In addition, requests may originate on the second bus which target a device on the first bus (termed "inbound requests"). These inbound requests are placed in the inbound request queue and are executed on the first bus
when removed from the inbound request queue.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not limitation in the Figures of the accompanying drawings, in which like references indicate similar elements and in which:
FIG. 1 is a block diagram of a prior art implementation of a bus bridge in a computer system;
FIG. 2 shows an overview of an exemplary multiprocessor computer system of the present invention;
FIG. 3 is a timing diagram of two bus transactions for one embodiment of the present invention;
FIG. 4 is a diagram of the bus bridge of one embodiment of the present invention;
FIG. 5 is a diagram showing an example association between the queue and data buffers in one embodiment of the present invention;
FIG. 6 is a diagram showing the contents of a slot within the outbound queue of one embodiment of the present invention;
FIG. 7 is a diagram showing the contents of a slot within the inbound queue of one embodiment of the present invention; and
FIGS. 8a and 8b show a flowchart describing the steps followed for a request issued on a bus in one embodiment of the present invention.
DETAILED DESCRIPTION
In the following detailed description of the present invention numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by one skilled in the art that the
present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure aspects of the present invention.
Some portions of the detailed descriptions which follow are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used
by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The
steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise
manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent
from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a
computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities
within the computer system memories or registers or other such information storage, transmission or display devices.
FIG. 2 shows an overview of an example multiprocessor computer system of the present invention. The computer system generally comprises a processor-memory bus or other communication means 201 for communicating information between one or more
processors 202, 203, 204 and 205. Processor-memory bus 201 includes address, data and control buses. Processors 202 through 205 may include a small, extremely fast internal cache memory, commonly referred to as a level one (L1) cache memory for
temporarily storing data and instructions on-chip. In addition, a bigger, slower level two (L2) cache memory 206 can be coupled to a processor, such as processor 205, for temporarily storing data and instructions for use by processor 205. In one mode,
the present invention includes Intel.RTM. architecture microprocessors as processors 202 through 205; however, the present invention may utilize any type of microprocessor architecture, or any of a host of digital signal processors.
Processor 202, 203, or 204 may comprise a parallel processor, such as a processor similar to or the same as processor 205. Alternatively, processor 202, 203, or 204 may comprise a co-processor, such as a digital signal processor. In addition,
processors 202 through 205 may include processors of different types.
The processor-memory bus 201 provides system access to the memory and input/output (I/O) subsystems. A memory controller 222 is coupled with processor-memory bus 201 for controlling access to a random access memory (RAM) or other dynamic storage
device 221 (commonly referred to as a main memory) for storing information and instructions for processors 202 through 205. A mass data storage device 225, such as a magnetic disk and disk drive, for storing information and instructions, and a display
device 223, such as a cathode ray tube (CRT), liquid crystal display (LCD), etc., for displaying information to the computer user may be coupled to processor-memory bus 201.
An input/output (I/O) bridge 224 may be coupled to processor-memory bus 201 and system I/O bus 231 to provide a communication path or gateway for devices on either processor-memory bus 201 or I/O bus 231 to access or transfer data between devices
on the other bus. Essentially, bridge 224 is an interface between the system I/O bus 231 and the processor-memory bus 201.
In addition, an I/O bus 242 may be coupled to processor-memory bus 201 via bridge 240. I/O bus may be coupled to additional peripheral devices, such as devices 232 through 236 coupled to system I/O bus 231.
In one embodiment of the present invention I/O bus 246 is coupled to system I/O bus 231 via bridge 245. I/O bus may be coupled to additional peripheral devices, such as devices 232 through 236 coupled to system I/O bus 231. In one mode, I/O bus
246 operates on a different standard (e.g., EISA) than system I/O bus 231 (e.g., PCI).
I/O bus 231 communicates information between peripheral devices in the computer system. Devices that may be coupled to system bus 231 include a display device 232, such as a cathode ray tube, liquid crystal display, etc., an alphanumeric input
device 233 including alphanumeric and other keys, etc., for communicating information and command selections to other devices in the computer system (e.g., processor 202) and a cursor control device 234 for controlling cursor movement. Moreover, a hard
copy device 235, such as a plotter or printer, for providing a visual representation of the computer images and a mass storage device 236, such as a magnetic disk and disk drive, for storing information and instructions may also be coupled to system bus
231.
In some implementations, it may not be required to provide a display device for displaying information. Certain implementations of the present invention may include additional processors or other components. Additionally, certain
implementations of the present invention may not require nor include all of the above components. For example, processors 202 through 204, display device 223, I/O bus 242, or mass storage device 225 may not be coupled to processor-memory bus 201.
Furthermore, some of the peripheral devices shown coupled to system I/O bus 231 may be coupled to processor-memory bus 201.
In the present invention, bus transactions occur on the processor buses (e.g., processor-memory bus 201 of FIG. 2) in the computer system in a pipelined manner. That is, multiple bus transactions may be pending at the same time, wherein each is
not fully completed. Therefore, when a requesting agent begins a bus transaction by driving an address onto the bus, the bus transaction may be only one of a number of bus transactions currently pending. Although bus transactions are pipelined, the bus
transactions in the present invention do not have to be fully completed in order, such that the present invention performs deferred transactions. Therefore, the present invention allows for completion replies to requests to be out-of-order. An example
bus protocol for out-of-order replies is described in U.S. patent application Ser. No. 08/085,541, filed Jun. 30, 1993, entitled "Method and Apparatus for Performing Bus Transactions in a Computer System".
The present invention accommodates for deferred transactions by essentially splitting a bus transaction into two independent transactions. The first transaction involves a request for data (or completion signals) by a requesting agent and a
response by the responding agent. The request may be comprised of the sending of an address on the address bus and a first token. The response may include the sending of the requested data (or completion signals) if the responding agent is ready to
respond. In this case, the bus transaction ends. However, if the responding agent is not ready to supply the request (i.e., the data or completion signals), the response may include the sending of a second token. In this case, the second transaction
comprises the resending of the second token with the requested data (or completion signals) by the responding agent to the requesting agent, such that the requesting agent receives the originally requested data to complete the transaction.
If the responding agent is not ready to complete the bus transaction, then the responding agent sends a deferred response over the bus at its appropriate response time. The requesting agent receives the deferred response. When the responding
agent is ready to complete the deferred bus transaction, the responding agent arbitrates for ownership of the bus. Once bus ownership is obtained, the responding agent sends a deferred reply including a second token on the bus. The requesting agent
monitors the bus and receives the second token as part of the deferred reply. In the present invention, the requesting agent latches the second token. The requesting agent then determines whether the second token sent from the responding agent matches
the first token. If the requesting agent determines that the second token from the responding agent does not match the first token (which the requesting agent generated), then the data on the bus (or the completion signal) is ignored and the requesting
agent continues monitoring the bus. If the requesting agent determines that the second token front the responding agent does match the first token, then the data on the bus (or the completion signals) is the data originally requested by the requesting
agent and the requesting agent latches the data on the data bus.
In one embodiment of the present invention, bus activity is hierarchically organized into operations, transactions, and phases. An operation is a bus procedure that appears atomic to software such as reading a naturally aligned memory location.
Executing an operation usually requires one transaction but may require multiple transactions, such as in the case of deferred replies in which requests and replies are different transactions. A transaction is the set of bus activities related to a
single request, from request bus arbitration through response-initiated data transfers on the data bus. In this embodiment, a transaction is the set of bus activities related to a single request, from request bus arbitration through response-initiated
data transfers on the data bus.
A transaction contains up to six distinct phases. However, certain phases are optional based on the transaction and response type. A phase uses a particular signal group to communicate a particular type of information. These phases are:
Arbitration Phase
Request Phase
Error Phase
Snoop Phase
Response Phase
Data Transfer Phase
In one mode, the Data Transfer Phase is optional and used if a transaction is transferring data. The data phase is request-initiated, if the data is available at the time of initiating the request (e.g., for a write transaction). The data phase
is response-initiated, if the data is available at the time of generating the transaction response (e.g., for a read transaction). A transaction may contain both a request-initiated data transfer and a response-initiated data transfer.
Different phases from different transactions can overlap, thereby pipelining bus usage and improving bus performance. FIG. 3 shows exemplary overlapped request/response phases for two transactions. Referring to FIG. 3, every transaction begins
with an Arbitration Phase, in which a requesting agent becomes the bus owner. The second phase is the Request Phase in which the bus owner drives a request and address information on the bus. After the Request Phase, a new transaction enters a
first-in-first-out (FIFO) queue, the In-Order Queue. All bus agents, including the requesting agent, maintain identical In-Order Queues and add each new request to those queues. In FIG. 3 for example, request 1 is driven in CLK3, observed in CLK4, and
in the In-Order Queue beginning in CLK5. The third phase of a transaction is an Error Phase, three clocks after the Request Phase. The Error Phase indicates any immediate errors triggered by the request. The fourth phase of a transaction is a Snoop
Phase, four or more clocks from the Request Phase. The Snoop Phase indicates if the cache line accessed in a transaction is valid or modified (dirty) in any agent's cache. The Snoop Phase also indicates whether a transaction will be completed in-order
or may be deferred for possible out-of-order completion.
Transactions proceed through the In-Order Queue in FIFO order. The topmost transaction in the In-Order Queue enters the Response Phase. The Response Phase indicates whether the transaction failed or succeeded, whether the response is immediate
or deferred, and whether the transaction includes data phases.
If a transaction contains a response-initiated data phase, then it enters data transfer along with the response phase, the transaction is removed from the In-Order Queue at the completion of its Response Phase and (an optional) response-initiated
Data Transfer Phase. As shown in FIG. 3, transaction 1 is removed from the In-Order Queue effective in CLK15.
Due to the split-transaction nature of the bus described above, it can be seen that multiple transactions may be outstanding at any given time. That is, multiple requests may have been issued for which no replies have been returned. In one
embodiment of the present invention, each agent on the bus can have tip to eight transactions outstanding.
FIG. 4 is an exemplary block diagram of the bus bridge of one embodiment of the present invention. In one mode, bus bridge 400 of FIG. 4 is bridge 224 or 240 of FIG. 2. In one embodiment of the present invention, I/O bus 402 operates according
to the well-known PCI bus standard. However, it should be noted that I/O bus 402 may operate according to any of a wide variety of standards, such as the well-known EISA, ISA, or VESA bus standards.
In the discussion to follow, bus bridge 400 is discussed as being connected to a processor bus and an I/O bus. It should be understood by those skilled in the art, however, that the examples and embodiments discussed below apply equally to
interconnect any two buses, not only a processor bus and an I/O bus.
Bus bridge 400 includes processor bus interface 410 coupled to processor bus 401. Processor bus 401 may be for example, bus 201 of FIG. 2. Processor bus interface 410 is also coupled to an outbound request decoder 415, an I/O bus master control
unit 425, and an inbound request queue 430. Bus interface 410 receives requests from processor bus 401 which target either the bridge or agents on I/O bus 402.
Bus interface 410 includes an arbitration unit 411, In-Order Queue 414, and configuration registers 412. Arbitration unit 411 controls bus bridge 400's arbitration for access to processor bus 401. The arbitration for access to processor bus 401
may be performed in any of a wide variety of conventional manners. Configuration registers 412 provide configuration values for bridge 400's operation within the computer system. These values include, for example, whether write posting is enabled or
disabled, whether deferred replies are enabled or disabled, etc. Enabling of write posting and deferred replies is discussed in more detail below.
In-Order Queue 414 is used by bridge 400 to monitor a list of currently pending transactions on the processor bus. As discussed above, a transaction on the processor bus enters In-Order Queue 414 after the Request Phase and is removed after
completion of the Response Phase (or Data Transfer Phase, if it exists).
In one embodiment of the present invention, bus interface 410 also includes address mapping logic 413. In systems where processor bus 401 and I/O bus 402 use different standards, the addresses associated with requests may need to be translated.
That is, a request from i/O bus 402 may target an address which is not in the proper format to be placed on processor bus 401. Address mapping logic 413 performs this translation. The translation is based on the standards of the two buses and is
performed in a conventional manner.
Requests are issued on processor bus 401 by an originating agent. The originating agent may generate these requests, or alternatively the originating agent may be another interface or bridge which is merely transferring the request to processor
bus 401. Regardless of where a request originates, when bus interface 410 receives the request it immediately transfers the request to outbound request decoder 415. Outbound request decoder 415 determines whether the request will be deferred, as
described in more detail below. After making this determination outbound request decoder 415 issues a signal to bus interface 410 indicating whether or not the request is deferred. If the request is deferred, then bus interface 410 returns a response
to the agent which placed the request on processor bus 401; this response indicates that the request is deferred. If, however, the request is not deferred, then bus interface 410 stalls processor bus 401 until the request is completed. By "stalling" it
is meant that no transactions are passed over the bus until the stall is released. In one mode, stalling the bus is accomplished by sending a signal to all agents on the bus that the bus should be stalled.
In one embodiment of the present invention, processor bus 401 is a pipelined bus. Thus, if a request is not deferred, the entire bus does not necessarily need to be stalled. In one mode, bridge 400 stalls the Response Phase of the bus when the
request is not deferred. By stalling the Response Phase, other phases of the pipeline bus are allowed to continue for other transactions while the current request is pending. For example, other agents can place requests on the bus and some result
signals (e.g., error signals) can be issued, however no responses are issued until bridge 400 releases the stall on the Response Phase.
In one mode, bus interface 410 completely stalls processor bus 401 if the outbound request queue 420 is filled. That is, when no remaining slots exist in the outbound request queue 420, bus interface 410 issues a signal on processor bus 401 to
completely stall the pipeline. By completely stalling the bus, no additional transactions can occur on processor bus 401 in any phase until a slot in the outbound request queue 420 becomes available. At such a time, bus interface 410 releases the stall
on processor bus 401.
In this mode, bus interface 410 stalls processor bus 401 if all slots in the outbound request queue 420 are filled. In s | | |
