 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device.
2. Description of the Related Art
In a high breakdown voltage semiconductor device, dielectric isolation method is known as an effective method of isolating each element.
FIG. 1 shows a conventional high breakdown voltage diode obtained by using such a dielectric isolation method. Reference numeral 101 denotes a p.sup.+ type silicon substrate, and there is formed a substrate wafer in which the p.sup.+ type
silicon substrate and an n.sup.- (or p.sup.-) type silicon substrate are bonded to each other by a direct bonding method. Reference numeral 102 is an oxide film of a bonding interface. The n.sup.- type substrate of the substrate wafer is selectively
etched up to the depth reaching the oxide film 102, so that a groove is formed. Thereby, an n.sup.- type layer 103, which is an island element region, is formed. In the groove, an oxide film 104 is formed inside and a polycrystalline silicon film 105
is buried therein. An n.sup.+ type layer 106, serving as a cathode region, is formed in the central surface portion of the island n.sup.- type layer 103 isolated from other portions by the oxide films 102 and 104. Then, p.sup.+ type layer 107, serving
as an anode region, is formed in the peripheral surface portion. As a result, a diode is formed. P.sup.+ layers 108 and 109 are formed along the oxide films 102 and 104 so as to enclose the surroundings of the island n.sup.- type layer 103. The
p.sup.+ type layers 108 and 109 are formed so as to allow large current to flow. A cathode electrode 110 and an anode electrode 111 are formed on the n.sup.+ type layer 106 and p.sup.+ type layer 107, respectively.
In the above diode, if reverse bias is applied to the portion between the anode and the cathode and a depletion layer extends to the n.sup.- type layer 103, and all applied voltages are applied between the n.sup.+ type layer 106 of the surface
portion and the p.sup.+ type layer 108 of the bottom portion. Therefore, in order to obtain a diode having sufficient high breakdown voltage, it is required that a distance d between the n.sup.+ type layer 106 and the p.sup.+ type layer 108 be
sufficiently largely made. More specifically, in order to obtain voltage of 600 V, d=45 .mu.m is needed.
If the thickness of the n.sup.- type layer 103 is made larger so as to ensure the above-mentioned distance d, the groove for the element isolation in a lateral direction must be deepened in accordance with the thickness of the n.sup.- type layer
103. This makes it extremely difficult to perform the element isolation in the lateral direction.
As mentioned above, according to the semiconductor device having the conventional dielectric isolation structure, it is necessary to make the thickness of the high resistance semiconductor layer whose depletion layer extends sufficiently large so
as to obtain a sufficient high breakdown voltage. Due to this, there is a problem that the element isolation becomes difficult to be performed.
The following explains the other examples of the semiconductor device having the conventional dielectric isolation structure.
FIG. 2 shows a conventional lateral type diode having the conventional dielectric isolation structure. An n.sup.- type silicon layer (active layer) 33 is formed on a semiconductor substrate 31 via an insulating film 32 for isolation. An n.sup.+
type layer 34 having a high impurity concentration is formed in the bottom portion of the active layer 33. A p-type anode layer 135 is formed in the active layer 33 and an n-type cathode layer 36 is formed in a portion which is away from the p-type
anode layer 35 with a predetermined distance, and an anode electrode 37 and a cathode electrode 38 are formed on the anode layer 35 and the cathode layer 36, respectively.
In the above-mentioned lateral type diode, for example, considering a reverse bias state in which the anode electrode 37 and the substrate 31 are grounded and a positive voltage is applied to the cathode electrode 38, the voltage to be applied to
the cathode is applied to the depletion layer extending to the active layer under the p-type anode layer 35, and the insulating film 32 for isolation.
Due to this, if the thickness of the active layer 33 under n-type cathode layer 36 is thin, a large electric field is shared at this portion, and an electric field concentration occurs in the vicinity of the curved portion of the bottom of the
n-type cathode layer 36, and avalanche breakdown is generated at a low applied voltage. In order to avoid the above problem and realize the sufficient high breakdown voltage, the thickness of the active layer 33 is conventionally set to be 40 .mu.m or
more.
However, if the thickness of the active layer is large, a deep isolation groove is needed for the element isolation in the lateral direction by a V-groove, and an area of the isolation groove region becomes large. Due to this, work processing
becomes difficult and an effective area of the element becomes small, so that the cost of an integrated circuit having the high breakdown voltage element increases.
As mentioned above, in the high breakdown voltage semiconductor device having the conventional dielectric isolation structure, if the active layer is thin, a sufficient breakdown voltage cannot be obtained. Moreover, if the active layer is
thick, the element isolation in the lateral direction becomes difficult.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, an object of the present invention is to provide a semiconductor device having high breakdown voltage using the dielectric isolation structure wherein a sufficiently high breakdown voltage can be
obtained even if a relative thin high resistance semiconductor layer is used.
According to the first aspect of the present invention, there is provided a high breakdown voltage semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a high resistance
semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a
first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region, wherein the
dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low
resistance regions.
According to the second aspect of the present invention, there is provided a high breakdown voltage semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a high resistance
semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction from
the isolation region, a first low resistance region of a first conductivity type formed in a region extending from a surface of the element region to the insulating layer, and a second low resistance region of a second conductivity type formed in a
region extending from a surface of the element region to the insulating layer, wherein the dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance
region is completely depleted when voltage is applied between the first and second low resistance regions.
According to the third embodiment of the present invention, there is provided a lateral type insulated gate bipolar transistor comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a high resistance
semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a
first low resistance region of a first conductivity type formed in a central surface portion of the element region, a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region, a drain region
of a second conductivity type formed in the first low resistance region, and a source region of a first conductivity type formed in the second low resistance region, wherein the dose of impurities in the element region is set such that a portion of the
element region between the source region and the drain region is completely depleted when voltage is applied between the source region and the drain region.
According to the fourth aspect of the present invention, there is provided a high breakdown voltage semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a high resistance
semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a
first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a surface portion of the element region to be separated from
the first low resistance region, wherein when voltage is applied between the first low resistance region and the second low resistance region and both the potential of the first low resistance region and that of the second low resistance region are
higher than the potential of the semiconductor substrate, a channel region of a second conductive type is formed in the bottom portion of the element region, whereby influence of potential of the semiconductor substrate is shielded.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention
may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of
the preferred embodiments given below, serve to explain the principles of the invention.
FIGS. 1 and 2 are cross sectional views showing a conventional high breakdown voltage diode;
FIG. 3 is a cross sectional view showing a diode of an embodiment in which a second low resistance region is deeply formed by impurity diffusion;
FIG. 4 is a cross sectional view showing a diode of an embodiment in which the buffer layer is formed in the bottom portion of the device of FIG. 3;
FIG. 5 is a cross sectional view showing a diode of an embodiment in which each conductivity type of each portion of FIG. 3 is reversed;
FIG. 6 is a cross sectional view showing an embodiment in which the present invention is applied to a IGBT;
FIG. 7 is a cross sectional view showing an IGBT of an embodiment in which the structure of FIG. 6 is modified;
FIG. 8 is a cross sectional view showing an IGBT of an embodiment in which the structure of FIG. 6 is modified;
FIG. 9 is a cross sectional view showing an IGBT of an embodiment in which the structure of FIG. 7 is modified;
FIG. 10 is a cross sectional view showing an embodiment in which the lateral element isolation of the element of FIG. 7 is performed by LOCOS method;
FIG. 11 is a cross sectional view showing an embodiment in which the structure of FIG. 10 is partially modified;
FIG. 12 is a cross sectional view showing an embodiment in which the element isolation due to LOCOS method is applied to the embodiment of FIG. 9;
FIG. 13 is a cross sectional view showing an embodiment in which an MCT is formed in the region isolated by the LOCOS;
FIG. 14 is a cross sectional view showing an embodiment an which IGBT of the embodiment of FIG. 10 is partially modified;
FIG. 15 is a cross sectional view showing an embodiment in which the IGBT of the embodiment of FIG. 6 is partially modified;
FIG. 16 is a cross section view showing an embodiment of FIG. 6 is partially modified;
FIGS. 17A to 17P are cross sectional views showing a manufacture process of the device substrate of the embodiment of FIG. 16;
FIG. 18 is a cross sectional view showing an embodiment in which the embodiment of FIG. 15 is partially modified;
FIG. 19 is a cross sectional view showing an embodiment in which the embodiment of FIG. 16 is partially modified;
FIG. 20 is a cross sectional view showing an embodiment in which the embodiment of FIG. 15 is partially modified;
FIG. 21 is a cross sectional view showing an embodiment in which the embodiment of FIG. 20 is partially modified;
FIG. 22 is a cross sectional view showing an embodiment in which the embodiment of FIG. 15 is partially modified;
FIG. 23 is a cross sectional view showing an embodiment in which the embodiment of FIG. 22 is partially modified;
FIG. 24 is a cross sectional view showing an embodiment in which the embodiment of FIG. 15 is partially modified;
FIG. 25 is a cross sectional view showing an embodiment in which the embodiment of FIG. 24 is partially modified;
FIG. 26 is a view showing an embodiment in which the present invention is applied to the lateral type diode;
FIG. 27 is a view showing a diode of an embodiment in which the structure of FIG. 26 is slightly modified;
FIG. 28 is a view showing an embodiment in which the present invention is applied to the MOSFET;
FIG. 29 is a view showing a MOSFET of an embodiment in which the structure of FIG. 28 is modified;
FIG. 30 is a view showing a MOSFET of an embodiment in which the structure of FIG. 28 is modified;
FIG. 31 is a view showing a MOSFET of an embodiment in which the structure of FIG. 29 is modified;
FIG. 32 is a view showing an embodiment in which the present invention is applied to the lateral type IGBT;
FIG. 33 is a view showing an IGBT of an embodiment in which the structure of FIG. 32 is modified;
FIG. 34 is a view showing an IGBT of an embodiment in which the structure of FIG. 32 is modified;
FIG. 35 is a view showing an IGBT of an embodiment in which the structure of FIG. 33 is modified;
FIG. 36 is a view showing a diode of an embodiment in which the structure of FIG. 26 is modified;
FIG. 37 is a view showing a MOSFET of an embodiment in which the structure of FIG. 28 is modified;
FIG. 38 is a view showing a MOSFET of an embodiment in which the structure of FIG. 37 is modified;
FIG. 39 is a view showing a MOSFET of an embodiment in which the structure of FIG. 35 is modified;
FIG. 40 is a view showing a diode of an embodiment in which a base high resistance film is added to the structure of FIG. 26;
FIG. 41 is a view showing a diode of an embodiment in which a base high resistance film is added to the structure of FIG. 27;
FIG. 42 is a view showing a MOSFET of an embodiment in which a base high resistance film is added to the in structure of FIG. 28;
FIG. 43 is a view showing a MOSFET of an embodiment in which a base high resistance film is added to the structure of FIG. 29;
FIG. 44 is a view showing a MOSFET of an embodiment in which a base high resistance film is added to the structure of FIG. 30;
FIG. 45 is a view showing a MOSFET of an embodiment in which a base high resistance film is added to the structure of FIG. 31;
FIG. 46 is a view showing an IGBT of an embodiment in which a base high resistance film is added to the structure of FIG. 32;
FIG. 47 is a view showing an IGBT of an embodiment in which a base high resistance film is added to the structure of FIG. 33;
FIG. 48 is a view showing an IGBT of an embodiment in which a base high resistance film is added to the structure of FIG. 34;
FIG. 49 is a view showing an IGBT of an embodiment in which a base high resistance film is added to the structure of FIG. 35;
FIG. 50 is a view showing a diode of an embodiment in which a base high resistance film is added to the structure of FIG. 36;
FIG. 51 is a view showing a MOSFET of an embodiment in which a base high resistance film is added to the structure of FIG. 37;
FIG. 52 is a view showing a MOSFET of an embodiment in which a base high resistance film is added to the structure of FIG. 38;
FIG. 53 is a view showing a MOSFET of an embodiment in which a base high resistance film is added to the structure of FIG. 39;
FIG. 54 is a view showing a diode of an embodiment in which the structure of FIG. 40 is modified;
FIG. 55 is a view showing a diode of an embodiment in which the structure of FIG. 41 is modified;
FIG. 56 is a view showing a MOSFET of an embodiment in which the structure of FIG. 42 is modified;
FIG. 57 is a view showing a MOSFET of an embodiment in which the structure of FIG. 43 is modified;
FIG. 58 is a view showing a MOSFET of an embodiment in which the structure of FIG. 44 is modified;
FIG. 59 is a view showing a MOSFET of an embodiment in which the structure of FIG. 45 is modified;
FIG. 60 is a view showing an IGBT of an embodiment in which the structure of FIG. 46 is modified;
FIG. 61 is a view showing an IGBT of an embodiment in which the structure of FIG. 47 is modified;
FIG. 62 is a view showing an IGBT of an embodiment in which the structure of FIG. 48 is modified;
FIG. 63 is a view showing an IGBT of an embodiment in which the structure of FIG. 49 is modified;
FIG. 64 is a view showing a diode of an embodiment in which the structure of FIG. 50 is modified;
FIG. 65 is a view showing a MOSFET of an embodiment in which the structure of FIG. 51 is modified;
FIG. 66 is a view showing a MOSFET of an embodiment in which the structure of FIG. 52 is modified;
FIG. 67 is a view showing a MOSFET of an embodiment in which the structure of FIG. 53 is modified;
FIG. 68 is a view showing a diode of an embodiment in which the structure of FIG. 26 is modified;
FIG. 69 is a view showing a diode of an embodiment in which the structure of FIG. 26 is modified;
FIG. 70 is a view showing a MOSFET of an embodiment in which the structure of FIG. 28 is modified;
FIG. 71 is a view showing a MOSFET of an embodiment in which the structure of FIG. 29 is modified;
FIG. 72 is a view showing a MOSFET of an embodiment in which the structure of FIG. 28 is modified;
FIG. 73 is a view showing an IGBT of an embodiment in which the structure of FIG. 32 is modified;
FIG. 74 is a view showing an IGBT of an embodiment in which the structure of FIG. 32 is modified;
FIG. 75 is a view showing an IGBT of an embodiment in which the structure of FIG. 32 is modified;
FIG. 76 is a view showing an IGBT of an embodiment in which the structure of FIG. 32 is modified;
FIG. 77 is a view showing an IGBT of an embodiment in which the structure of FIG. 32 is modified;
FIG. 78 is a view showing all IGBT of an embodiment in which the structure of FIG. 32 is modified;
FIG. 79 is a view showing a diode of an embodiment in which the structure of FIG. 26 is modified;
FIGS. 80A to 80C are views showing an example of the structure of the lateral isolation of the device of the present invention;
FIG. 81 is a view showing the relationship between the total amount of impurities of an active layer and breakdown voltage in the embodiment of FIG. 26;
FIG. 82 is a view showing the relationship between the thickness of an oxide film under the high resistance film and breakdown voltage in the embodiment of FIG. 26;
FIG. 83 is a view showing the relationship between the thickness of the active layer and breakdown voltage in the embodiment of FIG. 26;
FIG. 84 is a view showing a diode relating to the other embodiment of the present invention;
FIG. 85 is a view showing an IGBT relating to the other embodiment of the present invention;
FIG. 86 is a view showing an IGBT of an embodiment in which the structure of FIG. 85 is modified;
FIG. 87 is a view showing an IGBT of an embodiment in which the structure of FIG. 85 is modified; and
FIGS. 88 to 112 are views showing a diode or an IGBT of an embodiment in which a high resistance film is removed in the embodiments of FIGS. 26 to 79.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
According to a first high breakdown voltage semiconductor device relating to the present invention, for example, it is assumed that reverse bias voltage is applied between first and second low resistance regions in a state that the first low
resistance region is set to be a high potential and the second low resistance region is set to be a ground potential. At this time, the applied voltage is impressed to the high resistance semiconductor layer in a deep direction at the same time with the
lateral direction. This is because a base semiconductor substrate is normally set to be a ground potential. Then, a depletion layer extends to the high resistance semiconductor layer from a pn junction around the first or second low resistance region.
When the applied voltage runs up to a certain value, the depletion layer reaches up to a first insulating film on the base semiconductor substrate, and the voltage in the deep direction is shared by the high resistance semiconductor layer and the first
insulating film.
In order to prevent the avalanche breakdown in such a high voltage applying state, it is better that that portion of the applied voltage, which is shared by the first insulating film, is set to be larger. Moreover, since a dielectric flux
density is continuous at the boundary surface between the high resistance semiconductor layer and the first insulating film, it is better that the electric field in the first insulating film is set to be small not to strengthen the electric field in the
vertical direction in the high resistance semiconductor layer.
In the first high breakdown voltage semiconductor device relating to the present invention, since the thickness of the first insulating film is 1 .mu.m or more, the electric field in the first insulating film is relatively small even in a state
that the depletion layer extends as mentioned above. Due to this, the vertical electric field of the high resistance semiconductor layer is controlled to be small. Moreover, since the applied voltage is mainly shared by the first insulating film, the
applied voltage to be applied in the deep direction of the high resistance semiconductor layer is controlled to be small. As mentioned above, according to the semiconductor device relating to the present invention, even if the high resistance
semiconductor is formed relatively thin, a high breakdown voltage characteristic can be sufficiently obtained.
According to the first high breakdown voltage semiconductor device relating to the present invention, particularly, if in the bottom portion of the high resistance layer, there is formed a buffer layer having low impurity concentration such that
a total amount of impurity per a unit area is set to be 3.times.10.sup.12 /cm.sup.2 or less, preferably 0.5 to 2.0.times.10.sup.12 /cm.sup.2, much higher breakdown voltage can be obtained. This is because space charge having high concentration occurs
from the high resistance semiconductor layer if the buffer layer is completely depleted at the time of reverse bias application. If a vertical component of the electric field at the boundary surface between the buffer layer and the first insulating film
is Es on the semiconductor layer side, Ei on the insulating film side, a dielectric constant of the semiconductor layer is .epsilon.s, and a dielectric constant of the insulating film is .epsilon.i, an equation of Es=(.epsilon.i/.epsilon.s) Ei can be
obtained. Due to this, as the electric field in the first insulating film becomes larger, the electric field in the semiconductor layer becomes large in accordance with this. However, the space charge occurred in the buffer layer acts to relax the
electric field on the semiconductor layer side. Therefore, by providing such a buffer layer, it is possible to make the electric field of the first insulating film larger as the electric field of the semiconductor layer is maintained small, thereby the
high breakdown voltage can be obtained.
According to a second high breakdown voltage semiconductor device relating to the present invention, the element isolation in the vertical direction is made by not the insulating film but the pn junction. Other than that, the structure of the
second semiconductor device is the same as that of the first semiconductor device. Therefore, the second semiconductor device is a relatively thin high resistance semiconductor layer and can obtain a sufficient high breakdown voltage characteristic.
In the first high breakdown voltage semiconductor device, there is considered a case in which a third low resistance region of a first conductivity type is formed in the boundary surface portion between the second insulating film (isolating
region) and the high resistance semiconductor layer of the element region. This structure cannot be avoided in a case in which a low resistance region of the first conductivity type is formed on the groove side wall of the adjacent element region. This
is because it is difficult to selectively diffuse a low resistance region in only one side of the groove side walls. According to this structure, there is a problem in breakdown occurring between the second and third low resistance regions when reverse
bias is applied. First, if reverse bias is applied, the depletion layer extends to the high resistance semiconductor layer from the surroundings of the second low resistance region and the upper surface of the first insulating film. Where the first and
third low resistance regions are connected through a neutral region, the potential of the third low resistance region follows the potential of the first low resistance region. When breakdown voltage of the pn junction between the second and third low
resistance regions is V.sub.B and reverse bias voltage reaches to V.sub.B while the first and third low resistance regions regions are connected through the neutral region, breakdown is generated. If the thickness of the high resistance semiconductor
layer and impurity concentration thereof are set such that the applied voltage at the time when the depletion layer under the second low resistance region reaches to the first insulating film is lower than V.sub.B, the first and third low resistance
regions is separated from each other by the depletion layer before breakdown occurs. As mentioned above, if the third low resistance region is separated from the first low resistance region by the depletion layer, the potential difference between the
second low resistance region and the third low resistance region does not increase and breakdown between these low resistance regions is prevented.
According to a third high breakdown voltage semiconductor device, the second low resistance region is formed up to the depth reaching the first insulating film, so that the first and third low resistance regions are separated from each other.
Therefore, the potential of the third low resistance region does not increase in accordance with the first low resistance region, and breakdown does not occur in the pn junction between the second and the third low resistance regions. Due this, high
breakdown voltage characteristic can be improved even if there is the third low resistance region.
According to a fourth high breakdown voltage semiconductor device relating to the present invention, a high resistance film formed on the boundary surface between the first insulating film and the high resistance semiconductor layer acts to
shield influence of the potential of the base semiconductor substrate, thereby excellent high breakdown voltage characteristic can be obtained.
Various embodiments of the present invention will be explained with reference to the drawings as follows.
FIG. 3 is an embodiment in which the p.sup.+ type layer 7, serving as an anode region of, is formed in the peripheral portion up to the depth reaching to the oxide film 2 of the base.
According to the structure of this embodiment, the n.sup.+ type layer 6 formed in the central portion of the device and the n.sup.+ type layer 31 formed in the peripheral side portion of the device are electrically separated, and are not
connected to each other at the neutral region unlike the embodiment of FIG. 16. Due to this, breakdown voltage of the pn junction between the p.sup.+ type layer 7 and the n.sup.+ type layer 31 has no influence on the breakdown voltage characteristic of
the device, and high breakdown voltage characteristic can be obtained.
FIG. 4 is an embodiment in which the n.sup.- type buffer layer 10 is formed in the bottom portion of the high resistance silicon layer 4 so as to obtain further high breakdown voltage.
FIG. 5 is an embodiment in which the n.sup.+ type layer 23 in the peripheral portion is formed up to the depth reaching to the oxide film 2. In other words, this is the embodiment in which the conductivity type of each portion of FIG. 4 is
reversed. This embodiment also shows that high breakdown voltage characteristic can be obtained.
FIG. 6 is an embodiment of IGBT. According to this embodiment, an oxide film 83 is formed between the high resistance silicon layer 4 and the high resistance film 71. The oxide film 83 has an opening under the source region and the drain
region. Due to this, one end of the high resistance film 71 is set to be source potential through the p type base layer 72, and the other end is set to be drain potential through the n type base layer 74. Since the portion therebetween is insulated
from the high resistance silicon layer 4 by the oxide film 83, potential gradient generated in the high resistance film 71 is more equalized than that of FIG. 6.
In order to prepare such IGBT, the oxide film 83 is formed on the surface of the substrate, serving as the high resistance silicon layer 4, an opening for contact is formed, and the high resistance film 71 such as SIPOS is deposited thereon. An
oxide film is formed on either the surface of the high resistance film 71 or that of the base substrate 1 or both surfaces by CVD or thermal oxidation, and these substrates are directly bonded. The base substrate may be formed by depositing
polycrystalline silicon in place of the bonding. The method of performing the element isolation due to the trench groove thereafter is the same as that of FIG. 43. Moreover, similar to the embodiment of FIG. 44, since the thickness of the high
resistance silicon layer is set to be about 1 .mu.m to 5 .mu.m, the p type base layer 72 and the n type base layer 74 reach to the high resistance film 71.
According to this embodiment, the high resistance film 71 of the bottom portion of the high resistance silicon layer 4 shields influence of the potential of the substrate. As the same time, similar to the upper high resistance film 8, the high
resistance film 71 serves as a field plate. Due to this, this embodiment also shows that the sufficiently high breakdown voltage characteristic can be obtained.
FIG. 7 is an embodiment of IGBT in which the embodiment of FIG. 6 is modified. The drain layer 75 reaches up to the high resistance film 71. The n.sup.+ type layer 31 is formed in the side portion of the high resistance silicon layer 4. Due to
this, the high resistance voltage characteristic can be also obtained according to this embodiment.
FIG. 8 is an embodiment of IGBT in which the connection method of the high resistance film 82 is changed based on the embodiment of FIG. 7. One end of the high resistance film 82 is connected to the surface of the n.sup.+ type source layer 73,
and the other end is connected to the p.sup.+ type drain layer 75 and the drain electrode 80. On the drain side, the high resistance film 82 and the drain electrode 80 may be separated from each other. Moreover, the source side end of the high
resistance film 82 may be connected to the source electrode 79.
FIG. 9 is an embodiment of IGBT in which the embodiment of FIG. 6 is modified. The drain layer 75 is formed to reach the high resistance film 71. Conductive members 84 and 85 such as metallic wires are connected to the source electrode 79, the
drain electrode 80 and the high resistance film 71, thereby further high breakdown voltage can be obtained.
The formation of the high resistance film such as SIPOS in the bottom portion of the element as explained in the embodiments of FIGS. 6 to 9 is useful to the embodiments previously shown.
Since the high resistance silicon layer 4 is thin in the embodiments of FIGS. 6 to 9, the oxide film reaching to the high resistance film 71 from the surface can be easily formed. Due to this, the element isolation can be performed by an LOCOS
method in place of the formation of the element isolation groove.
FIG. 10 is an embodiment in which the element isolation is performed by the LOCOS method. There is locally formed an oxide film 226 reaching to the high resistance film 71 from the surface of the high resistance silicon layer 4, thereby the
element isolation in the lateral direction is performed. According to this embodiment, IGBT shown in FIG. 46 is formed in one of the regions separated by the oxide film 226, and a CMOS circuit, serving as a logic circuit, is formed in the other region.
It is noted that the n.sup.+ type layer 31 of FIG. 46 is formed on the side surface of the trench and is not shown in FIG. 46. An n.sup.+ type layer corresponding to the n.sup.+ type layer 31 may be formed under the source electrode 79 of IGBT to reach
to the high resistance film 71. Thereby, the electrical connection between the source electrode 79 and the high resistance film 71 can be much improved.
FIG. 11 is an embodiment in which no high resistance film 71 of FIG. 10 is formed. In place of the high resistance film 71, the thickness of the oxide film 2 is set to be 2.mu. or more, thereby the high breakdown voltage characteristic can be
obtained.
FIG. 12 is an embodiment in which the element isolation by the LOCOS method is applied to the embodiment of FIG. 9. The LOCOS oxide film 226 is formed so as to reach the oxide film 83 from the surface of the high resistance silicon layer 4.
FIG. 13 is an embodiment in which MCT is formed in the region separated by the LOCOS method. The MCT is formed by partially modifying IGBT of the embodiment of FIG. 10. An n.sup.+ type region 227 is formed in the p type region 72 to be parallel
to the n.sup.+ type region 73. On the surface portion of the p type region 72 sandwiched between the n.sup.+ region 73 and the n.sup.+ region 227, there is formed a second gate electrode 229 through the gate insulating film 228. A cathode electrode 230
is formed on the n.sup.+ type region 73, and an anode electrode 231 is formed on the p.sup.+ type region 75. A p.sup.+ type region 232 is formed adjacent to the n.sup.+ type region 227 so as to improve contact with the p type region. An electrode 233
is formed over the n.sup.+ type region 227 and the p.sup.+ region 232. It is noted that the electrode 233 may not be formed in this case.
The element of this embodiment is driven to be on 10 by the first gate electrode 78, and off by the second gate electrode 229.
FIG. 14 is an embodiment in which the IGBT of the embodiment of FIG. 10 is partially modified. Ends of the high resistance film 82 are connected to the surface of the n.sup.+ type source layer 73 and the surface of the p.sup.+ type drain layer
75, respectively. The source side end may be connected to the source electrode 79.
FIG. 15 is an embodiment in which the IGBT of the embodiment of FIG. 10 is partially modified. In place of the high resistance film 71, a polycrystalline silicon film 234 is buried in the oxide film 2. The polycrystalline silicon film 234 is
set to have a predetermined resistivity by an ion implantation, and patterned in a strip form or a mesh form with a suitable space. The polycrystalline silicon film 234 serves as a field plate, and the element having the high voltage characteristic can
be realized.
FIG. 16 is an embodiment in which a polycrystalline silicon film 235, which is similar to the polycrystalline silicon film 234, under the polycrystalline silicon film 234 based on the element of the embodiment of FIG. 15. These two-layered
polycrystalline silicon layers 234 and 235 are alternately arranged such that the spaces thereof do not correspond to each other. More specifically, these films are patterned such that the polycrystalline silicon film 235 is surely arranged under the
space of the polycrystalline silicon film 234. By such an arrangement of the polycrystalline silicon films, influence of the potential of the substrate 1 on the element is effectively shielded.
FIGS. 17A to 17P are views showing the manufacturing process of the dielectic isolation element substrate of FIG. 16.
A silicon substrate of FIG. 17A is used as the high resistance silicon layer 4 which is the element region. As shown in FIG. 17B, an oxide film 236 is formed on the silicon substrate by thermal oxidation. Then, as shown in FIG. 17C, a
polycrystalline silicon film 234 is formed thereon. Thereafter, an impurity is doped by the ion plantation, and as a result, a predetermined resistivity is applied to the polycrystalline silicon film 236. Then, as shown in FIG. 17D, the polycrystalline
silicon film 234 is formed in a stripe pattern or a mesh pattern to have a predetermined space. Thereafter, as shown in FIG. 17E, the upper portion of the polycrystalline silicon film 234 and the space portion are completely buried with an oxide film
237 by CVD.
Then, as shown in FIG. 17F, the surface of the film is polished and flattened, and the polycrystalline silicon film 235 is again deposited thereon, and patterned as shown in FIG. 17H. Thereafter, as shown in FIG. 17I, a CVD oxide film 238 is
deposited thereon, and the surface thereof is polished and flattened as shown in FIG. 17J. The process shown in FIGS. 17G to 17J is the repetition of the process shown in FIGS. 17C to 17F.
In place of the process in which the deposited film of FIG. 17I is polished as shown in FIG. 17J, it is possible to perform a process in which a thicker polycrystalline silicon film 239 is deposited, and polished as shown in FIG. 17K, so that the
flattened substrate can be obtained as shown in FIG. 17L.
Other than the substrate of FIG. 17J (or FIG. 17L) having the oxide film formed by burying two-layered polycrystalline silicon films, the silicon substrate having a thermal oxide film 240 is prepared. Then, as shown in FIG. 17M, the silicon
substrate is directly bonded to the two-layered polycrystalline silicon films, thereby obtaining the integrated substrate. Then, as shown in FIG. 17N, the integrated substrate is polished such that the high resistance silicon layer 4 has a predetermined
thickness, so that the device substrate is completed. In this case, an incomplete bonded portion which is the peripheral portion of the device substrate is cut. The thermal oxide film 240 of the substrate 1 of FIG. 17M is not always formed.
In the above example, the manufacturing process of the dielectric isolation element using two substrates has been explained. However, the device substrate can be obtained using one substrate. For example, after the substrate is formed as shown
in FIG. 17I, a polycrystalline silicon 241 is deposited thick as shown in FIG. 17O, and the polycrystalline silicon 241 is used as a base substrate as it is. Then, as shown in FIG. 17P, the high resistance silicon layer 4 is polished to have a
predetermined thickness, thereby obtaining the same device substrate.
In the above element substrate forming process, if the deposition step of a polycrystalline silicon film 235, and the patterning step are omitted, the device substrate shown in the embodiment of FIG. 15 can be obtained.
FIG. 18 is an embodiment in which the embodiment of FIG. 16 is partially modified. In this embodiment, the polycrystalline silicon film 234 is formed only under a drift layer between the p type base layer 72 and the n type base layer 74.
FIG. 19 is an embodiment in which the embodiment of FIG. 16 is partially modified. In this embodiment, the polycrystalline silicon films 234 and 235 are formed only under the drift layer between the p type base layer 72 and the n type base layer
74.
FIG. 20 is an embodiment in which the embodiment of FIG. 15 is partially modified. Similar to the embodiment of FIG. 9, the conductive members 84 and 85 such as metal are buried under the source electrode 79 and the drain electrode 80, thereby
the polycrystalline silicon 234 formed in the bottom portion of the device is connected to the source electrode 79 and the drain electrode 80. Each of portions 234a and 234b to be connected to each of conductive members 84 and 85 is designed to have a
suitable length for a field plate.
FIG. 21 is an embodiment in which the polycrystalline silicon 235 is formed under the polycrystalline silicon 234 as shown in the embodiment of FIG. 16 and influence of the substrate potential is effectively shielded based on the embodiment of
FIG. 20.
FIG. 22 is an embodiment in which the embodiment of FIG. 15 is partially modified. The portions 234c and 234d of the polycrystalline silicon film 234 buried in the silicon oxide film 2 which are formed under the p type base layer 72 and the n
type buffer layer 74, are exposed to the upper surface of the oxide film 2, and connected to the p type base layer 72 and the n type buffer layer 74, respectively. Due to this, that portion of the polycrystalline film 234, which is just under the source
and that portion of the polycrystalline film 234, which is just under the drain thereof, are set to be source potential and drain potential, respectively. The portions 234c and 234d of the polycrystalline silicon film 234 having the above-set potential
are set to have suitable lengths as field plates similar to the embodiment of FIG. 20.
In order to manufacture the above-mentioned device structure, to the steps explained in FIGS. 17A to 17P, there may be added a step of forming an opening in an oxide film 236 at a portion to be used as a connecting portion between the p type base
layer 72, and the polycrystalline silicon 234c, and between the n type buffer layer 74, and and the polycrystalline silicon 234d.
FIG. 23 is an embodiment in which the polycrystalline silicon film 235 is formed at a level lower that that of the polycrystalline silicon film 234 similar to the embodiment of FIG. 19.
FIG. 24 is an embodiment in which IGBT of the embodiment of FIG. 15 is partially modified. In this embodiment, in place of the high resistance film 82 of the embodiment of FIG. 15, a polycrystalline silicon film 242, which is similar to the
polycrystalline silicon film 234 buried in the oxide film 2, is formed as a field plate. Since the polycrystalline silicon film 242 can be formed at the same time with the gate electrode 78, the manufacturing process of this embodiment is easier than
that of the embodiment of FIG. 15.
FIG. 25 is an embodiment in which the polycrystalline silicon film 235 is further formed at a level lower than that of the polycrystalline silicon film 234 of the bottom portion as in the embodiment of FIG. 16 and the polycrystalline silicon film
243 is further formed at a level higher than that of the polycrystalline silicon film 242. Thereby, shield effect against the upper and lower elements increases.
The material of the films 234, 235, 242, and 243 explained the embodiments of FIGS. 15 to 25 are not limited to polycrystalline silicon. It is possible to replace polycrystalline silicon with SIPOS and the other conductive materials, or
resistance materials. Moreover, the modifications explained in FIGS. 15 to 25 are useful for the diode, MOSFET, MCT, EST.
As explained above, according to the present invention, in the high breakdown voltage semiconductor device comprising the high resistance semiconductor layer, which is separated from the base semiconductor substrate by the first insulating film
and separated in the lateral direction by the second insulating film or the pn junction, and the first low resistance region of the first conductive type and the low resistance region of the second conductive type formed in the surface portion of the
high resistance semiconductor layer, the thickness of the first insulating film is set to be 1 .mu.m or more, reverse bias voltage of the device is largely shared by the first insulating film, and electrical field in the high resistance semiconductor
layer, which depends on the electrical field in the first insulating film, is weakened, thereby sufficiently high breakdown voltage can be obtained even if the high resistance semiconductor layer is thin. Moreover, since the high resistance
semiconductor layer can be made thin, the element separation can be easily made.
According to the second specific form of the present invention, a thin active layer is used such that a high impurity concentration layer formed in a high resistance active layer reaches to the first insulating film for isolation. With the
structure of the present invention, for example, it is assumed that the high impurity concentration layer of the first conductivity type is formed to reach to the depth of the first insulating film, and high voltage is applied to the high impurity
concentration layer of the first conductivity type such that the pn junction becomes reverse biased in a state that the high impurity concentration of the second conductivity type and the substrate are grounded. At this time, voltage to be applied to
the high impurity concentration layer of the first conductivity type is all shared by the first insulating film in the vertical direction. The lateral potential distribution of the surface of the active layer is made uniform in accordance with the
uniform potential distribution to be formed in the high resistance film formed in the surface of the active layer. Thereby, the field concentration in the active layer is relaxed and the high breakdown voltage characteristic, which cannot be expected
from the prior art, can be obtaine | | |
