A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. In one embodiment, to expedite the dispatch of instructions, the first microcode instruction of the cache line is identified during predecode and stored as a microcode pointer. When the cache line is scanned for dispatch, the microcode pointer is used to identify the first microcode instruction which is conveyed to the MROM unit. In another embodiment, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the microcode pointer and the functional bits of the predecode data to multiplex instruction specific bytes of the first microcode instruction to the MROM unit. If the predicted first microcode instruction is not the actual first microcode instruction, then in a subsequent clock cycle, the actual microcode instruction is dispatched the MROM unit and the incorrectly predicted microcode instruction is canceled.

A method, a computer readable storage, and an apparatus estimate a motion of a moving image and comprising a process of adjusting a number of search points per frame by adaptively updating a threshold value per frame to regularly maintain fixed a computational complexity of a video encoder irrespective of characteristics of the moving image.

The present invention provides, in one embodiment, a system and method for concealing video errors. The system includes a coding engine for processing each frame of a video signal to generate macroblocks, selecting a refresh interval based upon network communication parameters, and encoding one or more of the macroblocks as refresh intra-coded macroblocks based upon the selected refresh interval. The refresh intra-coded macroblocks are placed into discrete data packets for transmission across a network to one or more remote devices. Upon receiving other refresh intra-coded macroblocks from a remote device via the network, the coding engine decodes the received intra-coded macroblocks, and places the decoded macroblocks in a newly decoded video frame to be used as reference frame macroblocks for reducing video errors associated with prediction drift.

A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. When the cache line is scanned for dispatch, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the location of the first scanned instruction and the functional bits of the predecode data to multiplex instruction specific bytes of the first scanned instruction to the MROM unit. If the first scanned instruction is not the first microcode instruction, then in a subsequent clock cycle, the first microcode instruction is dispatched the MROM unit and the mispredicted instruction is canceled.

Improved methods of operating a digital data processor to perform binary division include estimating reciprocals of at least selected divisors based on value accessed from a look-up table. For divisors in a first numerical range, the estimation can be based on a value stored in a first look-up table at an index defined by the divisor. For divisors in a second numerical range, the estimation can be based on an index that is a bitwise-shifted function of the divisor. The methods can be applied to scalar and vector binary division.