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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to methods of forming DRAMs
(dynamic random access memory), and more particularly relates to a method
of forming synchronous DRAMs (hereinafter called SDRAM), which operates in
synchronism with an external clock signal provided from an external
source.
2. Description of the Prior Art
There are different types of SDRAMs operating at different frequencies of
an external clock signal. One of such SDRAMs is a low-speed one operating
at 66 MHz, and another is a high-speed one operating at 125 MHz.
The high-speed SDRAMs include a SDRAM which has two data buses provided for
one memory block, and another SDRAM in which one memory block is divided
into two memory blocks.
In consecutive data writing, those high-speed SDRAMs receive two data in a
sequence, synchronized with an external clock signal, within a time period
of two cycles. Those two data are arranged in parallel, and written into
the SDRAMs simultaneously within two cycles, which are called a 2 cycle
pre-fetch operation. In this manner, those SDRAMs realize a high-speed
operation.
In simultaneous data writing of those high-speed SDRAMs, however, data are
required to be written into addresses of consecutive column addresses
within the same row address. Even if a row address is the same, however,
data cannot be simultaneously written into two addresses when their column
addresses are not consecutive. Thus, the high-speed SDRAMs require only
two cycles for consecutive data writing (simultaneous data writing in
actuality) when two addresses have the same row address and consecutive
column addresses. However, four cycles become necessary for writing two
data when two addresses have the same row address but non-consecutive
column addresses.
Nonetheless, the high-speed SDRAMs operate at such a high speed that there
is little problem even though consecutive data writing cannot be conducted
for addresses having the same row address and non-consequtive column
addresses.
On the other hand, the low-speed SDRAMs require consecutive data writing,
regardless of column addresses, for two addresses having the same row
address in order to make up for their low operating speed. Thus, the
low-speed SDRAMs are designed such that consecutive writing operations can
be carried out for two column addresses having the same row address.
It might be convenient if there is a single method of manufacturing both
the low-speed SDRAMs, which can carry out consecutive writing operations
for two addresses having the same row address and arbitrary column
addresses, and the high-speed SDRAMs, which can carry out the 2 cycle
pre-fetch operations for two addresses having the same row address and
consecutive column addresses. Such a method which can readily switch
between the manufacturing of the low-speed SDRAMs and the manufacturing of
high-speed SDRAMs may bring about a significant advantage in the
operations management.
Accordingly, there is a need in the field of SDRAMs for a method of
manufacturing both the low-speed SDRAMs and the high-speed SDRAMs which
can readily switch from the manufacturing of one type of SDRAMs to the
manufacturing of the other type of SDRAMs.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a
method which can satisfy the need described above.
Also, it is another and more specific object of the present invention to
provide a method of manufacturing both the low-speed SDRAMs and the
high-speed SDRAMs which can readily switch from the manufacturing of one
type of SDRAMs to the manufacturing of the other type of SDRAMs.
In order to achieve the above objects, a method of making an SDRAM into
either a low-speed type or a high-speed type according to the present
invention includes the steps of determining an electrical connection of a
predetermined electrode of the SDRAM, and providing the predetermined
electrode with a voltage level defined by the electrical connection,
wherein the voltage level determines whether the SDRAM is made into the
low-speed type or the high speed type, and wherein the low-speed type can
carry out consecutive writing operations at a low clock rate for two
addresses having the same row address, and the high-speed type can carry
out simultaneous writing operations at a high clock rate for two addresses
having the same row address and consecutive column addresses.
According to the present invention, the SDRAM can be made into either the
low-speed SDRAM or the high-speed SDRAM by determining an electrical
connection of the predetermined electrode and providing the predetermined
electrode with a voltage level defined by the electrical connection. A
process of making the SDRAM into either the high-speed SDRAM or the
low-speed SDRAM is simple and easy to implement, so that the process can
readily switch from the manufacturing of one type of SDRAMs to the
manufacturing of the other type of SDRAMs.
It is still another object of the present invention to provide a SDRAM
which can be made into either the low-speed SDRAM or the high-speed SDRAM
through a simple process.
In order to achieve the above object, an SDRAM which can be made into
either a low-speed type or a high-speed type according to the present
invention includes a control circuit controlling an operation of the
SDRAM, and an electrode connected to the control circuit, wherein a
voltage level applied to the electrode determines which one of the
low-speed type or the high-speed type is formed.
According to the present invention, the SDRAM can be made into either the
low-speed SDRAM or the high-speed SDRAM by applying different voltage
level to the electrode. Thus, the present invention can provide an SDRAM
which can be made into either the low-speed SDRAM or the high-speed SDRAM
through a simple process.
Other objects and further features of the present invention will be
apparent from the following detailed description when read in conjunction
with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram for explaining a first embodiment of a method of
forming an SDRAM according to the present invention;
FIG. 2 is a circuit diagram of a write-amplifier-output control-signal
generation circuit forming part of a control circuit of FIG. 1;
FIG. 3 is a circuit diagram of a one-shot pulse generation circuit provided
in the write-amplifier-output control-signal generation circuit of FIG. 2;
FIG. 4 is a circuit diagram of another one-shot pulse generation circuit
provided in the write-amplifier-output control-signal generation circuit
of FIG. 2;
FIG. 5 is a circuit diagram of a write-data latch circuit and a write
amplifier of FIG. 1;
FIG. 6 is an illustrative drawing for explaining the first embodiment of a
method of forming an SDRAM according to the present invention, showing a
case of forming a low-speed SDRAM;
FIG. 7 is an illustrative drawing for explaining the first embodiment of a
method of forming an SDRAM according to the present invention, showing a
case of forming a high-speed SDRAM;
FIG. 8 is a circuit diagram for explaining an operation of the low-speed
SDRAM of the first embodiment;
FIG. 9 is a circuit diagram for explaining an operation of the
write-amplifier-output control-signal generation circuit of FIG. 2 in the
case of the low-speed SDRAM of the first embodiment;
FIG. 10 is a circuit diagram for explaining an operation of the one-shot
pulse generation circuit of FIG. 3 in the case of the low-speed SDRAM of
the first embodiment;
FIG. 11 is a circuit diagram for explaining an operation of the one-shot
pulse generation circuit of FIG. 4 in the case of the low-speed SDRAM of
the first embodiment;
FIG. 12 is a circuit diagram for explaining an operation of the
write-amplifier-output control-signal generation circuit of FIG. 2 in the
case of the low-speed SDRAM of the first embodiment;
FIG. 13 is a circuit diagram for explaining an operation of the one-shot
pulse generation circuit of FIG. 3 in the case of the low-speed SDRAM of
the first embodiment;
FIG. 14 is a circuit diagram for explaining an operation of the one-shot
pulse generation circuit of FIG. 4 in the case of the low-speed SDRAM of
the first embodiment;
FIG. 15 is a time chart for explaining an operation of the
write-amplifier-output control-signal generation circuit of FIG. 2 in the
case of the low-speed SDRAM of the first embodiment;
FIG. 16 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
low-speed SDRAM of the first embodiment;
FIG. 17 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
low-speed SDRAM of the first embodiment;
FIG. 18 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
low-speed SDRAM of the first embodiment;
FIG. 19 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
low-speed SDRAM of the first embodiment;
FIGS. 20A to 20G are time charts for explaining a writing operation of the
low-speed SDRAM of the first embodiment;
FIG. 21 is a circuit diagram for explaining an operation of the high-speed
SDRAM of the first embodiment;
FIG. 22 is a circuit diagram for explaining an operation of the
write-amplifier-output control-signal generation circuit of FIG. 2 in the
case of the high-speed SDRAM of the first embodiment;
FIG. 23 is a time chart for explaining an operation of the
write-amplifier-output control-signal generation circuit of FIG. 2 in the
case of the high-speed SDRAM of the first embodiment;
FIG. 24 is a circuit diagram for explaining an operation of the
write-amplifier-output control-signal generation circuit of FIG. 2 in the
case of the high-speed SDRAM of the first embodiment;
FIG. 25 is a circuit diagram for explaining an operation of the
write-amplifier-output control-signal generation circuit of FIG. 2 in the
case of the high-speed SDRAM of the first embodiment;
FIG. 26 is a circuit diagram for explaining an operation of the
write-amplifier-output control-signal generation circuit of FIG. 2 in the
case of the high-speed SDRAM of the first embodiment;
FIG. 27 is a time chart for explaining the one-shot pulse generation
circuits of the high-speed SDRAM of the first embodiment;
FIG. 28 is a circuit diagram for explaining an operation of the one-shot
pulse generation circuit of FIG. 3 in the case of the high-speed SDRAM of
the first embodiment;
FIG. 29 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
high-speed SDRAM of the first embodiment;
FIG. 30 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
high-speed SDRAM of the first embodiment;
FIG. 31 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
high-speed SDRAM of the first embodiment;
FIG. 32 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
high-speed SDRAM of the first embodiment;
FIG. 33 is a circuit diagram for explaining operations of the write-data
latch circuit and the write amplifier of FIG. 5 in the case of the
high-speed SDRAM of the first embodiment;
FIGS. 34A to 34G are time charts for explaining a writing operation of the
high-speed SDRAM of the first embodiment;
FIG. 35 is a block diagram for explaining a second embodiment of a method
of forming an SDRAM according to the present invention;
FIGS. 36A to 36C are process charts showing each step of a bonding process
according to the present invention;
FIGS. 37A to 37C are process charts showing each step of a wiring process
according to the present invention; and
FIG. 38 is a flow chart of a method of forming an SDRAM according to the
present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the following, embodiment of the present invention will be described
with reference to the accompanying drawings.
FIG. 1 is a block diagram for explaining a first embodiment of a method of
forming SDRAMs according to the present invention. In FIG. 1, a circuit
structure on a chip before the chip is subject to a bonding process is
shown.
The SDRAMs of the first embodiment have two data buses provided for one
memory block. In FIG. 1, a memory block 1 is made up from an array of
memory cells.
2.sub.0, 2.sub.1, . . . , and 2.sub.2n+1 represent columns of the memory
block 1, and BL.sub.j and /BL.sub.j (j=0, 1, . . . , 2n+1) represent a
pair of bit lines provided for each columns 2j. Sense amplifiers 3j are
also provided for each columns 2j.
A word decoder 4 selects and drives one word line among word lines of the
memory block 1 by decoding a row address signal. A column decoder 5
selects one column from columns of the memory block 1 by decoding a column
address signal.
A pair of data bus lines DB.sub.0 and /DB.sub.0 are provided for the even
number columns 2.sub.0, 2.sub.2, . . . , and 2.sub.2n. The data bus line
DB.sub.0 is shared by the bit lines BL.sub.0, BL.sub.2, . . . , and
BL.sub.2n, and the data bus line /DB.sub.0 is shared by the bit lines
/BL.sub.0, /BL.sub.2, . . . , and /BL.sub.2n.
A pair of data bus lines DB.sub.1 and /DB.sub.1 are provided for the odd
number columns 2.sub.1, 2.sub.3, . . . , and 2.sub.2n+1. The data bus line
DB.sub.1 is shared by the bit lines BL.sub.1, BL.sub.3, . . . , and
BL.sub.2n+1, and the data bus line /DB.sub.1 is shared by the bit lines
/BL.sub.1, /BL.sub.3, . . . , and /BL.sub.2n+1.
A data input buffer 6 receives write data, and write-data latch circuits
7.sub.0 and 7.sub.1 latch write data received by the data input buffer 6.
A write amplifier 8.sub.0 is used for writing the write data latched by the
write data latch circuit 7.sub.0 into the memory block 1, and are provided
for the even number columns 2.sub.0, 2.sub.2, . . . , and 2.sub.2n. A
write amplifier 8.sub.1 is used for writing the write data latched by the
write data latch circuit 7.sub.1 into the memory block 1, and are provided
for the odd number columns 2.sub.1, 2.sub.3, . . . , and 2.sub.2n+1.
A data bus amplifier 9.sub.0 amplifies data on the data bus lines DB.sub.0
and /DB.sub.0 read from the memory block 1 via the column decoder 5. A
read-data latch circuit 10.sub.0 latches data which is amplified by the
data bus amplifier 9.sub.0.
A data bus amplifier 9.sub.1 amplifies data on the data bus lines DB.sub.1
and /DB.sub.1 read from the memory block 1 via the column decoder 5. A
read-data latch circuit 10.sub.1 latches data which is amplified by the
data bus amplifier 9.sub.1.
A data output buffer 11 outputs the data latched by the read data latch
circuit 10.sub.0 and 10.sub.1.
A control circuit 12 receives a clock signal CLK, a row address strobe
signal /RAS, a column address strobe signal /CAS, a write control signal
/WE, and a data mask signal DQM form external sources.
A circuit including a bonding pad 13 and a resister 14 provides an
operation mode signal N1H at a node 15. The operation mode signal N1H
determines whether the SDRAM is to operate as a low-speed SDRAM or as a
high-speed SDRAM.
FIG. 2 shows a write-amplifier-output control-signal generation circuit,
which is included in the control circuit 12 and generates a
write-amplifier control signal for controlling the write data output of
the write amplifier 8.sub.0 and 8.sub.1.
In FIG. 2, the least significant bit CA0 of a column address signal
indicates whether the even number columns 2.sub.0, 2.sub.2, . . . , and
2.sub.2n are selected in the memory block 1, or the odd number columns
2.sub.1, 2.sub.3, . . . , and 2.sub.2n+1 are selected.
A write control signal WRITE is generated inside the control circuit 12,
which is set to a high level for writing and to a low level for reading. A
write-amplifier-output control signal /WEN0 is used for controlling the
output of the write amplifier 8.sub.0, and a write-amplifier-output
control signal /WEN1 is used for controlling the output of the write
amplifier 8.sub.1.
A frequency divider 17 divides an external clock signal CLK into half.
Also, the circuit of FIG. 2 includes inverters 18 to 27, NAND circuits 28
to 33, nMOS transistors 34 to 37, pMOS transistors 38 to 41, and one-shot
pulse generation circuits 42 and 43.
FIG. 3 shows a circuit structure of the one-shot pulse generation circuits
42. The one-shot pulse generation circuits 42 includes NAND circuits 45 to
48, delay circuits 49 and 50, a NOR circuit 51, and inverters 50' and 52.
Here, the NAND circuits 46 and 47 together form a RS flip-flop circuit.
FIG. 4 shows a circuit structure of the one-shot pulse generation circuits
43. The one-shot pulse generation circuits 42 includes NAND circuits 54 to
57, delay circuits 58 and 59, a NOR circuit 60, and inverters 59' and 61.
Here, the NAND circuits 55 and 56 together form a RS flip-flop circuit.
The delay circuits 58 and 59 have the same time delays as those of the
delay circuits 49 and 50 of FIG. 3, respectively,
FIG. 5 shows a circuit structure of the write-data latch circuits 7.sub.0
and 7.sub.1 and the write amplifier 8.sub.0 and 8.sub.1. The circuit
structure of FIG. 5 includes NAND circuits 63 and 64, inverters 65 to 84,
NOR circuits 85 and 86, nMOS transistors 87 to 96, and pMOS transistors 97
to 102.
As shown in FIG. 6, when forming a low-speed SDRAM according to the first
embodiment of the present invention, the bonding pad 13 is connected via a
wire 105 to an external node (hereinafter called a VCC power node) 104 to
which a power voltage level VCC is applied. Here, a chip is indicated by
106 and a package is indicated by 107.
On the other hand, when forming a high-speed SDRAM, the bonding pad 13 is
not connected to the VCC power node 104, as shown in FIG. 7.
As shown in FIG. 8, if the bonding pad 13 is connected to the VCC power
node 104 in order to form a low-speed SDRAM, the voltage level of the node
15 becomes VCC. Thus, the operation mode signal N1H having a high level is
obtained.
As a result, as shown in FIG. 9, the inverter 18 of the
write-amplifier-output control-signal generation circuit has a low-level
output. Then, the output of the NAND circuit 28 is fixed to a high level,
so that the NAND circuit 29 works as an inverter for the external clock
signal CLK.
For example, if the external clock signal CLK is 66 MHz, the inverter 19
outputs a signal identical to the external clock signal CLK of 66 MHz.
This signal is supplied to the one-shot pulse generation circuits 42 and
43.
Also, the operation mode signal N1H is the high level, so that the pMOS
transistor 39 is turned off and the nMOS transistor 35 is turned on. Thus,
a node 109 becomes the low level, and the output of the inverter 21
becomes the high level. This leads to the nMOS transistor 34 and the pMOS
transistor 38 being turned on.
Also, the pMOS transistor 41 is turned off, and the nMOS transistor 37 is
turned on. Thus, the output of the inverter 25 becomes the high level.
This leads to the nMOS transistor 36 and the pMOS transistor 40 being
turned on.
In data writing, the write control signal WRITE becomes the high level. If
the column address signal CA0 is set to the high level in the n-th cycle,
for example, the output of the NAND circuit 30 becomes the low level. A
latch circuit comprised of the inverter 22 and the inverter 23 latches the
low level output of the NAND circuit 30 with the output of the inverter 22
being the high level.
Also, the output of the NAND circuit 32 becomes the high level. A latch
circuit comprised of the inverter 26 and the inverter 27 latches the high
level output of the NAND circuit 32 with the output of the inverter 26
being the low level.
As shown in FIG. 10, the output of the NOR circuit 51 is fixed to the low
level in the one-shot pulse generation circuit 42, because the operation
mode signal N1H is the high level. This leads to the outputs of the delay
circuit 50 and the inverter 50' being fixed to the low level and the high
level, respectively. Thus, the NAND circuit 48 serves as an inverter.
Then, in the n-th cycle mentioned above, the output of the inverter 19,
i.e., the external clock signal CLK, becomes the low level. As a result,
the outputs of the NAND circuit 45, the NAND circuit 46, and the NAND
circuit 47 become the high level, the low level, and the high level,
respectively. The output of the inverter 52, i.e., the
write-amplifier-output control signal /WEN0, becomes the high level.
Then, the external clock signal CLK becomes the high level. As a result,
the outputs of the NAND circuit 45, the NAND circuit 46, and the NAND
circuit 47 become the low level, the high level, and the low level,
respectively. The write-amplifier-output control signal /WEN0 becomes the
low level.
Then, the external clock signal CLK becomes the low level again after a
time period shorter than the delay time of the delay circuit 49. As a
result, the output of the NAND circuit 45 is changed to the high level.
However, the outputs of the NAND circuit 46 and the NAND circuit 47 remain
at the high level and the low level, respectively. Also, the
write-amplifier-output control signal /WEN0 stays at the low level.
After the passage of a time period equal to the delay time of the delay
circuit 49, the outputs of the delay circuit 49, the NAND circuit 48, the
NAND circuit 47, and the NAND circuit 46 become the high level, the low
level, the high level, and the low level, respectively. Thus, the
write-amplifier-output control signal /WEN0 becomes the high level.
Thus, the one-shot pulse generation circuit 42 outputs the
write-amplifier-output control signal /WEN0 which has a reversed phase
relationship with and the same frequency as that of the external clock
signal CLK. Also, the write-amplifier-output control signal /WEN0 has a
pulse width equal to the delay time of the delay circuit 49.
If the high level period of the external clock signal CLK is longer than
the delay time of the delay circuit 48, the write-amplifier-output control
signal /WEN0 has the same high level pulse width as that of the external
clock signal CLK.
In the one-shot pulse generation circuit 43, as shown in FIG. 11, the
output of the NOR circuit 60 is fixed to the low level, because the
operation mode signal N1H is the high level. This leads to the outputs of
the delay circuit 59 and the inverter 59' being fixed to the low level and
the high level, respectively. Thus, the NAND circuit 57 serves as an
inverter.
Then, in the n-th cycle mentioned above, the output of the inverter 26
becomes the low level. As a result, the outputs of the NAND circuit 54,
the NAND circuit 55, and the NAND circuit 56 become the high level, the
low level, and the high level, respectively. The output of the inverter
61, i.e., the write-amplifier-output control signal /WEN1, becomes the
high level.
If the column address signal CA0 changes to the low level in the n+1-th
cycle following the n-th cycle mentioned above, the output of the NAND
circuit 30 of the write-amplifier-output control-signal generation circuit
becomes the high level as shown in FIG. 12. A latch circuit comprised of
the inverter 22 and the inverter 23 latches the high level output of the
NAND circuit 30 with the output of the inverter 22 being the low level.
Also, the output of the NAND circuit 32 becomes the low level. A latch
circuit comprised of the inverter 26 and the inverter 27 latches the low
level output of the NAND circuit 32 with the output of the inverter 26
being the high level.
Consequently, in the one-shot pulse generation circuit 42 shown in FIG. 13,
the outputs of the NAND circuit 46, the NAND circuit 47, and the NAND
circuit 48 become the high level, the low level, and the high level,
respectively. The output of the inverter 52, i.e., the
write-amplifier-output control signal /WEN0, becomes the high level.
In the one-shot pulse generation circuit 43 shown in FIG. 14, when the
output of the inverter 19, i.e., the external clock signal CLK is the low
level, the outputs of the NAND circuit 54, the NAND circuit 55, and the
NAND circuit 56 become the high level, the low level, and the high level,
respectively. The output of the inverter 61, i.e., the
write-amplifier-output control signal /WEN1, becomes the high level.
Then, the external clock signal CLK becomes the high level. As a result,
the outputs of the NAND circuit 54, the NAND circuit 55, and the NAND
circuit 56 become the low level, the high level, and the low level,
respectively. The write-amplifier-output control signal /WEN1 becomes the
low level.
Then, the external clock signal CLK becomes the low level again after a
time period shorter than the delay time of the delay circuit 58. As a
result, the output of the NAND circuit 54 is changed to the high level.
However, the outputs of the NAND circuit 55 and the NAND circuit 56 remain
at the high level and the low level, respectively. Also, the
write-amplifier-output control signal /WEN1 stays at the low level.
After the passage of a time period equal to the delay time of the delay
circuit 58, the outputs of the delay circuit 58, the NAND circuit 57, the
NAND circuit 56, and the NAND circuit 55 become the high level, the low
level, the high level, and the low level, respectively. Thus, the
write-amplifier-output control signal /WEN1 becomes the high level.
Thus, the one-shot pulse generation circuit 43 outputs the
write-amplifier-output control signal /WEN1 which has a reversed phase
relationship with and the same frequency as that of the external clock
signal CLK. Also, the write-amplifier-output control signal /WEN1 has a
pulse width equal to the delay time of the delay circuit 58.
If the high level period of the external clock signal CLK is longer than
the delay time of the delay circuit 58, the write-amplifier-output control
signal /WEN1 has the same high level pulse width as that of the external
clock signal CLK.
FIG. 15 shows relations between the external clock signal CLK, the column
address signal CA0, and the write-amplifier-output control signal /WEN0
and /WEN1. Those relations are observed in data writing described above,
when the column address signal CA0 changes from the high level to the low
level.
As a result, the write-data latch circuits 7.sub.0 and 7.sub.1 and the
write amplifiers 8.sub.0 and 8.sub.1 operate as shown in FIG. 16 to FIG.
19.
In the write-data latch circuit 7.sub.0, the outputs of the NOR circuit 85
and the inverter 70 are the low level and the high level, respectively,
because the operation mode signal N1H is the high level. This leads to the
nMOS transistor 89 and the pMOS transistor 99 being turned on.
In the write-data latch circuit 7.sub.1, the outputs of the NOR circuit 86
and the inverter 80 are the low level and the high level, respectively,
because the operation mode signal N1H is the high level. This leads to the
nMOS transistor 94 and the pMOS transistor 102 being turned on.
In data writing, the write control signal WRITE becomes the high level. If
the column address signal CA0 is set to the high level in the n-th cycle
as described above while the external clock signal CLK is the low level,
the output of the NAND circuit 63 becomes the high level. Thus, the output
of the inverter 65 becomes the low level, which leads to the nMOS
transistor 87 and the pMOS transistor 97 being turned on and to the nMOS
transistor 88 and the pMOS transistor 98 being turned off.
In the write-data latch circuit 7.sub.1, the output of the NAND circuit 64
becomes the high level. Thus, the output of the inverter 77 becomes the
low level, which leads to the nMOS transistor 92 and the pMOS transistor
100 being turned on and to the nMOS transistor 93 and the pMOS transistor
101 being turned off.
As a result, when the write data DQ is DI.sub.n, the write data DI.sub.n is
latched by a latch circuit comprised of the inverters 66 and 67, and,
also, latched by a latch circuit comprised of the inverters 75 and 76. The
outputs of the inverters 66 and 75 are /DI.sub.n and /DI.sub.n,
respectively.
At this point of time, both of the write-amplifier-output control signals
/WEN0 and /WEN1 are the high level. Thus, in the write amplifier 8.sub.0,
the output of the inverter 71 is the low level, and the nMOS transistors
90 and 91 are turned off. In the write amplifier 8.sub.1, the output of
the inverter 83 is the low level, and the nMOS transistors 95 and 96 are
turned off.
When the external clock signal CLK changes to the high level as shown in
FIG. 17, the output of the NAND circuit 63 becomes the low level in the
write-data latch circuit 7.sub.0. Thus, the output of the inverter 65
becomes the high level, which leads to the nMOS transistor 87 and the pMOS
transistor 97 being turned off and to the nMOS transistor 88 and the pMOS
transistor 98 being turned on.
At this point of time, the write-amplifier-output control signal /WEN0 is
the low level. Thus, the output of the inverter 7.sub.1 becomes the high
level in the write amplifier 8.sub.0, and the nMOS transistors 90 and 91
are turned on.
As a result, a latch circuit comprised of the inverters 68 and 69 latches
the reversed write data /DI.sub.n with the output of the inverter 68 being
DI.sub.n. Thus, the latch circuit comprised of the inverters 72 and 73
latches the write data DI.sub.n with the output of the inverter 72 being
/DI.sub.n. This leads to the output of the inverter 74 being DI.sub.n, so
that the data bus lines DB.sub.0 and /DB.sub.0 become /DI.sub.n and
DI.sub.n, respectively.
In the write-data latch circuit 7.sub.1, the output of the NAND circuit 64
stays at the high level. Thus, the output of the inverter 77 stays at the
low level, which leads to the nMOS transistor 92 and the pMOS transistor
100 remaining turned on and to the nMOS transistor 93 and the pMOS
transistor 101 remaining turned off.
At this point of time, the write-amplifier-output control signal /WEN1
remains at the high level. Thus, the output of the inverter 83 stays at
the low level in the write amplifier 8.sub.1, and the nMOS transistors 95
and 96 remain turned off.
Then, the cycle becomes the n+1-th cycle. As shown in FIG. 18, if the
column address signal CA0 becomes the low level, the output of the NAND
circuit 63 becomes the high level in the write-data latch circuit 7.sub.0.
This is the case while the external clock signal CLK is the low level. The
output of the inverter 65 becomes the low level, which leads to the nMOS
transistor 87 and the pMOS transistor 97 being turned on and to the nMOS
transistor 88 and the pMOS transistor 98 being turned off.
At this time, the write-amplifier-output control signal /WEN0 becomes the
high level, so that the output of the inverter 71 becomes the low level.
Thus, the nMOS transistors 90 and 91 are turned off.
As a result, when the write data DQ is DI.sub.n+1, the write data
DI.sub.n+1 is latched by a latch circuit comprised of the inverters 66 and
67 with the output of the inverter 66 being /DI.sub.n+1.
In the write-data latch circuit 7.sub.1, the output of the NAND circuit 64
becomes the high level. The output of the inverter 77 becomes the low
level, which leads to the nMOS transistor 92 and the pMOS transistor 100
being turned on and to the nMOS transistor 93 and the pMOS transistor 101
being turned off.
As a result, when the write data DQ is DI.sub.n+1, the write data
DI.sub.n+1 is latched by a latch circuit comprised of the inverters 75 and
76 with the output of the inverter 75 being /DI.sub.n+1.
At this point of time, the write-amplifier-output control signal /WEN1
stays at the high level, so that the output of the inverter 83 remains at
the low level. Thus, the nMOS transistors 95 and 96 remain turned off.
When the external clock signal CLK changes to the high level as shown in
FIG. 19, the output of the NAND circuit 63 stays at the high level in the
write-data latch circuit 7.sub.0. Thus, the output of the inverter 65
stays at the low level, which leads to the nMOS transistor 87 and the pMOS
transistor 97 remaining turned on and to the nMOS transistor 88 and the
pMOS transistor 98 remaining turned off.
At this point of time, the write-amplifier-output control signal /WEN0
remains at the high level. Thus, the output of the inverter 71 remains at
the low level in the write amplifier 8.sub.0, and the nMOS transistors 90
and 91 remain turned off.
In the write-data latch circuit 7.sub.1, the output of the NAND circuit 64
becomes the low level. The output of the inverter 77 becomes the high
level, which leads to the nMOS transistor 92 and the pMOS transistor 100
being turned off and to the nMOS transistor 93 and the pMOS transistor 101
being turned on.
At this point of time, the write-amplifier-output control signal /WEN1
becomes the low level, so that the output of the inverter 83 becomes the
high level. Thus, the nMOS transistors 95 and 96 are turned on.
As a result, the latch circuit comprised of the inverters 78 and 79 latches
the reversed write data /DI.sub.n+1 with the output of the inverter 78
being DI.sub.n+1. Thus, the latch circuit comprised of the inverters 81
and 82 latches the write data DI.sub.n+1 with the output of the inverter
81 being /DI.sub.n+1. This leads to the output of the inverter 84 being
DI.sub.n+1, so that the data bus lines DB.sub.1 and /DB.sub.1 become
/DI.sub.n+1 and DI.sub.n+1, respectively.
FIGS. 20A to 20G show a case in which consecutive data writing is carried
out with regard to the column addresses 0, 1, 16, 17, 31, and 38.
FIG. 20A shows the external clock signal CLK, FIG. 20B shows the row
address strobe signal /RAS, FIG. 20C shows the column address strobe
signal /CAS, FIG. 20D shows the address signal ADD, FIG. 20E shows the
input data DQ, FIG. 20F shows the data mask signal DQM, and FIG. 20G shows
the column selection signal CL.
In FIG. 20D to FIG. 20F, 00, 01, 16, 17, 31, and 38 indicate the column
addresses 0, 1, 16, 17, 31, and 38, respectively.
At a 0th cycle, when the row address strobe signal /RAS is changed to the
low level, an address signal provided at the address signal input node is
latched as a row address signal. This data latch is carried out at a
positive edge of the external clock signal CLK. The row address signal is
decoded to select a word line.
The column address strobe signal /CAS is changed to the low level at a
third cycle, for example. Then, at a positive edge of the external clock
signal CLK, the column address signal indicating the 0th column address at
the address input node is latched.
Also, at the same positive edge of the external clock signal CLK, data
provided at the data input/output node is latched by the write-data latch
circuit 7.sub.0. This data is the data which is to be written into the
column address 0.
During a high level period of the external clock signal CLK, the data
latched in the write-data latch circuit 7.sub.0 is written into the column
address 0.
Then, at a fourth cycle, the column address strobe signal /CAS is changed
to the high level. At a positive edge of the external clock signal CLK,
data provided at the data input/output node to be written into the column
address 1 is latched by the write-data latch circuit 7.sub.1.
During a high level period of the external clock signal CLK, the data
latched in the write-data latch circuit 7.sub.1 is written into the column
address 1.
At a fifth cycle, the column address strobe signal /CAS is changed to the
low level. Then, at a positive edge of the external clock signal CLK, a
column address signal indicating the column address 16 at the address
signal input node is latched.
Also, at the same positive edge of the external clock signal CLK, data
provided at the data input/output node to be written into the column
address 16 is latched by the write-data latch circuit 7.sub.0.
During a high level period of the external clock signal CLK, the data
latched in the write-data latch circuit 7.sub.0 is written into the column
address 16.
At a sixth cycle, the column address strobe signal /CAS is changed to the
high level. At a positive edge of the external clock signal CLK, data
provided at the data input/output node to be written into the column
address 17 is latched by the write-data latch circuit 7.sub.1.
During a high level period of the external clock signal CLK, the data
latched in the write-data latch circuit 7.sub.1 is written into the column
address 17.
At a seventh cycle, the column address strobe signal /CAS is changed to the
low level. At a positive edge of the external clock signal CLK, data
provided at the data input/output node to be written into the column
address 31 is latched by the write-data latch circuit 7.sub.1.
During a high level period of the external clock signal CLK, the data
latched in the write-data latch circuit 7.sub.1 is written into the column
address 31.
At an eighth cycle, the column address strobe signal /CAS remains to the
low level. At a positive edge of the external clock signal CLK, data
provided at the data input/output node to be written into the column
address 38 is latched by the write-data latch circuit 7.sub.0.
During a high level period of the external clock signal CLK, the data
latched in the write-data latch circuit 7.sub.01 is written into the
column address 38.
In the manner as described above, the low-speed SDRAM produced according to
the first embodiment of the present invention can carry out consecutive
data writing operations for column addresses having the same row address
at a low clock rate such as the 66 MHz of the external clock signal CLK.
On the other hand, when producing a high-speed SDRAM shown in FIG. 7, the
bonding pad 13 is not connected to the VCC power node 104. In this case,
as shown in FIG. 21, the voltage level of the node 15 becomes the ground
level 0 V, so that the operation mode signal N1H becomes the low level.
As a result, as shown in FIG. 22, the output of the inverter 18 of the
write-amplifier-output control-signal generation circuit becomes the high
level. Thus, the external clock signal CLK, the output of the frequency
divider 17, the output of the inverter 18, the output of the NAND circuit
28, the output of the NAND circuit 29, and the output of the inverter 19
as shown in FIG. 23 are obtained.
With the external clock signal CLK of such frequency as 125 MHz, the
inverter 19 generates an internal clock signal which has half the
frequency and the same high-level pulse width as that of the external
clock signal CLK. This internal clock signal is then supplied to the
one-shot pulse generation circuits 42 and 43.
With reference to FIG. 22, since the operation mode signal N1H is at the
low level, the pMOS transistor 39, the nMOS transistor 35, the pMOS
transistor 41, and the nMOS transistor 37 are turned on, off, on, and off,
respectively.
The write control signal WRITE becomes the high level at the time of data
writing. When the column address signal CA0 is changed to the high level
at an n-th cycle, for example, the outputs of the NAND circuits 30 and 32
become the low level and the high level, respectively.
In this case, when the external clock signal CLK is the low level, the
outputs of the NAND circuit 31 and the inverter 21 become the high level
and the low level, respectively, with the nMOS transistor 34 and the pMOS
transistor 38 being turned off.
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