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BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
This invention relates to a method and process for attaching an
electrically conductive substance onto substrates and, in particular, a
process that provides attachment of solder bumps onto substrates, with
particular advantages in applications in which a pitch of less than 400
microns is required.
BACKGROUND
Enormous research and development resources are spent the world over in the
perennial search for low cost, high volume methods of producing and
assembling integrated circuits or "chips". An integral piece of chip
assembly is making electrical interconnections. Solder bumped flip chip
technology has become extremely popular because it provides a tiny
semiconductor die with terminations all on one side (in the form of solder
pads or bumps); after the chip surface has been treated, it can be flipped
over and attached to a matching substrate. To make the connection, flip
chip technology includes techniques for affixing bumps of electrically
conductive material onto substrates, including boards, packages and chips.
Flip chip bumping techniques have also proven useful in tape automated
bonding (TAB). Other applications for solder bumps have included
opto-electronics and silicon-on-silicon interconnects.
Flip chip technology presents a number of advantages that make it a
preferred form of electronic interconnect. Flip chip provides improved
electrical performance. Flip chip interconnections are the most efficient
electrical interconnections for high frequency applications such as main
frames and computer workstations. In addition to efficiency in function,
the flip chip is efficient in form because of its small size. As devices
of ever greater power are reduced in size, flip chip provides the smallest
interconnect option. Other advantages include easier thermal management
and reduced EMI emmissions and reduced RFI susceptibility.
Solder bump flip chip assembly can be made compatible with well-established
Surface Mount Technology (SMT). (For a thorough introduction to SMT,
please refer to the Handbook of Surface Mount Technology, Stephen W.
Hinch, Longman Scientific & Technical, UK, 1988.) With the appropriate
choice of solder bump metallurgy, an SMT assembly line can simultaneously
assemble both flip chip and surface mount packages on a product passing
through the line. This compatibility provides the utilization of an
installed base of SMT assembly lines as well as the flexibility of
designing packages incorporating flip chip into larger SMT packages.
Perhaps the most telling advantage of flip chip over other packaging
technologies is its lower cost. Flip chip eliminates an entire level of
interconnect--the package level (see Steps B through E in FIG. 2). By
eliminating the package level, system cost is significantly reduced. In
the IC business generally, the potential cost savings justify investments
in multi-million dollar flip chip technology research.
The primary way of making flip chip interconnects is with solder bumps.
Solder bumps have been applied by evaporation, electroplating, stencil
printing and serial methods. However, each of these methods has particular
limitations and much research has been and is being performed to overcome
the limitations of each of these methods.
For the past three decades, companies such as IBM have used evaporation to
form high lead (Pb) bumps for flip chip applications. One major
disadvantage of evaporation is the high cost: at least ten million dollars
worth of capital equipment is required. Processing costs are also high due
to tooling and mask costs, process delays, low throughput, low yields, and
necessarily frequent manual removal of hazardous lead waste. Finally,
alloy compositions are limited because many metals are not suitable for
evaporation. Especially limiting is the fact that the deposition rate of
tin (Sn) is such that it cannot readily be evaporated. A high tin alloy
(63Sn-37Pb, that is "eutectic") is highly desirable as a bumping material,
because the melting point of eutectic tin (T.sub.m =183 degrees C.) is
compatible with existing SMT materials and processes (usually performed at
200-210 degrees C.). By contrast, the melting point of lead is 327 degrees
C., a temperature that would melt many of the organic materials used in
SMT (e.g. epoxy circuit beards, whose maximum temperature is 230 degrees
C., and other components).
There is no shortage of patents that have issued covering improvements in
the evaporation process. Because the evaporation process involves
vaporizing lead and allowing the lead to deposit on all surfaces, both
masked and unmasked, the cleaning of the metal shadow mask is messy and
hazardous. The metal mask can only be reused three or four times before it
is no longer cleanable and must be discarded. The waste lead, including
the lead-encrusted metal mask, poses environmental and worker safety
problems as well as escalates manufacturing expense. A recent patent, U.S.
Pat. No. 5,152,878, addressed the problem of mask cleaning and presented
some labor saving cleaning techniques. However, although improvements may
speed bumping and reduce labor costs to a certain degree, the equipment
required for evaporation remains costly, and the hazards of the waste lead
are ever-present.
Whereas the evaporation technique is fraught with the hazards of vaporizing
lead, electroplating is a wet technique using chemical baths as the medium
in which to deposit bumps. The chemical baths contain lead and other
hazardous materials that pose a handling and disposal problem. Moreover,
electroplating is limited in efficiency because it is a batch process.
Thus, volume production faces the attendant challenges of an equipment
intense serial process and, as IC manufacturers are all too keenly aware,
cost is governed by the production volume or capacity limits. Other
disadvantages of electroplating include difficulty in alloy composition
control, problems in consistently achieving acceptable bump height at
small bump pitches, and difficulty in the elimination of surface
impurities.
Stencil printing (also known as screen printing), depicted in FIG. 2A, is
by far the simplest approach, at least conceptually, but has posed
seemingly insurmountable limitations on bump size and pitch. (See,
generally, Handbook of Surface Mount Technology, ibid, pp 245-260).
As depicted in FIG. 2A, stencil printing involves placing a mask 10 or
screen on a substrate 12, slathering on a solder paste on top of the mask,
using a squeegee 16 to squeegee the paste, which serves to force paste
into all the apertures in the mask and to scrape off the excess paste, and
removing the mask prior to re-flowing the solder paste. Re-flow is
essentially controlled melting in order that the small spheres of metal
that compose the solder paste coalesce to form the electronic
interconnect.
Packing more interconnects on smaller chip has created a need for smaller
bumps with smaller pitch (pitch being the distance between the centers of
two adjacent bumps). Conventional stencil printing methods have had a
lower pitch limit of 400 microns, primarily due to the limitations on
well-established stencil aspect ratio (about 2.5:1) of aperture width
relative to mask thickness. This limit is the result of the interplay of
the spacing of holes in and thickness of the stencil and the physical and
chemical characteristics of the solder paste. The well-known pitch
limitation convinced IC manufacturers that stencil printing had no future
in the majority of flip chip bumping applications since a pitch of less
than 400 microns is required.
AT&T has used stencil printing to produce silicon-on-silicon assemblies.
The process involves mounting the mask, joining the silicon to silicon
with stenciled paste between the silicon components, and reflowing,
thereby producing a silicon-on-silicon attach. The mask apertures are
limited by the aspect ratio.
Serial methods have been proposed, and while attractive in theory, none has
been commercialized. Proposed methods have included "stud-bumping" with
wirebonding equipment (also known as "wirebond bumps"), decal processing,
and solder jet processes. Methods proposed to simplify serial processes
still require multiple steps. U.S. Pat. No. 5,156,997 issued to Kumar et
al. describes a simplified process consisting of depositing a barrier and
diffusion layer, forming a bump from a metal using a focused liquid metal
ion source, and removing the exposed barrier/adhesion layer by etching.
The process takes over 13 hours to bump a 200 die wafer. Thus, even
simplified serial processing has associated processing disadvantages such
as slow throughput.
A dramatic and significant improvement would be a simple, low cost, high
volume, environmentally friendly (or environmentally neutral),
non-hazardous process for applying bumps of various alloys to substrate
where the bumps are uniform in height and the pitch small, and, ideally,
such a method would provide bump alloys that are compatible with existing
surface mount technology assembly lines.
SUMMARY OF THE INVENTION
The invention provides a non-hazardous, environmentally neutral process for
bumping substrates (including silicon wafers) for electronic
interconnects. The inventive process provides for Contained Paste
Deposition (CPD) on masked substrate with mask attached during reflow. The
process provides for bumps that are suitable for flip chip application
with pitches of less than 400 microns. Process cost is further lowered by
inventive aspects including a reusable metal mask in one embodiment, and a
photoimageable polymer coating, removable or not, in other embodiments.
Further, this method uses manufacturing technology that is
well-characterized and suitable for volume production.
CPD separates the composition control of the bump from the volume control
of the bump. For example, in evaporation and plating, the volume and
composition are determined simultaneously in a single process step. With
CPD, the composition of the metal is determined during the paste
manufacture; while the process of forming the bumps determines the volume
of the metal bump.
Virtually any alloy composition can be used to bump wafers according to the
present invention. The limitations of evaporation methods are completely
overcome because CPD allows the selection of any alloy, whereas many
alloys cannot be effectively evaporated. When compatibility with SMT is
desirable, melting point characteristics are essentially the only
limitation in alloy selection. The inventive method provides more precise
control of the alloy composition than currently achievable in alloy and
elemental plating methods. The present method provides solutions to
environmental and worker safety issues associated with current methods of
applying lead (Pb) via evaporation or the chemical waste produced by
plating baths. Consistent bump height, volume, and spacing can be
accomplished.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1, 1A and 1B inclusive, depicts cross-sections of the
mask/paste/substrate and mask/bump/substrate assembly according to the
invention.
FIG. 2, 2A through 2I inclusive, represents conventional stencil method,
conventional SMT packaging, and conventional stencil method as used in the
SMT assembly process.
FIG. 3, 3A through 3H, represents flip chip bump formation and flip chip
assembly according to the invention.
FIG. 4 as a flow chart of the bump formation method according to the
present invention.
FIG. 5 illustrates the assembling of mask upon the substrate in the
preferred embodiment.
FIG. 6, 6A through 6C inclusive, represents the invention providing
attached stand-off bumps.
FIG. 7 represents CPD providing controlled-volume ball production.
DETAILED DESCRIPTION OF THE INVENTION
As outlined in FIG. 4, the inventive method generally includes the steps of
selecting 410 a substrate, mask and paste; assembling 412 the substrate
and mask; aligning 414 the substrate-mask, depositing 416 the paste;
reflowing 422 the substrate-mask-paste, removing 424 the mask; cleaning
430 the mask; reusing the mask in another repetition of the process. Other
embodiments eliminate the step of mask removal 424; still others include
intermediate inspection 418, 426 and touch-up 420, 428 steps to ensure the
uniform thickness of solder paste deposition and ball placement. If a
nonwettable substrate is used, then rather than a bumped substrate, the
method generates solder ball of controlled volume.
FIG. 3, A through H inclusive, illustrates the inventive process. FIG. 3A
through 3E illustrates flip chip bump formation and FIG. 3F through 3H
illustrates flip chip assembly. The selected substrate 320 having a
surface 321 or active side selected for the formation of electrical
interconnections to which wettable or solderable regions 322 or solderable
bump limiting metal (BLM) regions have been attached. In the preferred
embodiment, the substrate chosen is a silicon wafer with a BLM that is
wettable by the alloy to be deposited. Silicon wafer with zincated pads
(Al pads treated with electro-less Zn, Ni, then Au plated), and passivated
with SiN (silicon nitride) is the substrate/BL,M combination of the
preferred embodiment. It is simple and effective to prepare a wafer with
solderable (or wettable) BLMs on a pitch of 400 microns or less. The
center-to-center distance between each wettable BLM corresponds to the
pitch of the bumps; the preferred embodiment provides for pitches in the
range of 150 to 350 microns. This minimum pitch limitation is currently a
function of mask technology, and even smaller pitches are achievable with
the present invention with improvements in mask fabrication technology.
The remaining regions of the substrate surface 321 must be non-wettable
regions 324 (for example, regions of the substrate covered by non-wettable
materials, such as polyimide, silicon nitride, or, silicon dioxide). In
the preferred embodiment for 63Sn-37Pb bumps, the silicon wafer has
wettable regions of Ni-Au and nonwettable regions of silicon nitride.
A pair of cross-sections of the mask/substrate/paste and mask/substrate
bump assem | | |
