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Semiconductor device having transistor pair
   
Document Number
US Patent 5541431
Issued Date
July 30, 1996
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Abstract
A semiconductor device has a plurality of transistor pairs. Each transistor pair includes a p-channel current path having a pair of p-type current terminal regions arranged by sandwiching a high resistivity of a first channel region, an n-channel current path having a pair of n-type current terminal regions arranged by sandwiching a high resistivity of a second channel region. The first channel region and the second channel region exert each electric field on each other by their intrinsic charges and are adjacently arranged so as to serve as a gate.
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Semiconductor device having transistor pair - US Patent 5541431 Drawing
Drawing from US Patent 5541431
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Number of Claims:
26
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Owner
Fujitsu Limited (Kawasaki,JP)
Published
July 30, 1996
Application Number
07/817,801
Filed
January 9, 1992
US Classification
257/347   257/348 257/350 257/E27.064 257/E27.099 257/E27.1 257/E27.112 257/E29.151
Int'l Classification
H01L   29/49   (20060101)   H01L   27/092   (20060101)   H01L   27/085   (20060101)   H01L   27/11   (20060101)   H01L   29/40   (20060101)   H01L   27/12   (20060101)  
Priority Data
Jan 09, 1991 [JP] 3-000987 Jan 09, 1991 [JP] 3-000988
USPTO Field of Search
257/347   257/348   257/350  
Related Patents
6552396 - Matched transistors and methods for forming the same - Owned by International Business Machines Corporation (Armonk, NY)

An SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region has a width and extends from a surface of the substrate layer downward into contact with the insulator layer along a portion of the width and extends only partially into the substrate layer along another portion of the width. The SOI multiple FET structure also includes a pair of gates on the surface of the substrate layer each overlapping one of the distal diffusion regions and the central diffusion region; and a pair of body regions in the substrate layer each under one of the gates for forming a channel between the one of the distal diffusion regions and the central diffusion region. The body regions are in electrical communication under the another portion of the width of the central diffusion region. Methods for forming the SOI multiple FET structure are also provided.

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Description
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