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Carrier for testing an unpackaged semiconductor die    
United States Patent5541525   
Link to this pagehttp://www.wikipatents.com/5541525.html
Inventor(s)Wood; Alan G. (Boise, ID); Farnworth; Warren M. (Nampa, ID); Hembree; David R. (Boise, ID)
AbstractA carrier for testing an unpackaged semiconductor die is provided. The carrier includes: a base; a temporary interconnect for establishing electrical communication between the die and external test circuitry; a retention mechanism for securing the interconnect to the base; and a force distribution mechanism for biasing the die and interconnect together. The interconnect includes a substrate having raised contact members adapted to penetrate bond pads, or tests pads, on the die to form an electrical connection. Conductive traces are formed on the substrate in electrical communication with the raised contact members and connect to external connectors formed on the base. The interconnect is adapted for testing a particular type of die but is interchangeable with other interconnects to permit testing of different types of dice using a universal carrier.



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Patent Text Patent PDF Print Page Summary File History
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Drawing from US Patent 5541525
Carrier for testing an unpackaged semiconductor die - US Patent 5541525 Drawing
Carrier for testing an unpackaged semiconductor die
Inventor     Wood; Alan G. (Boise, ID); Farnworth; Warren M. (Nampa, ID); Hembree; David R. (Boise, ID)
Owner/Assignee     Micron Technology, Inc. (Boise, ID)
Patent assignment
All assignments
Publication Date     July 30, 1996
Application Number     08/345,064
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     November 14, 1994
US Classification     324/755 257/E21.512 257/E21.525 257/E23.004 257/E23.069 257/E23.07 324/754 324/765
Int'l Classification     G01R 031/02 G01R 001/073
Examiner     Karlsen; Ernest F.
Assistant Examiner    
Attorney/Law Firm     Gratton; Stephen A.
Address
Parent Case     CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of application Ser. No. 08/124,899 filed Sep. 21, 1993, now U.S. Pat. No. 5,495,179, which is a continuation-in-part of application Ser. No. 08/046,675, filed Apr. 14, 1993, now U.S. Pat. No. 5,367,253, which is a continuation-in-part of application Ser. No. 07/973,931 filed on Nov. 10, 1992, now U.S. Pat. No. 5,302,891, which is a continuation of application Ser. No. 07/709,858, filed Jun. 4, 1991, abandoned.
Priority Data    
USPTO Field of Search     324/755 324/754 324/757 324/158.1 324/765
Patent Tags     carrier testing unpackaged semiconductor die
   
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 U.S. References
 
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ReferenceRelevancyCommentsReferenceRelevancyComments
5326428
Farnworth
324/724
Jul,1994

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5323035
Leedy
257/248
Jun,1994

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5302891
Wood
324/765
Apr,1994

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5264787
Woith
324/758
Nov,1993

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5249450
Wood
72/359
Oct,1993

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5177438
Littlebury
324/754
Jan,1993

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5177439
Liu
324/754
Jan,1993

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5173451
Kinsman
438/15
Dec,1992

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5123850
Elder
439/67
Jun,1992

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5103557
Leedy

Apr,1992

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5088190
Malhi

Feb,1992

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5073117
Malhi

Dec,1991

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5072116
Kawade

Dec,1991

[0 after 0 votes]
5006792
Malhi
324/762
Apr,1991

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4963225
Lehman-Lamer
216/18
Oct,1990

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4952272
Okino
216/11
Aug,1990

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Blonder
257/739
Jun,1990

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4924589
Leedy
438/6
May,1990

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Bendat
228/105
Feb,1990

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4899107
Corbett
324/765
Feb,1990

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Reid
324/757
Apr,1986

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4312117
Robillard
438/107
Dec,1969

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 Technical Review Submit all comments and votes
 Claims Submit all comments and votes
 


What is claimed is:

1. An apparatus for testing an unpackaged semiconductor die comprising:

a base formed with sidewalls and a cavity;

a plate with a support surface, said plate adapted for attachment to the base such that the support surface is contained within the cavity;

an interconnect mounted to the support surface, said interconnect including a substrate and a contact member formed on the substrate adapted to contact a contact location on the die, and a conductive trace in electrical communication with the contact member;

an external retention contact mounted to the base and extending into the cavity for contacting the conductive trace as the plate is attached to the base to retain the interconnect on the support surface and to establish electrical communication between the conductive trace and test circuitry; and

a force distribution mechanism clipped to the base for biasing the die and interconnect together.

2. The apparatus as claimed in claim 1 and wherein the interconnect is interchangeable with other interconnects to permit testing of different types of die using the carrier.

3. The apparatus as claimed in claim 1 and wherein the retention contact is adapted to press against the conductive trace on the interconnect at a first end and to electrically connect to test circuitry at a second end.

4. The apparatus as claimed in claim 1 and wherein the force distribution mechanism includes a pressure plate for contacting the die, a bridge plate attachable to the base and a spring sandwiched between the pressure plate and bridge plate.

5. The apparatus as claimed in claim 4 and wherein the pressure plate and bridge plate each include an aperture to permit the die to be attached to the pressure plate using an assembly tool.

6. The apparatus as claimed in claim 1 and wherein the contact member on the interconnect is formed as a mesa with a raised projection adapted to penetrate the contact location on the die to a penetration depth.

7. The apparatus as claimed in claim 1 and wherein the contact member on the interconnect is formed as a thick film contact using an ultrasonic forging process and the substrate is a material selected from the group consisting of silicon, ceramic, silicon-on-glass, silicon-on sapphire, and germanium.

8. The apparatus as claimed in claim 1 and wherein the contact member on the interconnect is a microbump contact mounted to a flexible tape and attached to the substrate.

9. A carrier for testing an unpackaged semiconductor die, comprising:

a carrier base having a cavity;

a plate with a support surface, said plate adapted for attachment to the base such that the support surface is contained within the cavity;

an interconnect mountable to the support surface, said interconnect comprising a substrate having a raised contact member adapted to penetrate a contact location on the die, said interconnect further comprising an electrically conductive trace in electrical communication with the contact member and terminating in a contact pad;

an external retention contact attached to the carrier base and extending into the cavity to abut the contact pad as the plate is attached to the base to retain the interconnect and establish electrical communication between the contact member on the interconnect and test circuitry; and

a force distribution mechanism for biasing the interconnect and die together, said force distribution mechanism including a pressure plate for abutting the die, a bridge plate clipped to the base and a spring sandwiched between the pressure plate and bridge plate for exerting a biasing force on the pressure plate.

10. The carrier as claimed in claim 9 and further comprising a second interconnect interchangeable with the interconnect to permit testing of another semiconductor die having a different configuration than the die.

11. The carrier as claimed in claim 9 and wherein the spring is formed as a spring member selected from the group consisting of wave washer, cylindrically curved washer, belleville washer, compress ion spring, and canted coils spring.

12. The carrier as claimed in claim 9 and wherein the substrate is formed of silicon and the contact members are formed as raised mesas having raised self-limiting projections.

13. The carrier as claimed in claim 9 and wherein the contact members have a conical base and a tip formed by an ultrasonic forging process.

14. The carrier as claimed in claim 9 and wherein the contact members are formed as microbumps mounted on an etched tape.

15. The carrier as claimed in claim 14 and wherein the contact members include a rough textured surface.

16. A carrier for testing an unpackaged semiconductor die, comprising:

a base having a cavity;

a plate with a support surface, said plate adapted for attachment to the base such that the support surface is contained within the cavity;

an interconnect placed on the support surface, said interconnect including raised contact members formed on a substrate and a pattern of conductive traces in electrical communication with the raised contact members, with the raised contact members adapted to penetrate contact locations on the die and the interconnect interchangeable with a second interconnect adapted to test a second die;

a plurality of external retention contacts attached to the base and extending into the cavity for contacting and retaining the interconnect on the support surface as the plate is attached to the base and for establishing an electrically conductive path between the circuit traces and test circuitry; and

a force distribution mechanism removably clipped to the base for exerting a biasing force on the die, said force distribution mechanism including a spring sandwiched between a pressure plate that presses against the die and a bridge clamp attached to the base.

17. The carrier as claimed in claim 16 and wherein the carrier base includes side walls and the retention contacts mount to the side walls.

18. The apparatus as claimed in claim 16 and wherein the contact member on the interconnect is formed as a mesa with a raised projection adapted to penetrate the contact location on the die to a penetration depth.
 Description Submit all comments and votes
 


This application is related to applications Ser. No. 07/788,065 filed Nov. 5, 1991, now U.S. Pat. No.5,440,240; Ser. No. 07/953,750 filed Sep. 29, 1992, abandoned; Ser. No. 08/073,005 filed Jun. 7, 1993, now U.S. Pat. No. 5,408,190; Ser. No. 08/073,003 filed Jun. 7, 1993; Ser. No. 08/120,628 filed Sep. 13, 1993; Ser. No. 07/896,297 filed Jun. 10, 1992, now U.S. Pat. No. 5,424,652; Ser. No. 08/192,391 filed Feb. 3, 1994, now U.S. Pat. No. 5,483,174; and, Ser. No. 08/137,675 filed Oct. 14, 1993, abandoned.

FIELD OF THE INVENTION

This invention relates to semiconductor manufacture and more particularly to a carrier suitable for holding and establishing electrical communication with an unpackaged semiconductor die. The carrier is especially useful in the manufacture and testing of known good semiconductor die (KGD).

BACKGROUND OF THE INVENTION

One of the fastest growing segments of the semiconductor industry is the manufacture of multi-chip modules (MCM). Multi-chip modules are being increasingly used in computers to form PC chip sets and in telecommunication items such as modems and cellular telephones. In addition, consumer electronic products such as watches and calculators typically include multi-chip modules.

With a multi-chip module, non-encapsulated or unpackaged dice (i.e., chips) are secured to a substrate (e.g., printed circuit board) using an adhesive. Electrical connections are then made directly to the bond pads on each die and to electrical leads on the substrate. In general, unpackaged dice cost less to manufacture than the equivalent packaged products. This is because the procedures for packaging semiconductor dice are complex and costly. Substantial cost savings are realized by eliminating packaging procedures.

However, because there is no package, procedures for testing the unpackaged dice are more difficult. With unpackaged dice semiconductor manufacturers are required to supply dice that have been tested and certified as known good die (KGD). Known-good-die (KGD) is a collective term that connotes unpackaged die having the same quality and reliability as the equivalent packaged product. This has led to a need in the art for manufacturing processes suitable for testing bare or unpackaged semiconductor die.

For test and burn-in of an unpackaged dice, a carrier replaces a conventional single chip package in the manufacturing process. The carrier typically includes an interconnect that allows a temporary electrical connection to be made between external test circuitry and the die. In addition, such a carrier must allow the necessary test procedures to be performed without damaging the die. The bond pads on a die are particularly susceptible to damage during the test procedure.

In response to the need for known good die (KGD), semiconductor manufacturers have developed carriers for testing unpackaged die. As an example, carriers for testing unpackaged die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., which are assigned to Micron Technology, Inc. Other test apparatus for unpackaged die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., which are assigned to Texas Instruments.

One of the key design considerations for a carrier is the method for establishing a temporary electrical connection with the bond pads on the die. With some carriers, the die is placed circuitry side down in the carrier and biased into contact with the interconnect. The interconnect contains the contact structure that physically aligns with and contacts the bond pads of the die. Exemplary contact structures include wires, needles, and bumps. The mechanisms for making electrical contact include piercing the native oxide of the bond pad with a sharp point, breaking or burnishing the native oxide with a bump, or moving across the bond pad with a contact adapted to scrub away the oxide. In general, each of these contact structures is adapted to form a low-resistance ohmic contact with the bondpad. Low-resistance refers to a resistance that is negligible. An ohmic contact is one in which voltage appearing across the contact is proportional to current flowing for both directions of flow.

Other design considerations for a carrier include electrical performance over a wide temperature range, thermal management, power and signal distribution, and the cost and reusability of the carrier. In addition, a carrier should be suitable for use with automated equipment and assembly procedures utilized in large scale semiconductor manufacture.

In view of the foregoing, it is an object of the present invention to provide an improved carrier adapted to test and burn-in an unpackaged die without damage to the die. It is a further object of the invention to provide an improved carrier for testing an unpackaged die, that is reusable, that is easy to assemble and disassemble, that provides efficient electrical coupling to contact locations on a die over a wide temperature range, and that can be used for testing different types of dice. It is a still further object of the present invention to provide a carrier useful in the manufacture of known good die that is compatible with automated equipment and processes used in the large scale manufacture of semiconductor dice. Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds.

SUMMARY OF THE INVENTION

In accordance with the present invention, a carrier for testing a discrete, unpackaged semiconductor die is provided. The carrier is adapted to retain a die under test (DUT) and provide a temporary electrical connection between the die and external test circuitry. This enables burn-in and other test procedures to be performed on the die.

Several different embodiments of carriers are provided. In general, each carrier embodiment includes a carrier base having external contacts connectable to test circuitry; a temporary interconnect in electrical communication with the external contacts on the carrier base and adapted to establish a temporary electrical connection with the die. In addition to the base and temporary interconnect, each carrier includes a force distribution mechanism for biasing the die and the interconnect together in the assembled carrier. The force distribution mechanism includes a bridge plate, a spring and a pressure plate. All of the elements of the carrier are designed to permit easy assembly and disassembly of the carrier and die.

The temporary interconnect for the carrier is formed in a configuration which accommodates a particular die bondpad configuration. This permits different types of interconnects to be interchangeable to allow testing of the different types of semiconductor dice using a universal carrier. The temporary interconnect includes raised contact members for penetrating into contact locations (e.g., bond pads, test pads) on the die. A pattern of conductive traces is formed on the interconnect in electrical communication with the contact members. Each conductive trace includes a contact pad, which in the assembled carrier, are used to establish an electrical path to external circuitry.

Different contact technologies can be employed to form the temporary interconnect and contact members. As an example, the interconnect includes a silicon substrate having raised silicon contact members with oxide-penetrating projections. Alternately, the interconnect includes a rigid substrate (e.g., ceramic, silicon) and thick film contact members formed by ultrasonic forging. As another alternate, the interconnect includes a rigid substrate having microbump contact members formed on an etched film. The microbump contact members can be formed with a rough textured surface for penetrating any native oxide present on the contact location.

For assembling the carrier with a die, a temporary interconnect having a configuration of contact members corresponding to the bond pads on the die is selected and placed on a support surface of the carrier base. An electrical path is then established between the contact members on the interconnect and external contacts on the carrier base. Several different arrangements an be employed to form the electrical path. Depending on the carrier embodiment, the electrical path can be formed using external contacts that abut the interconnect, using external contacts that clip to the interconnect, or by wire bonding the external contacts to the interconnect. In addition to providing an electrical path, the external contacts function in some embodiments as a retention mechanism for securing the interconnect to the carrier base. In embodiments wherein the interconnect is wire bonded, an adhesive is used to secure the interconnect to the carrier base.

During the assembly procedure, the die is initially attached to the force distribution mechanism, typically using a vacuum. Next, the die and temporary interconnect are optically aligned using a vision system, and the die is placed into abutting contact with the interconnect with a controlled or predetermined force. This causes the contact members on the interconnect to penetrate into the contact locations on the die and establish an electrical connection. At the same time, the force distribution mechanism is attached to the carrier base to bias the die and interconnect together. The external contacts on the assembled carrier are then attached to test circuitry and the die is tested using suitable test equipment (e.g., burn-in oven and circuitry). Following the test procedures, the carrier is disassembled and the tested die is removed from the carrier.

In a first embodiment of the invention the carrier base includes external contacts formed as retention contacts. In a second embodiment of the invention the carrier base includes external contacts formed as clips. In a third embodiment of the invention the carrier base includes external contacts formed as spring-like tines encased in a plastic body. In a fourth embodiment of the invention the carrier base includes external contacts that are wire bonded to the interconnect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exploded perspective view of a carrier constructed in accordance with the invention;

FIG. 2 is a cross section taken along section line 2--2 of FIG. 1;

FIG. 2A is a cross section taken along section line 2A--2A of FIG. 1;

FIG. 2B is a cross section equivalent to FIG. 2A of an alternate embodiment carrier having a wire bond option;

FIG. 3 is a plan view of a temporary interconnect for a carrier constructed in accordance with the invention;

FIG. 3A is a cross section view of a self-limiting silicon contact member in one embodiment of the interconnect of FIG. 3;

FIG. 3B is a cross sectional view of a thick film contact member in another embodiment of the interconnect of FIG. 3;

FIG. 3C is a cross sectional view of a microbump contact member in another embodiment of the interconnect of FIG. 3;

FIG. 3D is a cross sectional view of another microbump contact member in another embodiment of the interconnect of FIG. 3;

FIG. 3E is a cross sectional view equivalent to FIG. 3C of a microbump contact;

FIG. 3F is a cross sectional view equivalent to FIG. 3 of a microbump contact member with a rough plated surface;

FIG. 4 is a schematic view illustrating a procedure for aligning a die under test and the interconnect shown in FIG. 3 during assembly of a carrier constructed in accordance with the invention;

FIG. 5 is a plan view of an alternate embodiment carrier shown with a bridge plate component removed and having a retention mechanism with clip-like contacts that clip directly to the carrier base;

FIG. 5A is a cross section taken along section line 5A--5A of FIG. 5;

FIG. 5B is a cross section taken along section line 5B--5B of FIG. 5;

FIG. 6 is an exploded perspective view of an alternate embodiment carrier constructed in accordance with the invention with tine contacts embedded in a plastic body;

FIG. 7 is a perspective view of an alternate embodiment carrier having an interconnect that is wire bonded to external contacts on the carrier body;

FIG. 7A is a cross sectional view taken along section line 7A--7A of FIG. 7; and

FIG. 7B is a cross sectional plan view of the interconnect for the carrier shown in FIG. 7 shown with the force distribution mechanism and pressure plate removed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIGS. 1 and 2, a carrier 10 constructed in accordance with the invention is shown.

The carrier 10, generally stated, includes:

a carrier base 12 adapted to retain a die 14 for testing;

a temporary interconnect 16 adapted to establish electrical communication between the die 14 and test circuitry;

a retention mechanism in the form of retention contacts 18 mounted to the carrier base 12 and adapted to retain the interconnect 16 within the carrier base 12 while establishing an electrical pathway to the interconnect 16; and

a force distribution mechanism comprising a pressure plate 20, a spring 22 and a bridge plate 24 for biasing the die 14 against the interconnect 16 with an evenly distributed biasing force.

In the assembled carrier 10, the die 14 is placed circuitry (or bond pad side) down on the interconnect 16. The interconnect 16 fits within the carrier base 12 in electrical contact with the retention contacts 18. In addition, the die 14 is retained and biased into engagement with the interconnect 16 by the spring 22 acting through the pressure plate 20.

The carrier base 12 is a generally rectangular shaped block, formed of an insulative, heat-resistant material such as a ceramic or a high temperature molded plastic. The carrier base 12 is designed to be placed in a burn-in oven or other test fixture for testing the die 14. The carrier base 12 has a hollowed out interior portion which includes a cavity 26. The carrier base 12 also includes a pair of integrally formed lugs 28, 30 on either side. The lugs 28, 30 include elongated through slots 32, that extend almost from end to end of the carrier, and function to facilitate assembly of the retention contacts 18 with the carrier base 12. In addition, the lugs 28, 30 include through openings 34 for handling and securing the carrier base 12 to various assembly and test equipment.

As shown in FIGS. 2 and 2A, the carrier 10 includes a bottom plate 31 that is removably mounted to the carrier base 12. A pair of clips 36 attached to the carrier base 12 secures the bottom plate 31 to the carrier base 12. The interconnect 16 is mounted to a support surface 17 of the bottom plate 31.

As also shown in FIGS. 2 and 2A, the force distribution mechanism includes the pressure plate 20, spring 22 and bridge plate 24. The pressure plate 20 is a rigid plate having an outer peripheral configuration that matches or is slightly larger that of the die 14. The pressure plate 20 includes an opening 38 which is used in the assembly of the carrier 10. As will be further explained, during assembly of the carrier 10, the opening 38 is used as a conduit for a vacuum to attach the die 14 to the pressure plate 20.

The clips 36 on the carrier base 12, in addition to securing the bottom plate 31 to the carrier base 12, also secure the bridge plate 24 to the carrier base 12. In the assembled carrier, the spring 22 is sandwiched between the bridge plate 24 and pressure plate 20 and exerts a spring force on the pressure plate 20. This spring force is evenly distributed by the pressure plate 20 over the back surface of the die 14 and biases the die 14 against the interconnect 16.

The spring 22 can be formed as a wave washer, a cylindrically curved washer, a belleville washer, a compression spring or a canted coil spring. These types of springs are commercially available from manufacturers such as ASMCO, Fairfield, N.J. and Bal Seal Engineering Company, Santa Ana, Calif.

Interconnect

Referring now to FIG. 3, the temporary interconnect 16 is shown separately. The interconnect 16 includes a substrate 50 having raised contact members 52. Each contact member 52 is connected to an electrically conductive trace 54. A contact pad 56 is formed at the end of each conductive trace 54. The raised contact members 52 are adapted to contact the bond pads 48 of the die 14 and form an electrical connection that is low resistance and ohmic. The electrically conductive traces 54 are in electrical communication with the contact members 52 and are adapted to conduct electrical signals to and from the contact members 52 and 56. In the assembled carrier 10, the contact pads 56 on the conductive traces 54 are abutted by the retention contacts 18 (FIG. 1).

The contact members 52 on the interconnect 16, are spaced in a pattern that corresponds to the placement of the bond pads 48 (FIG. 3A) on the die 14. The interconnect 16 shown in FIG. 3 is for a die having bond pads 48 formed along each end (i.e., end connect). The bond pads 48 are embedded in a protective layer 72 (FIG. 3A). Since the interconnect 16 is removable from the carrier 10, other interconnect configurations may be provided for other die bond pad configurations (e.g., peripheral, array, edge connect, lead over chip (LOC)). This permits carriers to be "universal" rather than "dedicated" to a particular die configuration.

FIGS. 3A-3D illustrate four different embodiments of the interconnect 16. In a first embodiment of the interconnect, shown in FIG. 3A, the interconnect 16A includes a silicon substrate 50A having raised contact members 52A formed with a self limiting feature as described below. Each contact member 52A is formed as a raised mesa or pillar that projects vertically upward from a surface of the silicon substrate 50A. In addition, each contact member 52A includes one or more raised projections 58 which extend from tip portions 60 of the contact member 52A. The raised projections 58 are adapted to penetrate the bond pads 48 of the die 14 and pierce through any native oxide on the bond pads to form an ohmic contact. At the same time a top surface 62 of the contact member 52A limits the penetration depth of the raised projections 58 into the bond pad 48. The height of the raised projections 58 is selected to be less than the depth "A" of a bond pad 48 (e.g., height=1/5 to 4/5 of A). This arrangement permits a metal oxide layer of the bond pad 48 to be pierced through and an ohmic contact to be established while at the same time minimizing damage to the bond pad 48. The raised projections 58 of the contact member 52A may be formed as knife edges, sharp apexes, conical points or with other suitable piercing structures. In addition, the raised projections 58 may be formed directly on the substrate 50A rather than on a raised contact member 52A. In that case, the surface of the substrate 50A would limit the bond pad penetration depth of the contact member 52A.

One suitable process for forming the contact members 52A as pillars having raised projections is disclosed in U.S. Pat. No. 5,326,428 entitled "Method For Testing Semiconductor Circuitry For Operability And Method Of Forming Apparatus For Testing Semiconductor Circuitry For Operability", which is incorporated herein by reference.

The contact members 52A of the interconnect 16A include an electrically conductive layer 64 formed of a metal or metal-silicide layer. The conductive layer 64 is electrically connected to an electrically conductive trace 54A formed on the silicon substrate 50A. The conductive traces 54A may be formed on the silicon substrate 50A utilizing semiconductor circuit fabrication techniques. As an example, the conductive traces 54A may be formed of a conductive metal (e.g., aluminum, copper, or a refractory metal) by deposition, plating, patterning and etching. As another example, the conductive traces 54A may be formed of polysilicon deposited and then suitably patterned. An insulating layer 66 (e.g., SiO.sub.2) formed on the substrate 50A provides electrical isolation for the traces 54A and tips 64.

Each conductive trace 54A terminates in a contact pad 56 (FIG. 3) formed along a longitudinal edge of the substrate 50A. The contact pads 56 are formed as a metal pad using a suitable pad metallurgy. In the assembled carrier 10 and as clearly shown in FIG. 2A, the retention contacts 18 abut the contact pads 56. This retains the interconnect 16 and establishes an electrical pathway through the retention contacts 18, through the conductive traces 54, through the contact members 52 and to the bond pads 48 of the die 14. Alternately, as shown in FIG. 2B, a carrier 10A may be assembled with the interconnect 16 wire bonded to the retention contacts 18A using thi