ATM cell assembly and disassembly device with enhanced data handling flexibility

What is claimed is:

1. An asynchronous transfer mode (ATM) cell assembly device for obtaining an ATM cell flow by assembling ATM cells from input data, comprising:

buffer means for temporarily storing the input data, from which stored data are outputted when an amount of the stored data becomes not less than a prescribed data amount sufficient for loading a payload section of each ATM cell; and

cell assembly means for assembling each ATM cell by loading the stored data outputted from the buffer means into the payload section and attaching a header section to the payload section, and then for outputting each assembled ATM cell when the stored data outputted from the buffer means are received and for outputting an empty cell when the stored data outputted from the buffer means are not received.

2. The device of claim 1, wherein the input data are entered in forms of synchronous transfer mode (STM) signals formed from a plurality of frames, where each frame is divided into a plurality of time slots, and the device further comprises data input means for extracting selected ones of the time slots in each frame of the STM signals as the input data and storing the extracted input data into the buffer means.

3. The device of claim 1, wherein the input data are entered in forms of synchronous transfer mode (STM) signals formed from continuous bit rate (CBR) signals with an arbitrary speed.

4. The device of claim 1, wherein the buffer means comprises a first-in first-out (FIFO) memory formed by a dual port RAM, to which the input data are stored at operation cycles of an input side from which the input data are entered, and from which the stored data are outputted at operation cycles of an output side to which the ATM cell flow is to be outputted.

5. The device of claim 1, wherein the cell assembly means includes means for generating the empty cells to be outputted when the stored data outputted from the buffer means are not received.

6. The device of claim 1, wherein the cell assembly means includes means for measuring the amount of the stored data in the buffer means at ATM cell output cycles, in accordance with which the cell assembly means acquires the stored data from the buffer means.

7. The device of claim 1, wherein the cell assembly means uses a partial filling scheme and includes dummy pattern output means for generating a dummy pattern to be filled into a remaining portion of a partially filled payload section in each ATM cell after the stored data are loaded.

8. An asynchronous transfer mode (ATM) cell assembly device for obtaining an ATM cell flow by assembling ATM cells from input data, comprising:

encoding means for obtaining the input data by encoding data to be transmitted as the ATM cells;

buffer means for temporarily storing the input data obtained by the encoding means;

output permission means for issuing an output permission signal permitting an output of the input data stored in the buffer means in accordance with usage parameter control (UPC) parameters determined at a time of call set up, where the buffer means is allowed to output the input data stored therein only when the output permission signal is received from the output permission means; and

cell assembly means for assembling each ATM cell by loading the stored input data outputted from the buffer means into a payload section and attaching a header section to the payload section, and outputting the ATM cell flow containing the assembled ATM cells.

9. The device of claim 8, wherein the buffer means controls either one of an encoding speed of the encoding means by which the encoding means encodes the data and an input data output speed of the encoding means by which the encoding means outputs the input data, according to one of an amount of the input data currently stored therein and a buffer capacity currently remaining therein.

10. The device of claim 9, wherein the buffer means controls said one of the encoding speed and the input data output speed of the encoding means such that said one of the encoding speed and the input data output speed of the encoding means is decreased when the amount of the input data currently stored in the buffer means becomes greater than a predetermined threshold, or when the capacity currently remaining in the buffer means becomes less than another predetermined threshold, and said one of the encoding speed and the input data output speed of the encoding means is increased when the amount of the input data currently stored in the buffer means becomes less than said predetermined threshold, or when the capacity currently remaining in the buffer means becomes greater than said another predetermined threshold.

11. The device of claim 8, wherein the buffer means outputs insignificant data different from the input data to be transmitted as said assembled ATM cells when the output permission signal is received from the output permission means when a sufficient amount of the input data are not stored therein, and the cell assembly means outputs one of an empty cell, a signaling cell, and an OAM (Operation, Administration, and Maintenance) cell when the insignificant data are outputted from the buffer means.

12. An asynchronous transfer mode (ATM) cell disassembly device for obtaining output signals from entered ATM cell flow by disassembling ATM cells, comprising:

ATM processing means for extracting output data to be outputted as the output signals from the ATM cells;

buffer means for temporarily storing the output data extracted by the ATM processing means, the output data being supplied from the ATM processing means to the buffer means and stored in the buffer means when a capacity of the buffer means currently remaining becomes not less than an amount of data loaded in a payload section of each ATM cell; and

output processing means for obtaining the output signals from the output data outputted from the buffer means, and outputting the obtained output signals.

13. The device of claim 12, wherein the ATM processing means further comprises:

filter unit for extracting selected ATM cells which have a specific cell header pattern among the ATM cells of the entered ATM cell flow;

jitter absorption buffer unit for temporarily storing at least a part of the selected ATM cells extracted by the filter unit; and

AAL processing unit for extracting the output data from said at least a part of the selected ATM cells stored in the jitter absorption buffer unit and outputting the extracted output data to the buffer means.

14. The device of claim 13, wherein the storing of said at least a part of the selected ATM cells from the filter unit into the jitter absorption buffer unit starts from one of the selected ATM cells whose adaptation layer header has a synchronization bit in an ON state.

15. The device of claim 13, wherein said at least a part of the selected ATM cells are taken out from the jitter absorption buffer unit by the AAL processing unit after an elapse of a prescribed time period since a start of the storing of said at least a part of the selected ATM cells or after a prescribed number of said at least a part of the selected ATM cells are stored from the filter unit to the jitter absorption buffer unit, so as to absorb jitters in cell arrival cycles of the ATM cells.

16. The device of claim 13, wherein the AAL processing unit includes means for measuring the capacity currently remaining in the buffer means at cell arrival cycles of the ATM cells.

17. The device of claim 13, wherein the AAL processing unit includes error recovery means for detecting and correcting cell loss and cell misinsertion errors in the entered ATM cell flow.

18. The device of claim 12, wherein the output signals are synchronous transfer mode (STM) signals formed from a plurality of frames, where each frame is divided into a plurality of time slots, and the output processing means obtains the output signals by loading the output data into the time slots in each frame of the STM signals.

19. The device of claim 12, wherein the STM signals are formed from continuous bit rate (CBR) signals with an arbitrary speed.

20. The device of claim 12, wherein the buffer means comprises a first-in first-out (FIFO) memory formed by a dual port RAM, to which the input data are stored at operation cycles of an input side from which the ATM cell flow is entered, and from which the stored data are outputted at operation cycles of an output side to which the output signals are to be outputted.

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an ATM cell assembly and disassembly device for assembling and disassembling the ATM cells carrying the data used in the ATM communication system.

2. Description of the Background Art

In recent years, in order to deal with the demands for variety of communications such as image communication and high speed data communication, the construction of the B-ISDN (Broadband-Integrated Service Digital Network) is in progress as an integrated communication network for facilitating efficient and flexible communication services. In a realization of the B-ISDN, the ATM (Asynchronous Transfer Mode) data exchange scheme is expected to play a key role. The ATM data exchange scheme is a scheme in which the data are loaded into a packet of a fixed length called ATM cell regardless of their attributes, and the communication service is realized by using such an ATM cell as a unit of data exchange.

In a conventional communication system, the packet assembly scheme has been applicable only to a kind of communication data which requires no real-time processing such as those for the usual data communication, so that a new packet assembly scheme is needed for the communication of the real-time data such as speech data and image data.

As such an ATM cell assembly scheme for the real-time data, there are propositions of: (a) a scheme for assembling an ATM cell by accumulating the successively entered real-time input data in a buffer, and attaching an ATM header to the accumulated data when a total amount of input data accumulated in the buffer reaches a predetermined amount such as that corresponding to a length of a payload section in each ATM cell to be assembled or a partially filling number for a payload section in each ATM cell to be assembled; and (b) a scheme in which a ratio of a speed of the input data and a transmission speed on the ATM side is determined in advance, and a cycle for outputting the ATM cell assembled from the input data and a cycle for outputting other cells such as empty cells are sequentially controlled to satisfy the predetermined transmission speed on the ATM side.

However, in scheme (a), the ATM cell generation cycle is going to be synchronous with the cycle of input data, so that it becomes necessary to provide a speed matching buffer for matching the transmission speed of the generated ATM cells with that suitable for the ATM side interface on the downstream side of the ATM cell assembly device, but this requirement leads to a considerable increase of the amount of hardware required for the communication system.

On the other hand, in scheme (b), it is impossible to provide a flexibility in the set up of the speed of the input data, so that a type of the input data that can be handled in the communication system is going to be restricted in view of the speed of the input data.

Now, one of the characterizing feature of the ATM communication scheme is the improvement of the network utilization efficiency based on the statistical multiplexing effect due to the label multiplexing of the cells on the transmission path. To this end, the ATM communication scheme requires a resource management which is not required in the conventional communication scheme.

More specifically, in order to share the resource in the network by the label multiplexing, each terminal which initiates the communication by making a call set up request reports parameters such as the peak rate and the average rate of the requested call as the UPC (Usage Parameter Control) parameters to the network. Then, the network carries out the resource management by making the judgement as to whether it is possible to guarantee the quality of service required to the network when the requested call is admitted or not according to the predetermined evaluation function, and then admitting the requested call only when it is judged that the required quality of service can be guaranteed even when the requested call is admitted. The terminal for which the requested call has been admitted in this manner should output the cells for the communication by observing the UPC parameters reported at a time of the call set up request, in order to prevent the outputted cells from being discarded by the policing function adopted in the network side.

This observance of the UPC parameters on the terminal side is usually achieved by modifying the cell traffic to be transmitted into a modified traffic satisfying the UPC parameters, and then outputting this modified traffic to the transmission path. This operation on the terminal side is called traffic shaping.

This traffic shaping has conventionally been achieved by a configuration shown in FIG. 1 in which the ATM cell flow generated at the ATM encoding and cell generation unit 501 is stored in a shaping buffer 502 once, and the ATM cells are taken out from this shaping buffer 502 under the control of a shaping controller 503 in accordance with the UPC parameters determined at a time of the call set up, and outputted to the transmission path. As the algorithm to be used by the shaping controller 503 in realizing such a traffic shaping, the leaky bucket algorithm and the sliding window algorithm are conventionally known.

In this manner, in the conventional communication scheme, the communication is realized in a form observing the UPC parameters by applying the traffic shaping on the cell flow outputted from the terminal before transmitting to the transmission path. However, in this conventional communication scheme, there is a possibility for the cells to be discarded at the shaping buffer 502. Namely, in the case the ATM encoding and cell generation unit 501 continually carries out the ATM encoding at a rate close to the peak speed, because the shaping buffer 502 can output the cells only at a constant rate, the amount of cells entered from the ATM encoding and cell generation unit 501 to the shaping buffer 502 may exceed the amount of cells outputted from the shaping buffer 502 to the transmission path, such that the overflow of the entered cells may occur at the shaping buffer 502.

As a solution to this problem of the shaping buffer overflow, the increasing of the capacity of the shaping buffer itself gives rise to another concern regarding the increase of the amount of hardware.

Also, in the ATM communication scheme, the communication service is expected to be charged in proportion to the peak rate used in the communication, so that the user will normally desire to suppress the peak rate to be used in the communication as low as possible in order to minimize the communication cost. In order to realize such a communication with the suppressed peak rate, the call set up request to the network should be made with a low peak rate and a peak rate value in the traffic shaping operation should be set to be low during the communication. Here, it possible for the peak rate used in the ATM encoding and cell generation unit 501 to exceed the peak rate used in the shaping buffer 502, and in such a case, depending on the encoding speed at the ATM encoding and cell generation unit 501, the shaping buffer 502 needs to accumulate a large number of cells, so that the large capacity is required for the shaping buffer 502, but this requirement also leads to the concern regarding the increase of the amount of hardware.

On the other hand, in the ITU-T (International Telecommnications Union-Telecommnication sector; formerly CCITT (The Consultative Committee for International Telegraph and Telephone)), the following schemes for preventing the deterioration of the congestion of the network are considered.

(a) The network attaches a flag for notifying the occurrence of the congestion to the user cell at the congested point in the network, the receiver side user receiving this user cell with this flag attached requests the transmitter side user to suppress the amount of transmission in response to this flag, and the transmitter side user suppresses the amount of transmission in accordance with this request from the receiver side user. This scheme is called the congestion control using FECN (Forward Explicit Congestion Notification).

(b) The network transmits a congestion notification cell from the congested point in the network to the transmitter side user, to request the suppression of the amount of transmission, and the transmitter side user suppresses the amount of transmission in response to this congestion notification cell. This scheme is called the congestion control using BECN (Backward Explicit Congestion Notification).

(c) The receiver side user recognizes the occurrence of the congestion of the network by detecting the cell loss due to the congestion, and requests the transmitter side user to suppress the amount of transmission, and the transmitter side user suppresses the amount of transmission in accordance with this request.

In any of these schemes, the transmitter side user to which the suppression of the amount of transmission is requested is expected to suppress the amount of transmission by controlling the shaping controller 503 to lower the parameters such as the peak rate and the average rate of the transmission traffic. However, in this case, the encoding speed at the ATM encoding and cell generation unit 501 is also required to be lowered in conjunction with the change of the parameters at the shaping controller 503, because otherwise the cells entering from the ATM encoding and cell generation unit 501 can exceed the cells outputted from the shaping buffer 502 to cause the shaping buffer overflow. Yet, such a changing of the parameters on both of the shaping controller 503 and the ATM encoding and cell generation unit 501 is going to be complicated as well as relatively slow because it calls for the parameter changing operations to be made at more than one parts in the configuration of FIG. 1.

Now, on the other hand, the ATM cell disassembly device is a device for recovering the data from the ATM cell obtained by the ATM cell assembly device. In this ATM cell disassembly device, in order to deal with the cell loss in the ATM communication network and the jitter in the cell arrival intervals called CDV (Cell Delay Variation), it is indispensable to provide a mechanism for absorbing and compensating these loss and CDV.

As a conventional scheme for the ATM cell disassembly for the real-time data, there is a scheme using a configuration shown in FIG. 2 in which the ATM cells received at an ATM processing unit 901 are pooled in a large capacity jitter absorption buffer 902 once, and the pooled ATM cells are taken out from this jitter absorption buffer 902 to an STM (Synchronous Transfer Mode) processing unit 903 at regular intervals, so as to absorb the jitter in the cell arrival intervals. Here, in a case the cell loss or the erroneous cell transmission is involved, the interpolation using dummy cell or dummy cell data and the discarding of the erroneously transmitted cell are carried out at either input or output side of the jitter absorption buffer 902.

Then, either at the output side of the jitter absorption buffer 902 or at the jitter absorption buffer 902 itself, the transfer to the receiver side clock is made, the necessary data obtained by removing unnecessary sections such as the header from the ATM cell are transmitted to the receiver side.

Here, in a case the operation frequency of the receiver side is predetermined, the ATM cell disassembly can be achieved by setting the timing to take out the cell from the jitter absorption buffer 902 to be equal to this operation frequency of the receiver side. However, in this scheme, the speed of the data outputted from the ATM cell disassembly device is predetermined and it is impossible to flexibly realize the various different speeds for the output data, or to flexibly deal with a case in which the receiver side comprises STM time slots whose number can vary in time.

Thus, the conventional ATM cell disassembly scheme lacks the flexibility as it fixes the ratio of the data input and output speeds to a predetermined ratio.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide an ATM cell assembly device capable of flexibly obtaining the ATM cell flow with any desired cell cycles, without being restricted by the speed of the input data and requiring an additional hardware such as a speed matching buffer.

It is another object of the present invention to provide an ATM cell assembly device capable of preventing the buffer overflow while achieving the desired traffic shaping, without significantly increasing the amount of hardware.

It is another object of the present invention to provide an ATM cell disassembly device capable of flexibly dealing with various data speeds.

According to one aspect of the present invention there is provided an asynchronous transfer mode (ATM) cell assembly device for obtaining an ATM cell flow by assembling ATM cells from input data, comprising: buffer means for temporarily storing the input data, from which stored data are outputted when an amount of the stored data becomes not less than a prescribed data amount sufficient for loading a payload section of each ATM cell; and cell assembly means for assembling each ATM cell by loading the stored data outputted from the buffer means into the payload section and attaching a header section to the payload section, and outputting the ATM cell flow containing the assembled ATM cells when the stored data outputted from the buffer means are received and other cells otherwise.

According to another aspect of the present invention there is provided an asynchronous transfer mode (ATM) cell assembly device for obtaining an ATM cell flow by assembling ATM cells from input data, comprising: encoding means for obtaining the input data by encoding data to be transmitted as the ATM cells; buffer means for temporarily storing the input data obtained by the encoding means; output permission means for issuing an output permission signal permitting an output of the input data stored in the buffer means in accordance with usage parameter control (UPC) parameters determined at a time of call set up, where the buffer means is allowed to output the input data stored therein only when the output permission signal is received from the output permission means; and cell assembly means for assembling each ATM cell by loading the stored input data outputted from the buffer means into a payload section and attaching a header section to the payload section, and outputting the ATM cell flow containing the assembled ATM cells.

According to another aspect of the present invention there is provided an asynchronous transfer mode (ATM) cell disassembly device for obtaining output signals from entered ATM cell flow by disassembling ATM cells, comprising: ATM processing means for extracting output data to be outputted as the output signals from the ATM cells; buffer means for temporarily storing the output data extracted by the ATM processing means, to which output data are stored from the ATM processing means when a capacity of the buffer means currently remaining becomes not less than an amount of data loaded in a payload section of each ATM cell; and output processing means for obtaining the output signals from the output data outputted from the buffer means, and outputting the obtained output signals.

Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of an example of a conventional ATM cell assembly device.

FIG. 2 is a schematic block diagram of an example of a conventional ATM cell disassembly device.

FIG. 3 is a schematic block diagram of a first embodiment of an ATM cell assembly device according to the present invention.

FIG. 4 is a schematic block diagram of a second embodiment of an ATM cell assembly device according to the present invention.

FIG. 5 is a block diagram of an STM processing unit in the ATM cell assembly device of FIG. 4.

FIG. 6 is a timing chart for the STM signals and the frame synchronization signal entered into the ATM cell assembly device of FIG. 4.

FIG. 7 is a diagrammatic illustration of stored data format in the buffer unit in the ATM cell assembly device of FIG. 4.

FIG. 8 is a diagram of an ATM processing unit in the ATM cell assembly device of FIG. 4.

FIG. 9 is a flow chart for the ATM cell assembling operation in the ATM cell assembly device of FIG. 4 in the case when the partial filling is not used.

FIG. 10 is a flow chart for the ATM cell assembling operation in the ATM cell assembly device of FIG. 4 in the case when partial filling is used.

FIGS. 11A and 11B are diagrammatic illustrations of 2 bytes and 1 byte AAL/SAR headers, respectively, used in the ATM cell assembly device of FIG. 4.

FIG. 12 is a schematic block diagram of a third embodiment of an ATM cell assembly device according to the present invention.

FIG. 13 is a diagram of an ATM cell assembly unit in the ATM cell assembly device of FIG. 12.

FIG. 14 is a block diagram of one possible modified configuration for the third embodiment of an ATM cell assembly device according to the present invention.

FIG. 15 is a block diagram of another possible modified configuration for the third embodiment of an ATM cell assembly device according to the present invention.

FIG. 16 is a schematic block diagram of one embodiment of an ATM cell disassembly device according to the present invention.

FIG. 17 is a diagram of an ATM processing unit in the ATM cell disassembly device of FIG. 16.

FIG. 18 is a diagrammatic illustration of the data format for the ATM cell used in the ATM cell disassembly device of FIG. 16.

FIG. 19 is a diagrammatic illustration of stored data format in the buffer unit in the ATM cell disassembly device of FIG. 16.

FIG. 20 is a diagram of an AAL processing unit in the ATM processing unit of FIG. 17.

FIG. 21 is a diagram of an error recovery unit in the AAL processing unit of FIG. 20.

FIG. 22 is a diagrammatic illustration of a state machine for an AAL operation unit in the error recovery unit of FIG. 21.

FIG. 23 is a circuit diagram of an SNP/parity calculation circuit to be provided in the AAL operation unit in the error recovery unit of FIG. 21.

FIGS. 24A and 24B are diagrammatic Illustrations of 1 byte and 2 bytes adaptation layer headers, respectively, used in the ATM cell disassembly device of FIG. 16.

FIG. 25 is a table summarizing the window control scheme to be utilized in a cell arrival order control in the ATM cell disassembly device of FIG. 16.

FIG. 26 is a diagram of an output processing unit in the ATM cell disassembly device of FIG. 16.

FIG. 27 is a flow chart for the algorithm to be executed by a re-assembly unit in the AAL processing unit of FIG. 20.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 3, a first embodiment of an ATM cell assembly device according to the present invention will be described in detail.

This ATM cell assembly device of the first embodiment shown in FIG. 3 is capable of connecting a plurality of already existing communication devices such as telephones, TVs, computers, etc., to the ATM network, and generally comprises: a multiplexing unit 800 receiving input data from a plurality (three in FIG. 3) input lines 812, 813, and 814 connected with already existing communication devices (not shown); a buffer unit 805, connected with an output of the multiplexing unit 800, for temporarily storing the output of the multiplexing unit 800; and an ATM cell processing unit 808, connected with an output of the buffer unit 805, for obtaining the desired ATM cell flow to be outputted to a transmission path 815.

The multiplexing unit 800 includes memories 801, 802, and 803 for storing the input data received from the input lines 812, 818, and 814, respectively, and a memory controller 804 for selectively outputting the input data stored in the memories 801, 802, and 803.

The buffer unit 805 includes a buffer 806 for temporarily storing the selected input data outputted from the multiplexing unit 800 in correspondence to each of the input lines 812, 813, and 814, and a buffer controller 807 for controlling a data output timing of the buffer 806 such that the accumulated data are read out to the ATM cell processing unit 808 when the amount of input data accumulated for each of the input lines 812, 813, and 814 reaches to a predetermined level appropriate for a payload section of the ATM cell to be assembled.

The ATM cell processing unit 808 includes a cell assembler 809 for assembling an ATM cell by attaching a header section to the accumulated data outputted from the buffer 806 of the buffer unit 805, an empty cell generator 810 for generating empty cells, and a selector 811 for selectively outputting the ATM cell obtained by the cell assembler 809 and the empty cells generated by the empty cell generator 810 to the transmission path 815. Here, the selector 811 selectively outputs the ATM cell obtained by the cell assembler 809 whenever the ATM cell is assembled by the cell assembler 809, and the empty cells generated by the empty cell generator 810 otherwise.

In other words, in this ATM cell assembly device of FIG. 3, whenever the valid ATM cell is not available, the empty cells are filled in, so as to obtain the full ATM cell flow with desired cell cycles.

Thus, in this ATM cell assembly device of FIG. 3, the desired ATM cell flow with desired cell cycles can be obtained by assembling the ATM cell from the input data entered at an arbitrary speed, without being restricted by the speed of the input data and requiring an additional hardware such as a speed matching buffer.

In addition, normally, it can be expected that the operation speed on the ATM network side is faster than the operation speed on the already existing communication device side, so that it can be considered as highly unlikely for the buffer 806 to store more than a certain amount of input data and therefore its capacity can be relatively small, which also contributes to the reduction of the amount of hardware.

Referring now to FIG. 4, a second embodiment of an ATM cell assembly device according to the present invention will be described in detail.

This ATM cell assembly device of the second embodiment shown in FIG. 4 is for obtaining the ATM cell flow from the STM signals such as the telephone signals. In principle, the STM signals comprises a plurality of time slots to which each frame has been divided in time, and the ATM cell is assembled by selectively extracting several slots from the STM signals and loading them into a payload section of the ATM cell, and attaching the header section.

In this second embodiment, the ATM cell assembly device generally comprises: an STM processing unit 11 for receiving the externally supplied STM signals; a buffer unit 12 connected with the STM processing unit 11 for temporarily storing the output of the STM processing unit 12; an ATM processing unit 13 connected with the buffer unit 12 for obtaining the ATM cell flow from the output of the buffer unit 12; and a control unit 14 for controlling the operations of the STM processing unit 11, the buffer unit 12, and the ATM processing unit 18 in a manner described in detail below.

The STM processing unit 11 extracts the input data to be transmitted as the ATM cells from the entered STM signals, and outputs the extracted input data to the buffer unit 12, while also outputting the synchronization information regarding the STM frame synchronization, i.e., the information indicating a head of each STM frame, to the buffer unit 12.

The buffer unit 12 comprises a dual port RAM (2P-RAM), and functions as a FIFO (First-In First-Out) memory. In addition, this buffer unit 12 also has a function of speed conversion (clock conversion) between the speed on the STM side and the speed on the ATM side.

The ATM processing unit 13 assembles the ATM cell by loading the input data taken out from the buffer unit 12 into the payload section of the ATM cell and attaching the header section, and outputs the obtained ATM cells to the ATM network side. In addition, this ATM processing unit 18 also has a function of outputting the empty cells to the ATM network side whenever the valid ATM cell to be outputted is absent.

In further detail, the STM processing unit 11 has a detailed configuration as shown in FIG. 5, which comprises an STM frame processor 101 receiving the STM signals along with the synchronization signal and the STM bit clock, and a buffer interface 102 for outputting the data and the synchronization information to the buffer unit 12. Here, the STM signals externally supplied to this STM processing unit 11 can be the 8 bit parallel data for example, and each frame of the STM signals may be divided into 32 STM time slots for example. The STM signals can also be the CBR (Continuous Bit Rate) signals having arbitrary speed.

In a case where the signals with each frame divided into 32 STM time slots are entered as the STM signals, a frame synchronization signal indicating a head of each frame is also entered along with the STM signals for each frame, as indicated in the timing chart of FIG. 6. On the other hand, in a case the CBR signals having arbitrary speed are entered as the STM signals, there is no need to enter this kind of the signal indicating a head of a frame. In this second embodiment, a case of the signals with each frame divided into 32 STM time slots will be referred to as an STM frame mode, while a case of the CBR signals with arbitrary speed will be referred to as a CBR mode, to distinguish these two cases. Either one of these modes can be selected freely from the external as well as from the control unit 14.

In the STM frame mode, the STM frame processor 101 extracts the data of those time slots which are specified by the control unit 14 in advance from each STM frame, and outputs the extracted data to the buffer interface 102. In addition, when the frame synchronization signal is detected along with the STM signals, the synchronization information in a form of the detected frame synchronization signal is also outputted to the buffer interface 102.

In the CBR mode, the STM frame processor 101 disregards the STM frames in the entered STM signals, and outputs all the data in the entered STM signals to the buffer interface 102. In addition, when the synchronization signal of some kind is detected along with the STM signals, the synchronization information in a form of the detected synchronization signal is also outputted to the buffer interface 102.

The buffer interface 102 receives the data in the STM signals and the synchronization information from the STM frame processor 101 and outputs them together to the buffer unit 12.

The buffer unit 12 is the FIFO memory formed by the dual port RAM as already mentioned above, and has the capacity of storing the data for two to three ATM cells. This buffer unit 12 writes the data outputted from the STM processing unit 11 at a clock on the STM side, and reads the stored data to the ATM processing unit 13 at a clock on the ATM side. In this buffer unit 12, the data of the STM signals and the synchronization information are stored in correspondence with each other, in a format indicated in FIG. 7.

On the other hand, the ATM processing unit 13 has a detailed configuration as shown in FIG. 8, which comprises a sequencer 201, a FIFO stored data measurement unit 202, a buffer interface 203, a header pattern output unit 204, a dummy pattern output unit 205, a selector 206, an empty cell pattern output unit 207, a selector 208, and a register processing unit 209, each of which will now be described.

This ATM processing unit 13 carries out the sequential operations for processing each ATM cell in the ATM cell cycles according to the sequencer 201, where each ATM cell cycle is equal to 53 clock cycle in this case as the internal circuit is operating in the 8 bit parallel mode.

The FIFO stored data amount measurement unit 202 is a module for constantly measuring the data amount such as the number of words currently stored in the buffer unit 12 in real-time, and outputting the result of the measurement to the register processing unit 209.

The buffer interface 203 has a function of acquiring the data from the buffer unit 12 in accordance with the command from the register processing unit 209, and supplying them to the selector 206.

The header pattern output unit 204 is a module for generating a header pattern for the ATM cell to be assembled, where the header pattern to be generated includes the ATM cell header and the AAL/SAR (ATM Adaptation Layer/Segmentation And Re-assembly sub-layer) header. In this second e